1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Startup Code for MIPS32 CPU-core
5 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
8 #include <asm-offsets.h>
11 #include <asm/regdef.h>
12 #include <asm/mipsregs.h>
14 #ifndef CONFIG_SYS_INIT_SP_ADDR
15 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
16 CONFIG_SYS_INIT_SP_OFFSET)
24 # define STATUS_SET ST0_KX
30 MTC0 zero, CP0_WATCHLO,\sel
31 mtc0 t1, CP0_WATCHHI,\sel
32 mfc0 t0, CP0_WATCHHI,\sel
37 .macro uhi_mips_exception
38 move k0, t9 # preserve t9 in k0
39 move k1, a0 # preserve a0 in k1
40 li t9, 15 # UHI exception operation
41 li a0, 0 # Use hard register context
42 sdbbp 1 # Invoke UHI operation
47 PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
48 and sp, t1, t0 # force 16 byte alignment
50 sp, sp, GD_SIZE # reserve space for gd
51 and sp, sp, t0 # force 16 byte alignment
52 move k0, sp # save gd pointer
53 #if CONFIG_VAL(SYS_MALLOC_F_LEN) && \
54 !CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F)
55 li t2, CONFIG_VAL(SYS_MALLOC_F_LEN)
57 sp, sp, t2 # reserve space for early malloc
58 and sp, sp, t0 # force 16 byte alignment
70 #if CONFIG_VAL(SYS_MALLOC_F_LEN) && \
71 !CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F)
72 PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
79 * Do not add instructions to the branch delay slot! Some SoC's
80 * like Octeon might patch the final U-Boot binary at this location
81 * with additional boot headers.
86 #if defined(CONFIG_MIPS_INSERT_BOOT_CONFIG)
88 * Store some board-specific boot configuration. This is used by some
89 * MIPS systems like Malta.
92 .word CONFIG_MIPS_BOOT_CONFIG_WORD0
93 .word CONFIG_MIPS_BOOT_CONFIG_WORD1
96 #if defined(CONFIG_ROM_EXCEPTION_VECTORS)
98 * Exception vector entry points. When running from ROM, an exception
99 * cannot be handled. Halt execution and transfer control to debugger,
100 * if one is attached.
103 /* TLB refill, 32 bit task */
107 /* XTLB refill, 64 bit task */
111 /* Cache error exception */
115 /* General exception */
119 /* Catch interrupt exceptions */
123 /* EJTAG debug exception */
131 mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing
132 #if __mips_isa_rev >= 6
133 mfc0 t0, CP0_CONFIG, 5
134 and t0, t0, MIPS_CONF5_VP
139 mfc0 t0, CP0_GLOBALNUMBER
142 #ifdef CONFIG_ARCH_BMIPS
143 1: mfc0 t0, CP0_DIAGNOSTIC, 3
144 and t0, t0, (1 << 31)
146 1: mfc0 t0, CP0_EBASE
147 and t0, t0, MIPS_EBASE_CPUNUM
150 /* Hang if this isn't the first CPU in the system */
157 /* Init CP0 Status */
158 4: mfc0 t0, CP0_STATUS
160 or t0, ST0_BEV | ST0_ERL | STATUS_SET
164 * Check whether CP0 Config1 is implemented. If not continue
165 * with legacy Watch register initialization.
172 * Check WR bit in CP0 Config1 to determine if Watch registers
175 mfc0 t0, CP0_CONFIG, 1
180 /* Clear Watch Status bits and disable watch exceptions */
181 li t1, 0x7 # Clear I, R and W conditions
194 MTC0 zero, CP0_WATCHLO
195 mtc0 zero, CP0_WATCHHI
198 /* Clear WP, IV and SW interrupts */
201 /* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */
202 mtc0 zero, CP0_COMPARE
204 #ifdef CONFIG_MIPS_CACHE_DISABLE
206 PTR_LA t9, mips_cache_disable
211 #ifdef CONFIG_MIPS_CM
212 PTR_LA t9, mips_cm_map
217 #ifdef CONFIG_MIPS_INIT_STACK_IN_SRAM
218 #ifdef CONFIG_MIPS_SRAM_INIT
219 /* Initialize the SRAM first */
220 PTR_LA t9, mips_sram_init
225 /* Set up initial stack and global data */
228 # ifdef CONFIG_DEBUG_UART
229 /* Earliest point to set up debug uart */
230 PTR_LA t9, debug_uart_init
236 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
237 # ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
238 /* Initialize any external memory */
239 PTR_LA t9, lowlevel_init
245 #ifdef CONFIG_MIPS_MACH_EARLY_INIT
246 bal mips_mach_early_init
250 #ifdef CONFIG_MIPS_CACHE_SETUP
251 /* Initialize caches... */
252 PTR_LA t9, mips_cache_reset
257 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
258 # ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
259 /* Initialize any external memory */
260 PTR_LA t9, lowlevel_init
266 #ifndef CONFIG_MIPS_INIT_STACK_IN_SRAM
267 /* Set up initial stack and global data */
270 # ifdef CONFIG_DEBUG_UART
271 /* Earliest point to set up debug uart */
272 PTR_LA t9, debug_uart_init
278 move a0, zero # a0 <-- boot_flags = 0
279 PTR_LA t9, board_init_f