1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Startup Code for MIPS32 CPU-core
5 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
8 #include <asm-offsets.h>
11 #include <asm/regdef.h>
12 #include <asm/mipsregs.h>
14 #ifndef CONFIG_SYS_INIT_SP_ADDR
15 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
16 CONFIG_SYS_INIT_SP_OFFSET)
25 # ifdef CONFIG_SYS_LITTLE_ENDIAN
26 # define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
27 (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
29 # define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
30 ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
32 # define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
33 # define STATUS_SET ST0_KX
39 MTC0 zero, CP0_WATCHLO,\sel
40 mtc0 t1, CP0_WATCHHI,\sel
41 mfc0 t0, CP0_WATCHHI,\sel
46 .macro uhi_mips_exception
47 move k0, t9 # preserve t9 in k0
48 move k1, a0 # preserve a0 in k1
49 li t9, 15 # UHI exception operation
50 li a0, 0 # Use hard register context
51 sdbbp 1 # Invoke UHI operation
56 PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
57 and sp, t1, t0 # force 16 byte alignment
59 sp, sp, GD_SIZE # reserve space for gd
60 and sp, sp, t0 # force 16 byte alignment
61 move k0, sp # save gd pointer
62 #if CONFIG_VAL(SYS_MALLOC_F_LEN)
63 li t2, CONFIG_VAL(SYS_MALLOC_F_LEN)
65 sp, sp, t2 # reserve space for early malloc
66 and sp, sp, t0 # force 16 byte alignment
78 #if CONFIG_VAL(SYS_MALLOC_F_LEN)
79 PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
84 /* U-Boot entry point */
86 mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing
88 #if defined(CONFIG_MIPS_INSERT_BOOT_CONFIG)
90 * Store some board-specific boot configuration. This is used by some
91 * MIPS systems like Malta.
94 .word CONFIG_MIPS_BOOT_CONFIG_WORD0
95 .word CONFIG_MIPS_BOOT_CONFIG_WORD1
98 #if defined(CONFIG_ROM_EXCEPTION_VECTORS)
100 * Exception vector entry points. When running from ROM, an exception
101 * cannot be handled. Halt execution and transfer control to debugger,
102 * if one is attached.
105 /* TLB refill, 32 bit task */
109 /* XTLB refill, 64 bit task */
113 /* Cache error exception */
117 /* General exception */
121 /* Catch interrupt exceptions */
125 /* EJTAG debug exception */
133 #if __mips_isa_rev >= 6
134 mfc0 t0, CP0_CONFIG, 5
135 and t0, t0, MIPS_CONF5_VP
140 mfc0 t0, CP0_GLOBALNUMBER
143 #ifdef CONFIG_ARCH_BMIPS
144 1: mfc0 t0, CP0_DIAGNOSTIC, 3
145 and t0, t0, (1 << 31)
147 1: mfc0 t0, CP0_EBASE
148 and t0, t0, EBASE_CPUNUM
151 /* Hang if this isn't the first CPU in the system */
158 /* Init CP0 Status */
159 4: mfc0 t0, CP0_STATUS
161 or t0, ST0_BEV | ST0_ERL | STATUS_SET
165 * Check whether CP0 Config1 is implemented. If not continue
166 * with legacy Watch register initialization.
173 * Check WR bit in CP0 Config1 to determine if Watch registers
176 mfc0 t0, CP0_CONFIG, 1
181 /* Clear Watch Status bits and disable watch exceptions */
182 li t1, 0x7 # Clear I, R and W conditions
195 MTC0 zero, CP0_WATCHLO
196 mtc0 zero, CP0_WATCHHI
199 /* Clear WP, IV and SW interrupts */
202 /* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */
203 mtc0 zero, CP0_COMPARE
205 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
207 and t0, t0, MIPS_CONF_IMPL
208 or t0, t0, CONF_CM_UNCACHED
213 #ifdef CONFIG_MIPS_CM
214 PTR_LA t9, mips_cm_map
219 #ifdef CONFIG_MIPS_INIT_STACK_IN_SRAM
220 #ifdef CONFIG_MIPS_SRAM_INIT
221 /* Initialize the SRAM first */
222 PTR_LA t9, mips_sram_init
227 /* Set up initial stack and global data */
230 # ifdef CONFIG_DEBUG_UART
231 /* Earliest point to set up debug uart */
232 PTR_LA t9, debug_uart_init
238 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
239 # ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
240 /* Initialize any external memory */
241 PTR_LA t9, lowlevel_init
246 /* Initialize caches... */
247 PTR_LA t9, mips_cache_reset
251 # ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
252 /* Initialize any external memory */
253 PTR_LA t9, lowlevel_init
259 #ifndef CONFIG_MIPS_INIT_STACK_IN_SRAM
260 /* Set up initial stack and global data */
263 # ifdef CONFIG_DEBUG_UART
264 /* Earliest point to set up debug uart */
265 PTR_LA t9, debug_uart_init
271 move a0, zero # a0 <-- boot_flags = 0
272 PTR_LA t9, board_init_f