2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2004-2016 Cavium, Inc.
9 #include <linux/of_address.h>
10 #include <linux/interrupt.h>
11 #include <linux/irqdomain.h>
12 #include <linux/bitops.h>
13 #include <linux/of_irq.h>
14 #include <linux/percpu.h>
15 #include <linux/slab.h>
16 #include <linux/irq.h>
17 #include <linux/smp.h>
20 #include <asm/octeon/octeon.h>
21 #include <asm/octeon/cvmx-ciu2-defs.h>
22 #include <asm/octeon/cvmx-ciu3-defs.h>
24 static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu0_en_mirror);
25 static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu1_en_mirror);
26 static DEFINE_PER_CPU(raw_spinlock_t, octeon_irq_ciu_spinlock);
27 static DEFINE_PER_CPU(unsigned int, octeon_irq_ciu3_idt_ip2);
29 static DEFINE_PER_CPU(unsigned int, octeon_irq_ciu3_idt_ip3);
30 static DEFINE_PER_CPU(struct octeon_ciu3_info *, octeon_ciu3_info);
31 #define CIU3_MBOX_PER_CORE 10
34 * The 8 most significant bits of the intsn identify the interrupt major block.
35 * Each major block might use its own interrupt domain. Thus 256 domains are
38 #define MAX_CIU3_DOMAINS 256
40 typedef irq_hw_number_t (*octeon_ciu3_intsn2hw_t)(struct irq_domain *, unsigned int);
42 /* Information for each ciu3 in the system */
43 struct octeon_ciu3_info {
46 struct irq_domain *domain[MAX_CIU3_DOMAINS];
47 octeon_ciu3_intsn2hw_t intsn2hw[MAX_CIU3_DOMAINS];
50 /* Each ciu3 in the system uses its own data (one ciu3 per node) */
51 static struct octeon_ciu3_info *octeon_ciu3_info_per_node[4];
53 struct octeon_irq_ciu_domain_data {
54 int num_sum; /* number of sum registers (2 or 3). */
57 /* Register offsets from ciu3_addr */
58 #define CIU3_CONST 0x220
59 #define CIU3_IDT_CTL(_idt) ((_idt) * 8 + 0x110000)
60 #define CIU3_IDT_PP(_idt, _idx) ((_idt) * 32 + (_idx) * 8 + 0x120000)
61 #define CIU3_IDT_IO(_idt) ((_idt) * 8 + 0x130000)
62 #define CIU3_DEST_PP_INT(_pp_ip) ((_pp_ip) * 8 + 0x200000)
63 #define CIU3_DEST_IO_INT(_io) ((_io) * 8 + 0x210000)
64 #define CIU3_ISC_CTL(_intsn) ((_intsn) * 8 + 0x80000000)
65 #define CIU3_ISC_W1C(_intsn) ((_intsn) * 8 + 0x90000000)
66 #define CIU3_ISC_W1S(_intsn) ((_intsn) * 8 + 0xa0000000)
68 static __read_mostly int octeon_irq_ciu_to_irq[8][64];
70 struct octeon_ciu_chip_data {
72 struct { /* only used for ciu3 */
76 struct { /* only used for ciu/ciu2 */
82 int current_cpu; /* Next CPU expected to take this irq */
83 int ciu_node; /* NUMA node number of the CIU */
86 struct octeon_core_chip_data {
87 struct mutex core_irq_mutex;
93 #define MIPS_CORE_IRQ_LINES 8
95 static struct octeon_core_chip_data octeon_irq_core_chip_data[MIPS_CORE_IRQ_LINES];
97 static int octeon_irq_set_ciu_mapping(int irq, int line, int bit, int gpio_line,
98 struct irq_chip *chip,
99 irq_flow_handler_t handler)
101 struct octeon_ciu_chip_data *cd;
103 cd = kzalloc(sizeof(*cd), GFP_KERNEL);
107 irq_set_chip_and_handler(irq, chip, handler);
111 cd->gpio_line = gpio_line;
113 irq_set_chip_data(irq, cd);
114 octeon_irq_ciu_to_irq[line][bit] = irq;
118 static void octeon_irq_free_cd(struct irq_domain *d, unsigned int irq)
120 struct irq_data *data = irq_get_irq_data(irq);
121 struct octeon_ciu_chip_data *cd = irq_data_get_irq_chip_data(data);
123 irq_set_chip_data(irq, NULL);
127 static int octeon_irq_force_ciu_mapping(struct irq_domain *domain,
128 int irq, int line, int bit)
130 return irq_domain_associate(domain, irq, line << 6 | bit);
133 static int octeon_coreid_for_cpu(int cpu)
136 return cpu_logical_map(cpu);
138 return cvmx_get_core_num();
142 static int octeon_cpu_for_coreid(int coreid)
145 return cpu_number_map(coreid);
147 return smp_processor_id();
151 static void octeon_irq_core_ack(struct irq_data *data)
153 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
154 unsigned int bit = cd->bit;
157 * We don't need to disable IRQs to make these atomic since
158 * they are already disabled earlier in the low level
161 clear_c0_status(0x100 << bit);
162 /* The two user interrupts must be cleared manually. */
164 clear_c0_cause(0x100 << bit);
167 static void octeon_irq_core_eoi(struct irq_data *data)
169 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
172 * We don't need to disable IRQs to make these atomic since
173 * they are already disabled earlier in the low level
176 set_c0_status(0x100 << cd->bit);
179 static void octeon_irq_core_set_enable_local(void *arg)
181 struct irq_data *data = arg;
182 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
183 unsigned int mask = 0x100 << cd->bit;
186 * Interrupts are already disabled, so these are atomic.
191 clear_c0_status(mask);
195 static void octeon_irq_core_disable(struct irq_data *data)
197 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
198 cd->desired_en = false;
201 static void octeon_irq_core_enable(struct irq_data *data)
203 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
204 cd->desired_en = true;
207 static void octeon_irq_core_bus_lock(struct irq_data *data)
209 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
211 mutex_lock(&cd->core_irq_mutex);
214 static void octeon_irq_core_bus_sync_unlock(struct irq_data *data)
216 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
218 if (cd->desired_en != cd->current_en) {
219 on_each_cpu(octeon_irq_core_set_enable_local, data, 1);
221 cd->current_en = cd->desired_en;
224 mutex_unlock(&cd->core_irq_mutex);
227 static struct irq_chip octeon_irq_chip_core = {
229 .irq_enable = octeon_irq_core_enable,
230 .irq_disable = octeon_irq_core_disable,
231 .irq_ack = octeon_irq_core_ack,
232 .irq_eoi = octeon_irq_core_eoi,
233 .irq_bus_lock = octeon_irq_core_bus_lock,
234 .irq_bus_sync_unlock = octeon_irq_core_bus_sync_unlock,
236 .irq_cpu_online = octeon_irq_core_eoi,
237 .irq_cpu_offline = octeon_irq_core_ack,
238 .flags = IRQCHIP_ONOFFLINE_ENABLED,
241 static void __init octeon_irq_init_core(void)
245 struct octeon_core_chip_data *cd;
247 for (i = 0; i < MIPS_CORE_IRQ_LINES; i++) {
248 cd = &octeon_irq_core_chip_data[i];
249 cd->current_en = false;
250 cd->desired_en = false;
252 mutex_init(&cd->core_irq_mutex);
254 irq = OCTEON_IRQ_SW0 + i;
255 irq_set_chip_data(irq, cd);
256 irq_set_chip_and_handler(irq, &octeon_irq_chip_core,
261 static int next_cpu_for_irq(struct irq_data *data)
266 struct cpumask *mask = irq_data_get_affinity_mask(data);
267 int weight = cpumask_weight(mask);
268 struct octeon_ciu_chip_data *cd = irq_data_get_irq_chip_data(data);
271 cpu = cd->current_cpu;
273 cpu = cpumask_next(cpu, mask);
274 if (cpu >= nr_cpu_ids) {
277 } else if (cpumask_test_cpu(cpu, cpu_online_mask)) {
281 } else if (weight == 1) {
282 cpu = cpumask_first(mask);
284 cpu = smp_processor_id();
286 cd->current_cpu = cpu;
289 return smp_processor_id();
293 static void octeon_irq_ciu_enable(struct irq_data *data)
295 int cpu = next_cpu_for_irq(data);
296 int coreid = octeon_coreid_for_cpu(cpu);
299 struct octeon_ciu_chip_data *cd;
300 raw_spinlock_t *lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
302 cd = irq_data_get_irq_chip_data(data);
304 raw_spin_lock_irqsave(lock, flags);
306 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
307 __set_bit(cd->bit, pen);
309 * Must be visible to octeon_irq_ip{2,3}_ciu() before
313 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
315 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
316 __set_bit(cd->bit, pen);
318 * Must be visible to octeon_irq_ip{2,3}_ciu() before
322 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
324 raw_spin_unlock_irqrestore(lock, flags);
327 static void octeon_irq_ciu_enable_local(struct irq_data *data)
331 struct octeon_ciu_chip_data *cd;
332 raw_spinlock_t *lock = this_cpu_ptr(&octeon_irq_ciu_spinlock);
334 cd = irq_data_get_irq_chip_data(data);
336 raw_spin_lock_irqsave(lock, flags);
338 pen = this_cpu_ptr(&octeon_irq_ciu0_en_mirror);
339 __set_bit(cd->bit, pen);
341 * Must be visible to octeon_irq_ip{2,3}_ciu() before
345 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen);
347 pen = this_cpu_ptr(&octeon_irq_ciu1_en_mirror);
348 __set_bit(cd->bit, pen);
350 * Must be visible to octeon_irq_ip{2,3}_ciu() before
354 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen);
356 raw_spin_unlock_irqrestore(lock, flags);
359 static void octeon_irq_ciu_disable_local(struct irq_data *data)
363 struct octeon_ciu_chip_data *cd;
364 raw_spinlock_t *lock = this_cpu_ptr(&octeon_irq_ciu_spinlock);
366 cd = irq_data_get_irq_chip_data(data);
368 raw_spin_lock_irqsave(lock, flags);
370 pen = this_cpu_ptr(&octeon_irq_ciu0_en_mirror);
371 __clear_bit(cd->bit, pen);
373 * Must be visible to octeon_irq_ip{2,3}_ciu() before
377 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen);
379 pen = this_cpu_ptr(&octeon_irq_ciu1_en_mirror);
380 __clear_bit(cd->bit, pen);
382 * Must be visible to octeon_irq_ip{2,3}_ciu() before
386 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen);
388 raw_spin_unlock_irqrestore(lock, flags);
391 static void octeon_irq_ciu_disable_all(struct irq_data *data)
396 struct octeon_ciu_chip_data *cd;
397 raw_spinlock_t *lock;
399 cd = irq_data_get_irq_chip_data(data);
401 for_each_online_cpu(cpu) {
402 int coreid = octeon_coreid_for_cpu(cpu);
403 lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
405 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
407 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
409 raw_spin_lock_irqsave(lock, flags);
410 __clear_bit(cd->bit, pen);
412 * Must be visible to octeon_irq_ip{2,3}_ciu() before
417 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
419 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
420 raw_spin_unlock_irqrestore(lock, flags);
424 static void octeon_irq_ciu_enable_all(struct irq_data *data)
429 struct octeon_ciu_chip_data *cd;
430 raw_spinlock_t *lock;
432 cd = irq_data_get_irq_chip_data(data);
434 for_each_online_cpu(cpu) {
435 int coreid = octeon_coreid_for_cpu(cpu);
436 lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
438 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
440 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
442 raw_spin_lock_irqsave(lock, flags);
443 __set_bit(cd->bit, pen);
445 * Must be visible to octeon_irq_ip{2,3}_ciu() before
450 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
452 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
453 raw_spin_unlock_irqrestore(lock, flags);
458 * Enable the irq on the next core in the affinity set for chips that
459 * have the EN*_W1{S,C} registers.
461 static void octeon_irq_ciu_enable_v2(struct irq_data *data)
464 int cpu = next_cpu_for_irq(data);
465 struct octeon_ciu_chip_data *cd;
467 cd = irq_data_get_irq_chip_data(data);
468 mask = 1ull << (cd->bit);
471 * Called under the desc lock, so these should never get out
475 int index = octeon_coreid_for_cpu(cpu) * 2;
476 set_bit(cd->bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu));
477 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
479 int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
480 set_bit(cd->bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
481 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
486 * Enable the irq in the sum2 registers.
488 static void octeon_irq_ciu_enable_sum2(struct irq_data *data)
491 int cpu = next_cpu_for_irq(data);
492 int index = octeon_coreid_for_cpu(cpu);
493 struct octeon_ciu_chip_data *cd;
495 cd = irq_data_get_irq_chip_data(data);
496 mask = 1ull << (cd->bit);
498 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1S(index), mask);
502 * Disable the irq in the sum2 registers.
504 static void octeon_irq_ciu_disable_local_sum2(struct irq_data *data)
507 int cpu = next_cpu_for_irq(data);
508 int index = octeon_coreid_for_cpu(cpu);
509 struct octeon_ciu_chip_data *cd;
511 cd = irq_data_get_irq_chip_data(data);
512 mask = 1ull << (cd->bit);
514 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(index), mask);
517 static void octeon_irq_ciu_ack_sum2(struct irq_data *data)
520 int cpu = next_cpu_for_irq(data);
521 int index = octeon_coreid_for_cpu(cpu);
522 struct octeon_ciu_chip_data *cd;
524 cd = irq_data_get_irq_chip_data(data);
525 mask = 1ull << (cd->bit);
527 cvmx_write_csr(CVMX_CIU_SUM2_PPX_IP4(index), mask);
530 static void octeon_irq_ciu_disable_all_sum2(struct irq_data *data)
533 struct octeon_ciu_chip_data *cd;
536 cd = irq_data_get_irq_chip_data(data);
537 mask = 1ull << (cd->bit);
539 for_each_online_cpu(cpu) {
540 int coreid = octeon_coreid_for_cpu(cpu);
542 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(coreid), mask);
547 * Enable the irq on the current CPU for chips that
548 * have the EN*_W1{S,C} registers.
550 static void octeon_irq_ciu_enable_local_v2(struct irq_data *data)
553 struct octeon_ciu_chip_data *cd;
555 cd = irq_data_get_irq_chip_data(data);
556 mask = 1ull << (cd->bit);
559 int index = cvmx_get_core_num() * 2;
560 set_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu0_en_mirror));
561 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
563 int index = cvmx_get_core_num() * 2 + 1;
564 set_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu1_en_mirror));
565 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
569 static void octeon_irq_ciu_disable_local_v2(struct irq_data *data)
572 struct octeon_ciu_chip_data *cd;
574 cd = irq_data_get_irq_chip_data(data);
575 mask = 1ull << (cd->bit);
578 int index = cvmx_get_core_num() * 2;
579 clear_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu0_en_mirror));
580 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
582 int index = cvmx_get_core_num() * 2 + 1;
583 clear_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu1_en_mirror));
584 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
589 * Write to the W1C bit in CVMX_CIU_INTX_SUM0 to clear the irq.
591 static void octeon_irq_ciu_ack(struct irq_data *data)
594 struct octeon_ciu_chip_data *cd;
596 cd = irq_data_get_irq_chip_data(data);
597 mask = 1ull << (cd->bit);
600 int index = cvmx_get_core_num() * 2;
601 cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
603 cvmx_write_csr(CVMX_CIU_INT_SUM1, mask);
608 * Disable the irq on the all cores for chips that have the EN*_W1{S,C}
611 static void octeon_irq_ciu_disable_all_v2(struct irq_data *data)
615 struct octeon_ciu_chip_data *cd;
617 cd = irq_data_get_irq_chip_data(data);
618 mask = 1ull << (cd->bit);
621 for_each_online_cpu(cpu) {
622 int index = octeon_coreid_for_cpu(cpu) * 2;
624 &per_cpu(octeon_irq_ciu0_en_mirror, cpu));
625 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
628 for_each_online_cpu(cpu) {
629 int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
631 &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
632 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
638 * Enable the irq on the all cores for chips that have the EN*_W1{S,C}
641 static void octeon_irq_ciu_enable_all_v2(struct irq_data *data)
645 struct octeon_ciu_chip_data *cd;
647 cd = irq_data_get_irq_chip_data(data);
648 mask = 1ull << (cd->bit);
651 for_each_online_cpu(cpu) {
652 int index = octeon_coreid_for_cpu(cpu) * 2;
654 &per_cpu(octeon_irq_ciu0_en_mirror, cpu));
655 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
658 for_each_online_cpu(cpu) {
659 int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
661 &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
662 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
667 static int octeon_irq_ciu_set_type(struct irq_data *data, unsigned int t)
669 irqd_set_trigger_type(data, t);
671 if (t & IRQ_TYPE_EDGE_BOTH)
672 irq_set_handler_locked(data, handle_edge_irq);
674 irq_set_handler_locked(data, handle_level_irq);
676 return IRQ_SET_MASK_OK;
679 static void octeon_irq_gpio_setup(struct irq_data *data)
681 union cvmx_gpio_bit_cfgx cfg;
682 struct octeon_ciu_chip_data *cd;
683 u32 t = irqd_get_trigger_type(data);
685 cd = irq_data_get_irq_chip_data(data);
689 cfg.s.int_type = (t & IRQ_TYPE_EDGE_BOTH) != 0;
690 cfg.s.rx_xor = (t & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) != 0;
692 /* 140 nS glitch filter*/
696 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), cfg.u64);
699 static void octeon_irq_ciu_enable_gpio_v2(struct irq_data *data)
701 octeon_irq_gpio_setup(data);
702 octeon_irq_ciu_enable_v2(data);
705 static void octeon_irq_ciu_enable_gpio(struct irq_data *data)
707 octeon_irq_gpio_setup(data);
708 octeon_irq_ciu_enable(data);
711 static int octeon_irq_ciu_gpio_set_type(struct irq_data *data, unsigned int t)
713 irqd_set_trigger_type(data, t);
714 octeon_irq_gpio_setup(data);
716 if (t & IRQ_TYPE_EDGE_BOTH)
717 irq_set_handler_locked(data, handle_edge_irq);
719 irq_set_handler_locked(data, handle_level_irq);
721 return IRQ_SET_MASK_OK;
724 static void octeon_irq_ciu_disable_gpio_v2(struct irq_data *data)
726 struct octeon_ciu_chip_data *cd;
728 cd = irq_data_get_irq_chip_data(data);
729 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0);
731 octeon_irq_ciu_disable_all_v2(data);
734 static void octeon_irq_ciu_disable_gpio(struct irq_data *data)
736 struct octeon_ciu_chip_data *cd;
738 cd = irq_data_get_irq_chip_data(data);
739 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0);
741 octeon_irq_ciu_disable_all(data);
744 static void octeon_irq_ciu_gpio_ack(struct irq_data *data)
746 struct octeon_ciu_chip_data *cd;
749 cd = irq_data_get_irq_chip_data(data);
750 mask = 1ull << (cd->gpio_line);
752 cvmx_write_csr(CVMX_GPIO_INT_CLR, mask);
757 static void octeon_irq_cpu_offline_ciu(struct irq_data *data)
759 int cpu = smp_processor_id();
760 cpumask_t new_affinity;
761 struct cpumask *mask = irq_data_get_affinity_mask(data);
763 if (!cpumask_test_cpu(cpu, mask))
766 if (cpumask_weight(mask) > 1) {
768 * It has multi CPU affinity, just remove this CPU
769 * from the affinity set.
771 cpumask_copy(&new_affinity, mask);
772 cpumask_clear_cpu(cpu, &new_affinity);
774 /* Otherwise, put it on lowest numbered online CPU. */
775 cpumask_clear(&new_affinity);
776 cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
778 irq_set_affinity_locked(data, &new_affinity, false);
781 static int octeon_irq_ciu_set_affinity(struct irq_data *data,
782 const struct cpumask *dest, bool force)
785 bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
787 struct octeon_ciu_chip_data *cd;
789 raw_spinlock_t *lock;
791 cd = irq_data_get_irq_chip_data(data);
794 * For non-v2 CIU, we will allow only single CPU affinity.
795 * This removes the need to do locking in the .ack/.eoi
798 if (cpumask_weight(dest) != 1)
805 for_each_online_cpu(cpu) {
806 int coreid = octeon_coreid_for_cpu(cpu);
808 lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
809 raw_spin_lock_irqsave(lock, flags);
812 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
814 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
816 if (cpumask_test_cpu(cpu, dest) && enable_one) {
818 __set_bit(cd->bit, pen);
820 __clear_bit(cd->bit, pen);
823 * Must be visible to octeon_irq_ip{2,3}_ciu() before
829 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
831 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
833 raw_spin_unlock_irqrestore(lock, flags);
839 * Set affinity for the irq for chips that have the EN*_W1{S,C}
842 static int octeon_irq_ciu_set_affinity_v2(struct irq_data *data,
843 const struct cpumask *dest,
847 bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
849 struct octeon_ciu_chip_data *cd;
854 cd = irq_data_get_irq_chip_data(data);
855 mask = 1ull << cd->bit;
858 for_each_online_cpu(cpu) {
859 unsigned long *pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
860 int index = octeon_coreid_for_cpu(cpu) * 2;
861 if (cpumask_test_cpu(cpu, dest) && enable_one) {
863 set_bit(cd->bit, pen);
864 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
866 clear_bit(cd->bit, pen);
867 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
871 for_each_online_cpu(cpu) {
872 unsigned long *pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
873 int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
874 if (cpumask_test_cpu(cpu, dest) && enable_one) {
876 set_bit(cd->bit, pen);
877 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
879 clear_bit(cd->bit, pen);
880 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
887 static int octeon_irq_ciu_set_affinity_sum2(struct irq_data *data,
888 const struct cpumask *dest,
892 bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
894 struct octeon_ciu_chip_data *cd;
899 cd = irq_data_get_irq_chip_data(data);
900 mask = 1ull << cd->bit;
902 for_each_online_cpu(cpu) {
903 int index = octeon_coreid_for_cpu(cpu);
905 if (cpumask_test_cpu(cpu, dest) && enable_one) {
907 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1S(index), mask);
909 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(index), mask);
916 static unsigned int edge_startup(struct irq_data *data)
918 /* ack any pending edge-irq at startup, so there is
919 * an _edge_ to fire on when the event reappears.
921 data->chip->irq_ack(data);
922 data->chip->irq_enable(data);
927 * Newer octeon chips have support for lockless CIU operation.
929 static struct irq_chip octeon_irq_chip_ciu_v2 = {
931 .irq_enable = octeon_irq_ciu_enable_v2,
932 .irq_disable = octeon_irq_ciu_disable_all_v2,
933 .irq_mask = octeon_irq_ciu_disable_local_v2,
934 .irq_unmask = octeon_irq_ciu_enable_v2,
936 .irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
937 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
941 static struct irq_chip octeon_irq_chip_ciu_v2_edge = {
943 .irq_enable = octeon_irq_ciu_enable_v2,
944 .irq_disable = octeon_irq_ciu_disable_all_v2,
945 .irq_ack = octeon_irq_ciu_ack,
946 .irq_mask = octeon_irq_ciu_disable_local_v2,
947 .irq_unmask = octeon_irq_ciu_enable_v2,
949 .irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
950 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
955 * Newer octeon chips have support for lockless CIU operation.
957 static struct irq_chip octeon_irq_chip_ciu_sum2 = {
959 .irq_enable = octeon_irq_ciu_enable_sum2,
960 .irq_disable = octeon_irq_ciu_disable_all_sum2,
961 .irq_mask = octeon_irq_ciu_disable_local_sum2,
962 .irq_unmask = octeon_irq_ciu_enable_sum2,
964 .irq_set_affinity = octeon_irq_ciu_set_affinity_sum2,
965 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
969 static struct irq_chip octeon_irq_chip_ciu_sum2_edge = {
971 .irq_enable = octeon_irq_ciu_enable_sum2,
972 .irq_disable = octeon_irq_ciu_disable_all_sum2,
973 .irq_ack = octeon_irq_ciu_ack_sum2,
974 .irq_mask = octeon_irq_ciu_disable_local_sum2,
975 .irq_unmask = octeon_irq_ciu_enable_sum2,
977 .irq_set_affinity = octeon_irq_ciu_set_affinity_sum2,
978 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
982 static struct irq_chip octeon_irq_chip_ciu = {
984 .irq_enable = octeon_irq_ciu_enable,
985 .irq_disable = octeon_irq_ciu_disable_all,
986 .irq_mask = octeon_irq_ciu_disable_local,
987 .irq_unmask = octeon_irq_ciu_enable,
989 .irq_set_affinity = octeon_irq_ciu_set_affinity,
990 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
994 static struct irq_chip octeon_irq_chip_ciu_edge = {
996 .irq_enable = octeon_irq_ciu_enable,
997 .irq_disable = octeon_irq_ciu_disable_all,
998 .irq_ack = octeon_irq_ciu_ack,
999 .irq_mask = octeon_irq_ciu_disable_local,
1000 .irq_unmask = octeon_irq_ciu_enable,
1002 .irq_set_affinity = octeon_irq_ciu_set_affinity,
1003 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
1007 /* The mbox versions don't do any affinity or round-robin. */
1008 static struct irq_chip octeon_irq_chip_ciu_mbox_v2 = {
1010 .irq_enable = octeon_irq_ciu_enable_all_v2,
1011 .irq_disable = octeon_irq_ciu_disable_all_v2,
1012 .irq_ack = octeon_irq_ciu_disable_local_v2,
1013 .irq_eoi = octeon_irq_ciu_enable_local_v2,
1015 .irq_cpu_online = octeon_irq_ciu_enable_local_v2,
1016 .irq_cpu_offline = octeon_irq_ciu_disable_local_v2,
1017 .flags = IRQCHIP_ONOFFLINE_ENABLED,
1020 static struct irq_chip octeon_irq_chip_ciu_mbox = {
1022 .irq_enable = octeon_irq_ciu_enable_all,
1023 .irq_disable = octeon_irq_ciu_disable_all,
1024 .irq_ack = octeon_irq_ciu_disable_local,
1025 .irq_eoi = octeon_irq_ciu_enable_local,
1027 .irq_cpu_online = octeon_irq_ciu_enable_local,
1028 .irq_cpu_offline = octeon_irq_ciu_disable_local,
1029 .flags = IRQCHIP_ONOFFLINE_ENABLED,
1032 static struct irq_chip octeon_irq_chip_ciu_gpio_v2 = {
1034 .irq_enable = octeon_irq_ciu_enable_gpio_v2,
1035 .irq_disable = octeon_irq_ciu_disable_gpio_v2,
1036 .irq_ack = octeon_irq_ciu_gpio_ack,
1037 .irq_mask = octeon_irq_ciu_disable_local_v2,
1038 .irq_unmask = octeon_irq_ciu_enable_v2,
1039 .irq_set_type = octeon_irq_ciu_gpio_set_type,
1041 .irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
1042 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
1044 .flags = IRQCHIP_SET_TYPE_MASKED,
1047 static struct irq_chip octeon_irq_chip_ciu_gpio = {
1049 .irq_enable = octeon_irq_ciu_enable_gpio,
1050 .irq_disable = octeon_irq_ciu_disable_gpio,
1051 .irq_mask = octeon_irq_ciu_disable_local,
1052 .irq_unmask = octeon_irq_ciu_enable,
1053 .irq_ack = octeon_irq_ciu_gpio_ack,
1054 .irq_set_type = octeon_irq_ciu_gpio_set_type,
1056 .irq_set_affinity = octeon_irq_ciu_set_affinity,
1057 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
1059 .flags = IRQCHIP_SET_TYPE_MASKED,
1063 * Watchdog interrupts are special. They are associated with a single
1064 * core, so we hardwire the affinity to that core.
1066 static void octeon_irq_ciu_wd_enable(struct irq_data *data)
1068 unsigned long flags;
1070 int coreid = data->irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
1071 int cpu = octeon_cpu_for_coreid(coreid);
1072 raw_spinlock_t *lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
1074 raw_spin_lock_irqsave(lock, flags);
1075 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
1076 __set_bit(coreid, pen);
1078 * Must be visible to octeon_irq_ip{2,3}_ciu() before enabling
1082 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
1083 raw_spin_unlock_irqrestore(lock, flags);
1087 * Watchdog interrupts are special. They are associated with a single
1088 * core, so we hardwire the affinity to that core.
1090 static void octeon_irq_ciu1_wd_enable_v2(struct irq_data *data)
1092 int coreid = data->irq - OCTEON_IRQ_WDOG0;
1093 int cpu = octeon_cpu_for_coreid(coreid);
1095 set_bit(coreid, &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
1096 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(coreid * 2 + 1), 1ull << coreid);
1100 static struct irq_chip octeon_irq_chip_ciu_wd_v2 = {
1102 .irq_enable = octeon_irq_ciu1_wd_enable_v2,
1103 .irq_disable = octeon_irq_ciu_disable_all_v2,
1104 .irq_mask = octeon_irq_ciu_disable_local_v2,
1105 .irq_unmask = octeon_irq_ciu_enable_local_v2,
1108 static struct irq_chip octeon_irq_chip_ciu_wd = {
1110 .irq_enable = octeon_irq_ciu_wd_enable,
1111 .irq_disable = octeon_irq_ciu_disable_all,
1112 .irq_mask = octeon_irq_ciu_disable_local,
1113 .irq_unmask = octeon_irq_ciu_enable_local,
1116 static bool octeon_irq_ciu_is_edge(unsigned int line, unsigned int bit)
1122 case 48 ... 49: /* GMX DRP */
1123 case 50: /* IPD_DRP */
1124 case 52 ... 55: /* Timers */
1131 else /* line == 1 */
1142 struct octeon_irq_gpio_domain_data {
1143 unsigned int base_hwirq;
1146 static int octeon_irq_gpio_xlat(struct irq_domain *d,
1147 struct device_node *node,
1149 unsigned int intsize,
1150 unsigned long *out_hwirq,
1151 unsigned int *out_type)
1155 unsigned int trigger;
1157 if (irq_domain_get_of_node(d) != node)
1167 trigger = intspec[1];
1171 type = IRQ_TYPE_EDGE_RISING;
1174 type = IRQ_TYPE_EDGE_FALLING;
1177 type = IRQ_TYPE_LEVEL_HIGH;
1180 type = IRQ_TYPE_LEVEL_LOW;
1183 pr_err("Error: (%pOFn) Invalid irq trigger specification: %x\n",
1186 type = IRQ_TYPE_LEVEL_LOW;
1195 static int octeon_irq_ciu_xlat(struct irq_domain *d,
1196 struct device_node *node,
1198 unsigned int intsize,
1199 unsigned long *out_hwirq,
1200 unsigned int *out_type)
1202 unsigned int ciu, bit;
1203 struct octeon_irq_ciu_domain_data *dd = d->host_data;
1208 if (ciu >= dd->num_sum || bit > 63)
1211 *out_hwirq = (ciu << 6) | bit;
1217 static struct irq_chip *octeon_irq_ciu_chip;
1218 static struct irq_chip *octeon_irq_ciu_chip_edge;
1219 static struct irq_chip *octeon_irq_gpio_chip;
1221 static int octeon_irq_ciu_map(struct irq_domain *d,
1222 unsigned int virq, irq_hw_number_t hw)
1225 unsigned int line = hw >> 6;
1226 unsigned int bit = hw & 63;
1227 struct octeon_irq_ciu_domain_data *dd = d->host_data;
1229 if (line >= dd->num_sum || octeon_irq_ciu_to_irq[line][bit] != 0)
1233 if (octeon_irq_ciu_is_edge(line, bit))
1234 rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1235 &octeon_irq_chip_ciu_sum2_edge,
1238 rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1239 &octeon_irq_chip_ciu_sum2,
1242 if (octeon_irq_ciu_is_edge(line, bit))
1243 rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1244 octeon_irq_ciu_chip_edge,
1247 rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1248 octeon_irq_ciu_chip,
1254 static int octeon_irq_gpio_map(struct irq_domain *d,
1255 unsigned int virq, irq_hw_number_t hw)
1257 struct octeon_irq_gpio_domain_data *gpiod = d->host_data;
1258 unsigned int line, bit;
1261 line = (hw + gpiod->base_hwirq) >> 6;
1262 bit = (hw + gpiod->base_hwirq) & 63;
1263 if (line >= ARRAY_SIZE(octeon_irq_ciu_to_irq) ||
1264 octeon_irq_ciu_to_irq[line][bit] != 0)
1268 * Default to handle_level_irq. If the DT contains a different
1269 * trigger type, it will call the irq_set_type callback and
1270 * the handler gets updated.
1272 r = octeon_irq_set_ciu_mapping(virq, line, bit, hw,
1273 octeon_irq_gpio_chip, handle_level_irq);
1277 static struct irq_domain_ops octeon_irq_domain_ciu_ops = {
1278 .map = octeon_irq_ciu_map,
1279 .unmap = octeon_irq_free_cd,
1280 .xlate = octeon_irq_ciu_xlat,
1283 static struct irq_domain_ops octeon_irq_domain_gpio_ops = {
1284 .map = octeon_irq_gpio_map,
1285 .unmap = octeon_irq_free_cd,
1286 .xlate = octeon_irq_gpio_xlat,
1289 static void octeon_irq_ip2_ciu(void)
1291 const unsigned long core_id = cvmx_get_core_num();
1292 u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2));
1294 ciu_sum &= __this_cpu_read(octeon_irq_ciu0_en_mirror);
1295 if (likely(ciu_sum)) {
1296 int bit = fls64(ciu_sum) - 1;
1297 int irq = octeon_irq_ciu_to_irq[0][bit];
1301 spurious_interrupt();
1303 spurious_interrupt();
1307 static void octeon_irq_ip3_ciu(void)
1309 u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1);
1311 ciu_sum &= __this_cpu_read(octeon_irq_ciu1_en_mirror);
1312 if (likely(ciu_sum)) {
1313 int bit = fls64(ciu_sum) - 1;
1314 int irq = octeon_irq_ciu_to_irq[1][bit];
1318 spurious_interrupt();
1320 spurious_interrupt();
1324 static void octeon_irq_ip4_ciu(void)
1326 int coreid = cvmx_get_core_num();
1327 u64 ciu_sum = cvmx_read_csr(CVMX_CIU_SUM2_PPX_IP4(coreid));
1328 u64 ciu_en = cvmx_read_csr(CVMX_CIU_EN2_PPX_IP4(coreid));
1331 if (likely(ciu_sum)) {
1332 int bit = fls64(ciu_sum) - 1;
1333 int irq = octeon_irq_ciu_to_irq[2][bit];
1338 spurious_interrupt();
1340 spurious_interrupt();
1344 static bool octeon_irq_use_ip4;
1346 static void octeon_irq_local_enable_ip4(void *arg)
1348 set_c0_status(STATUSF_IP4);
1351 static void octeon_irq_ip4_mask(void)
1353 clear_c0_status(STATUSF_IP4);
1354 spurious_interrupt();
1357 static void (*octeon_irq_ip2)(void);
1358 static void (*octeon_irq_ip3)(void);
1359 static void (*octeon_irq_ip4)(void);
1361 void (*octeon_irq_setup_secondary)(void);
1363 void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t h)
1366 octeon_irq_use_ip4 = true;
1367 on_each_cpu(octeon_irq_local_enable_ip4, NULL, 1);
1370 static void octeon_irq_percpu_enable(void)
1375 static void octeon_irq_init_ciu_percpu(void)
1377 int coreid = cvmx_get_core_num();
1380 __this_cpu_write(octeon_irq_ciu0_en_mirror, 0);
1381 __this_cpu_write(octeon_irq_ciu1_en_mirror, 0);
1383 raw_spin_lock_init(this_cpu_ptr(&octeon_irq_ciu_spinlock));
1385 * Disable All CIU Interrupts. The ones we need will be
1386 * enabled later. Read the SUM register so we know the write
1389 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0);
1390 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
1391 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
1392 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
1393 cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2)));
1396 static void octeon_irq_init_ciu2_percpu(void)
1399 int coreid = cvmx_get_core_num();
1400 u64 base = CVMX_CIU2_EN_PPX_IP2_WRKQ(coreid);
1403 * Disable All CIU2 Interrupts. The ones we need will be
1404 * enabled later. Read the SUM register so we know the write
1407 * There are 9 registers and 3 IPX levels with strides 0x1000
1408 * and 0x200 respectivly. Use loops to clear them.
1410 for (regx = 0; regx <= 0x8000; regx += 0x1000) {
1411 for (ipx = 0; ipx <= 0x400; ipx += 0x200)
1412 cvmx_write_csr(base + regx + ipx, 0);
1415 cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid));
1418 static void octeon_irq_setup_secondary_ciu(void)
1420 octeon_irq_init_ciu_percpu();
1421 octeon_irq_percpu_enable();
1423 /* Enable the CIU lines */
1424 set_c0_status(STATUSF_IP3 | STATUSF_IP2);
1425 if (octeon_irq_use_ip4)
1426 set_c0_status(STATUSF_IP4);
1428 clear_c0_status(STATUSF_IP4);
1431 static void octeon_irq_setup_secondary_ciu2(void)
1433 octeon_irq_init_ciu2_percpu();
1434 octeon_irq_percpu_enable();
1436 /* Enable the CIU lines */
1437 set_c0_status(STATUSF_IP3 | STATUSF_IP2);
1438 if (octeon_irq_use_ip4)
1439 set_c0_status(STATUSF_IP4);
1441 clear_c0_status(STATUSF_IP4);
1444 static int __init octeon_irq_init_ciu(
1445 struct device_node *ciu_node, struct device_node *parent)
1448 struct irq_chip *chip;
1449 struct irq_chip *chip_edge;
1450 struct irq_chip *chip_mbox;
1451 struct irq_chip *chip_wd;
1452 struct irq_domain *ciu_domain = NULL;
1453 struct octeon_irq_ciu_domain_data *dd;
1455 dd = kzalloc(sizeof(*dd), GFP_KERNEL);
1459 octeon_irq_init_ciu_percpu();
1460 octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu;
1462 octeon_irq_ip2 = octeon_irq_ip2_ciu;
1463 octeon_irq_ip3 = octeon_irq_ip3_ciu;
1464 if ((OCTEON_IS_OCTEON2() || OCTEON_IS_OCTEON3())
1465 && !OCTEON_IS_MODEL(OCTEON_CN63XX)) {
1466 octeon_irq_ip4 = octeon_irq_ip4_ciu;
1468 octeon_irq_use_ip4 = true;
1470 octeon_irq_ip4 = octeon_irq_ip4_mask;
1472 octeon_irq_use_ip4 = false;
1474 if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) ||
1475 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
1476 OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) ||
1477 OCTEON_IS_OCTEON2() || OCTEON_IS_OCTEON3()) {
1478 chip = &octeon_irq_chip_ciu_v2;
1479 chip_edge = &octeon_irq_chip_ciu_v2_edge;
1480 chip_mbox = &octeon_irq_chip_ciu_mbox_v2;
1481 chip_wd = &octeon_irq_chip_ciu_wd_v2;
1482 octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio_v2;
1484 chip = &octeon_irq_chip_ciu;
1485 chip_edge = &octeon_irq_chip_ciu_edge;
1486 chip_mbox = &octeon_irq_chip_ciu_mbox;
1487 chip_wd = &octeon_irq_chip_ciu_wd;
1488 octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio;
1490 octeon_irq_ciu_chip = chip;
1491 octeon_irq_ciu_chip_edge = chip_edge;
1494 octeon_irq_init_core();
1496 ciu_domain = irq_domain_add_tree(
1497 ciu_node, &octeon_irq_domain_ciu_ops, dd);
1498 irq_set_default_host(ciu_domain);
1501 for (i = 0; i < 16; i++) {
1502 r = octeon_irq_force_ciu_mapping(
1503 ciu_domain, i + OCTEON_IRQ_WORKQ0, 0, i + 0);
1508 r = octeon_irq_set_ciu_mapping(
1509 OCTEON_IRQ_MBOX0, 0, 32, 0, chip_mbox, handle_percpu_irq);
1512 r = octeon_irq_set_ciu_mapping(
1513 OCTEON_IRQ_MBOX1, 0, 33, 0, chip_mbox, handle_percpu_irq);
1517 for (i = 0; i < 4; i++) {
1518 r = octeon_irq_force_ciu_mapping(
1519 ciu_domain, i + OCTEON_IRQ_PCI_INT0, 0, i + 36);
1523 for (i = 0; i < 4; i++) {
1524 r = octeon_irq_force_ciu_mapping(
1525 ciu_domain, i + OCTEON_IRQ_PCI_MSI0, 0, i + 40);
1530 r = octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_TWSI, 0, 45);
1534 r = octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_RML, 0, 46);
1538 for (i = 0; i < 4; i++) {
1539 r = octeon_irq_force_ciu_mapping(
1540 ciu_domain, i + OCTEON_IRQ_TIMER0, 0, i + 52);
1545 r = octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_TWSI2, 0, 59);
1550 for (i = 0; i < 16; i++) {
1551 r = octeon_irq_set_ciu_mapping(
1552 i + OCTEON_IRQ_WDOG0, 1, i + 0, 0, chip_wd,
1558 /* Enable the CIU lines */
1559 set_c0_status(STATUSF_IP3 | STATUSF_IP2);
1560 if (octeon_irq_use_ip4)
1561 set_c0_status(STATUSF_IP4);
1563 clear_c0_status(STATUSF_IP4);
1570 static int __init octeon_irq_init_gpio(
1571 struct device_node *gpio_node, struct device_node *parent)
1573 struct octeon_irq_gpio_domain_data *gpiod;
1574 u32 interrupt_cells;
1575 unsigned int base_hwirq;
1578 r = of_property_read_u32(parent, "#interrupt-cells", &interrupt_cells);
1582 if (interrupt_cells == 1) {
1585 r = of_property_read_u32_index(gpio_node, "interrupts", 0, &v);
1587 pr_warn("No \"interrupts\" property.\n");
1591 } else if (interrupt_cells == 2) {
1594 r = of_property_read_u32_index(gpio_node, "interrupts", 0, &v0);
1596 pr_warn("No \"interrupts\" property.\n");
1599 r = of_property_read_u32_index(gpio_node, "interrupts", 1, &v1);
1601 pr_warn("No \"interrupts\" property.\n");
1604 base_hwirq = (v0 << 6) | v1;
1606 pr_warn("Bad \"#interrupt-cells\" property: %u\n",
1611 gpiod = kzalloc(sizeof(*gpiod), GFP_KERNEL);
1613 /* gpio domain host_data is the base hwirq number. */
1614 gpiod->base_hwirq = base_hwirq;
1615 irq_domain_add_linear(
1616 gpio_node, 16, &octeon_irq_domain_gpio_ops, gpiod);
1618 pr_warn("Cannot allocate memory for GPIO irq_domain.\n");
1623 * Clear the OF_POPULATED flag that was set by of_irq_init()
1624 * so that all GPIO devices will be probed.
1626 of_node_clear_flag(gpio_node, OF_POPULATED);
1631 * Watchdog interrupts are special. They are associated with a single
1632 * core, so we hardwire the affinity to that core.
1634 static void octeon_irq_ciu2_wd_enable(struct irq_data *data)
1638 int coreid = data->irq - OCTEON_IRQ_WDOG0;
1639 struct octeon_ciu_chip_data *cd;
1641 cd = irq_data_get_irq_chip_data(data);
1642 mask = 1ull << (cd->bit);
1644 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(coreid) +
1645 (0x1000ull * cd->line);
1646 cvmx_write_csr(en_addr, mask);
1650 static void octeon_irq_ciu2_enable(struct irq_data *data)
1654 int cpu = next_cpu_for_irq(data);
1655 int coreid = octeon_coreid_for_cpu(cpu);
1656 struct octeon_ciu_chip_data *cd;
1658 cd = irq_data_get_irq_chip_data(data);
1659 mask = 1ull << (cd->bit);
1661 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(coreid) +
1662 (0x1000ull * cd->line);
1663 cvmx_write_csr(en_addr, mask);
1666 static void octeon_irq_ciu2_enable_local(struct irq_data *data)
1670 int coreid = cvmx_get_core_num();
1671 struct octeon_ciu_chip_data *cd;
1673 cd = irq_data_get_irq_chip_data(data);
1674 mask = 1ull << (cd->bit);
1676 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(coreid) +
1677 (0x1000ull * cd->line);
1678 cvmx_write_csr(en_addr, mask);
1682 static void octeon_irq_ciu2_disable_local(struct irq_data *data)
1686 int coreid = cvmx_get_core_num();
1687 struct octeon_ciu_chip_data *cd;
1689 cd = irq_data_get_irq_chip_data(data);
1690 mask = 1ull << (cd->bit);
1692 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(coreid) +
1693 (0x1000ull * cd->line);
1694 cvmx_write_csr(en_addr, mask);
1698 static void octeon_irq_ciu2_ack(struct irq_data *data)
1702 int coreid = cvmx_get_core_num();
1703 struct octeon_ciu_chip_data *cd;
1705 cd = irq_data_get_irq_chip_data(data);
1706 mask = 1ull << (cd->bit);
1708 en_addr = CVMX_CIU2_RAW_PPX_IP2_WRKQ(coreid) + (0x1000ull * cd->line);
1709 cvmx_write_csr(en_addr, mask);
1713 static void octeon_irq_ciu2_disable_all(struct irq_data *data)
1717 struct octeon_ciu_chip_data *cd;
1719 cd = irq_data_get_irq_chip_data(data);
1720 mask = 1ull << (cd->bit);
1722 for_each_online_cpu(cpu) {
1723 u64 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(
1724 octeon_coreid_for_cpu(cpu)) + (0x1000ull * cd->line);
1725 cvmx_write_csr(en_addr, mask);
1729 static void octeon_irq_ciu2_mbox_enable_all(struct irq_data *data)
1734 mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0);
1736 for_each_online_cpu(cpu) {
1737 u64 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(
1738 octeon_coreid_for_cpu(cpu));
1739 cvmx_write_csr(en_addr, mask);
1743 static void octeon_irq_ciu2_mbox_disable_all(struct irq_data *data)
1748 mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0);
1750 for_each_online_cpu(cpu) {
1751 u64 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(
1752 octeon_coreid_for_cpu(cpu));
1753 cvmx_write_csr(en_addr, mask);
1757 static void octeon_irq_ciu2_mbox_enable_local(struct irq_data *data)
1761 int coreid = cvmx_get_core_num();
1763 mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0);
1764 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(coreid);
1765 cvmx_write_csr(en_addr, mask);
1768 static void octeon_irq_ciu2_mbox_disable_local(struct irq_data *data)
1772 int coreid = cvmx_get_core_num();
1774 mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0);
1775 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(coreid);
1776 cvmx_write_csr(en_addr, mask);
1780 static int octeon_irq_ciu2_set_affinity(struct irq_data *data,
1781 const struct cpumask *dest, bool force)
1784 bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
1786 struct octeon_ciu_chip_data *cd;
1791 cd = irq_data_get_irq_chip_data(data);
1792 mask = 1ull << cd->bit;
1794 for_each_online_cpu(cpu) {
1796 if (cpumask_test_cpu(cpu, dest) && enable_one) {
1798 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(
1799 octeon_coreid_for_cpu(cpu)) +
1800 (0x1000ull * cd->line);
1802 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(
1803 octeon_coreid_for_cpu(cpu)) +
1804 (0x1000ull * cd->line);
1806 cvmx_write_csr(en_addr, mask);
1813 static void octeon_irq_ciu2_enable_gpio(struct irq_data *data)
1815 octeon_irq_gpio_setup(data);
1816 octeon_irq_ciu2_enable(data);
1819 static void octeon_irq_ciu2_disable_gpio(struct irq_data *data)
1821 struct octeon_ciu_chip_data *cd;
1823 cd = irq_data_get_irq_chip_data(data);
1825 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0);
1827 octeon_irq_ciu2_disable_all(data);
1830 static struct irq_chip octeon_irq_chip_ciu2 = {
1832 .irq_enable = octeon_irq_ciu2_enable,
1833 .irq_disable = octeon_irq_ciu2_disable_all,
1834 .irq_mask = octeon_irq_ciu2_disable_local,
1835 .irq_unmask = octeon_irq_ciu2_enable,
1837 .irq_set_affinity = octeon_irq_ciu2_set_affinity,
1838 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
1842 static struct irq_chip octeon_irq_chip_ciu2_edge = {
1844 .irq_enable = octeon_irq_ciu2_enable,
1845 .irq_disable = octeon_irq_ciu2_disable_all,
1846 .irq_ack = octeon_irq_ciu2_ack,
1847 .irq_mask = octeon_irq_ciu2_disable_local,
1848 .irq_unmask = octeon_irq_ciu2_enable,
1850 .irq_set_affinity = octeon_irq_ciu2_set_affinity,
1851 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
1855 static struct irq_chip octeon_irq_chip_ciu2_mbox = {
1857 .irq_enable = octeon_irq_ciu2_mbox_enable_all,
1858 .irq_disable = octeon_irq_ciu2_mbox_disable_all,
1859 .irq_ack = octeon_irq_ciu2_mbox_disable_local,
1860 .irq_eoi = octeon_irq_ciu2_mbox_enable_local,
1862 .irq_cpu_online = octeon_irq_ciu2_mbox_enable_local,
1863 .irq_cpu_offline = octeon_irq_ciu2_mbox_disable_local,
1864 .flags = IRQCHIP_ONOFFLINE_ENABLED,
1867 static struct irq_chip octeon_irq_chip_ciu2_wd = {
1869 .irq_enable = octeon_irq_ciu2_wd_enable,
1870 .irq_disable = octeon_irq_ciu2_disable_all,
1871 .irq_mask = octeon_irq_ciu2_disable_local,
1872 .irq_unmask = octeon_irq_ciu2_enable_local,
1875 static struct irq_chip octeon_irq_chip_ciu2_gpio = {
1877 .irq_enable = octeon_irq_ciu2_enable_gpio,
1878 .irq_disable = octeon_irq_ciu2_disable_gpio,
1879 .irq_ack = octeon_irq_ciu_gpio_ack,
1880 .irq_mask = octeon_irq_ciu2_disable_local,
1881 .irq_unmask = octeon_irq_ciu2_enable,
1882 .irq_set_type = octeon_irq_ciu_gpio_set_type,
1884 .irq_set_affinity = octeon_irq_ciu2_set_affinity,
1885 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
1887 .flags = IRQCHIP_SET_TYPE_MASKED,
1890 static int octeon_irq_ciu2_xlat(struct irq_domain *d,
1891 struct device_node *node,
1893 unsigned int intsize,
1894 unsigned long *out_hwirq,
1895 unsigned int *out_type)
1897 unsigned int ciu, bit;
1902 *out_hwirq = (ciu << 6) | bit;
1908 static bool octeon_irq_ciu2_is_edge(unsigned int line, unsigned int bit)
1912 if (line == 3) /* MIO */
1914 case 2: /* IPD_DRP */
1915 case 8 ... 11: /* Timers */
1922 else if (line == 6) /* PKT */
1924 case 52 ... 53: /* ILK_DRP */
1925 case 8 ... 12: /* GMX_DRP */
1934 static int octeon_irq_ciu2_map(struct irq_domain *d,
1935 unsigned int virq, irq_hw_number_t hw)
1937 unsigned int line = hw >> 6;
1938 unsigned int bit = hw & 63;
1941 * Don't map irq if it is reserved for GPIO.
1942 * (Line 7 are the GPIO lines.)
1947 if (line > 7 || octeon_irq_ciu_to_irq[line][bit] != 0)
1950 if (octeon_irq_ciu2_is_edge(line, bit))
1951 octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1952 &octeon_irq_chip_ciu2_edge,
1955 octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1956 &octeon_irq_chip_ciu2,
1962 static struct irq_domain_ops octeon_irq_domain_ciu2_ops = {
1963 .map = octeon_irq_ciu2_map,
1964 .unmap = octeon_irq_free_cd,
1965 .xlate = octeon_irq_ciu2_xlat,
1968 static void octeon_irq_ciu2(void)
1973 u64 src_reg, src, sum;
1974 const unsigned long core_id = cvmx_get_core_num();
1976 sum = cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(core_id)) & 0xfful;
1981 line = fls64(sum) - 1;
1982 src_reg = CVMX_CIU2_SRC_PPX_IP2_WRKQ(core_id) + (0x1000 * line);
1983 src = cvmx_read_csr(src_reg);
1988 bit = fls64(src) - 1;
1989 irq = octeon_irq_ciu_to_irq[line][bit];
1997 spurious_interrupt();
1999 /* CN68XX pass 1.x has an errata that accessing the ACK registers
2000 can stop interrupts from propagating */
2001 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
2002 cvmx_read_csr(CVMX_CIU2_INTR_CIU_READY);
2004 cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP2(core_id));
2008 static void octeon_irq_ciu2_mbox(void)
2012 const unsigned long core_id = cvmx_get_core_num();
2013 u64 sum = cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP3(core_id)) >> 60;
2018 line = fls64(sum) - 1;
2020 do_IRQ(OCTEON_IRQ_MBOX0 + line);
2024 spurious_interrupt();
2026 /* CN68XX pass 1.x has an errata that accessing the ACK registers
2027 can stop interrupts from propagating */
2028 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
2029 cvmx_read_csr(CVMX_CIU2_INTR_CIU_READY);
2031 cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP3(core_id));
2035 static int __init octeon_irq_init_ciu2(
2036 struct device_node *ciu_node, struct device_node *parent)
2039 struct irq_domain *ciu_domain = NULL;
2041 octeon_irq_init_ciu2_percpu();
2042 octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu2;
2044 octeon_irq_gpio_chip = &octeon_irq_chip_ciu2_gpio;
2045 octeon_irq_ip2 = octeon_irq_ciu2;
2046 octeon_irq_ip3 = octeon_irq_ciu2_mbox;
2047 octeon_irq_ip4 = octeon_irq_ip4_mask;
2050 octeon_irq_init_core();
2052 ciu_domain = irq_domain_add_tree(
2053 ciu_node, &octeon_irq_domain_ciu2_ops, NULL);
2054 irq_set_default_host(ciu_domain);
2057 for (i = 0; i < 64; i++) {
2058 r = octeon_irq_force_ciu_mapping(
2059 ciu_domain, i + OCTEON_IRQ_WORKQ0, 0, i);
2064 for (i = 0; i < 32; i++) {
2065 r = octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i, 0,
2066 &octeon_irq_chip_ciu2_wd, handle_level_irq);
2071 for (i = 0; i < 4; i++) {
2072 r = octeon_irq_force_ciu_mapping(
2073 ciu_domain, i + OCTEON_IRQ_TIMER0, 3, i + 8);
2078 for (i = 0; i < 4; i++) {
2079 r = octeon_irq_force_ciu_mapping(
2080 ciu_domain, i + OCTEON_IRQ_PCI_INT0, 4, i);
2085 for (i = 0; i < 4; i++) {
2086 r = octeon_irq_force_ciu_mapping(
2087 ciu_domain, i + OCTEON_IRQ_PCI_MSI0, 4, i + 8);
2092 irq_set_chip_and_handler(OCTEON_IRQ_MBOX0, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq);
2093 irq_set_chip_and_handler(OCTEON_IRQ_MBOX1, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq);
2094 irq_set_chip_and_handler(OCTEON_IRQ_MBOX2, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq);
2095 irq_set_chip_and_handler(OCTEON_IRQ_MBOX3, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq);
2097 /* Enable the CIU lines */
2098 set_c0_status(STATUSF_IP3 | STATUSF_IP2);
2099 clear_c0_status(STATUSF_IP4);
2105 struct octeon_irq_cib_host_data {
2106 raw_spinlock_t lock;
2112 struct octeon_irq_cib_chip_data {
2113 struct octeon_irq_cib_host_data *host_data;
2117 static void octeon_irq_cib_enable(struct irq_data *data)
2119 unsigned long flags;
2121 struct octeon_irq_cib_chip_data *cd = irq_data_get_irq_chip_data(data);
2122 struct octeon_irq_cib_host_data *host_data = cd->host_data;
2124 raw_spin_lock_irqsave(&host_data->lock, flags);
2125 en = cvmx_read_csr(host_data->en_reg);
2126 en |= 1ull << cd->bit;
2127 cvmx_write_csr(host_data->en_reg, en);
2128 raw_spin_unlock_irqrestore(&host_data->lock, flags);
2131 static void octeon_irq_cib_disable(struct irq_data *data)
2133 unsigned long flags;
2135 struct octeon_irq_cib_chip_data *cd = irq_data_get_irq_chip_data(data);
2136 struct octeon_irq_cib_host_data *host_data = cd->host_data;
2138 raw_spin_lock_irqsave(&host_data->lock, flags);
2139 en = cvmx_read_csr(host_data->en_reg);
2140 en &= ~(1ull << cd->bit);
2141 cvmx_write_csr(host_data->en_reg, en);
2142 raw_spin_unlock_irqrestore(&host_data->lock, flags);
2145 static int octeon_irq_cib_set_type(struct irq_data *data, unsigned int t)
2147 irqd_set_trigger_type(data, t);
2148 return IRQ_SET_MASK_OK;
2151 static struct irq_chip octeon_irq_chip_cib = {
2153 .irq_enable = octeon_irq_cib_enable,
2154 .irq_disable = octeon_irq_cib_disable,
2155 .irq_mask = octeon_irq_cib_disable,
2156 .irq_unmask = octeon_irq_cib_enable,
2157 .irq_set_type = octeon_irq_cib_set_type,
2160 static int octeon_irq_cib_xlat(struct irq_domain *d,
2161 struct device_node *node,
2163 unsigned int intsize,
2164 unsigned long *out_hwirq,
2165 unsigned int *out_type)
2167 unsigned int type = 0;
2173 case 0: /* unofficial value, but we might as well let it work. */
2174 case 4: /* official value for level triggering. */
2175 *out_type = IRQ_TYPE_LEVEL_HIGH;
2177 case 1: /* official value for edge triggering. */
2178 *out_type = IRQ_TYPE_EDGE_RISING;
2180 default: /* Nothing else is acceptable. */
2184 *out_hwirq = intspec[0];
2189 static int octeon_irq_cib_map(struct irq_domain *d,
2190 unsigned int virq, irq_hw_number_t hw)
2192 struct octeon_irq_cib_host_data *host_data = d->host_data;
2193 struct octeon_irq_cib_chip_data *cd;
2195 if (hw >= host_data->max_bits) {
2196 pr_err("ERROR: %s mapping %u is to big!\n",
2197 irq_domain_get_of_node(d)->name, (unsigned)hw);
2201 cd = kzalloc(sizeof(*cd), GFP_KERNEL);
2202 cd->host_data = host_data;
2205 irq_set_chip_and_handler(virq, &octeon_irq_chip_cib,
2207 irq_set_chip_data(virq, cd);
2211 static struct irq_domain_ops octeon_irq_domain_cib_ops = {
2212 .map = octeon_irq_cib_map,
2213 .unmap = octeon_irq_free_cd,
2214 .xlate = octeon_irq_cib_xlat,
2217 /* Chain to real handler. */
2218 static irqreturn_t octeon_irq_cib_handler(int my_irq, void *data)
2225 struct irq_domain *cib_domain = data;
2226 struct octeon_irq_cib_host_data *host_data = cib_domain->host_data;
2228 en = cvmx_read_csr(host_data->en_reg);
2229 raw = cvmx_read_csr(host_data->raw_reg);
2233 for (i = 0; i < host_data->max_bits; i++) {
2234 if ((bits & 1ull << i) == 0)
2236 irq = irq_find_mapping(cib_domain, i);
2238 unsigned long flags;
2240 pr_err("ERROR: CIB bit %d@%llx IRQ unhandled, disabling\n",
2241 i, host_data->raw_reg);
2242 raw_spin_lock_irqsave(&host_data->lock, flags);
2243 en = cvmx_read_csr(host_data->en_reg);
2245 cvmx_write_csr(host_data->en_reg, en);
2246 cvmx_write_csr(host_data->raw_reg, 1ull << i);
2247 raw_spin_unlock_irqrestore(&host_data->lock, flags);
2249 struct irq_desc *desc = irq_to_desc(irq);
2250 struct irq_data *irq_data = irq_desc_get_irq_data(desc);
2251 /* If edge, acknowledge the bit we will be sending. */
2252 if (irqd_get_trigger_type(irq_data) &
2254 cvmx_write_csr(host_data->raw_reg, 1ull << i);
2255 generic_handle_irq_desc(desc);
2262 static int __init octeon_irq_init_cib(struct device_node *ciu_node,
2263 struct device_node *parent)
2267 struct octeon_irq_cib_host_data *host_data;
2270 struct irq_domain *cib_domain;
2272 parent_irq = irq_of_parse_and_map(ciu_node, 0);
2274 pr_err("ERROR: Couldn't acquire parent_irq for %pOFn\n",
2279 host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);
2282 raw_spin_lock_init(&host_data->lock);
2284 addr = of_get_address(ciu_node, 0, NULL, NULL);
2286 pr_err("ERROR: Couldn't acquire reg(0) %pOFn\n", ciu_node);
2289 host_data->raw_reg = (u64)phys_to_virt(
2290 of_translate_address(ciu_node, addr));
2292 addr = of_get_address(ciu_node, 1, NULL, NULL);
2294 pr_err("ERROR: Couldn't acquire reg(1) %pOFn\n", ciu_node);
2297 host_data->en_reg = (u64)phys_to_virt(
2298 of_translate_address(ciu_node, addr));
2300 r = of_property_read_u32(ciu_node, "cavium,max-bits", &val);
2302 pr_err("ERROR: Couldn't read cavium,max-bits from %pOFn\n",
2306 host_data->max_bits = val;
2308 cib_domain = irq_domain_add_linear(ciu_node, host_data->max_bits,
2309 &octeon_irq_domain_cib_ops,
2312 pr_err("ERROR: Couldn't irq_domain_add_linear()\n");
2316 cvmx_write_csr(host_data->en_reg, 0); /* disable all IRQs */
2317 cvmx_write_csr(host_data->raw_reg, ~0); /* ack any outstanding */
2319 r = request_irq(parent_irq, octeon_irq_cib_handler,
2320 IRQF_NO_THREAD, "cib", cib_domain);
2322 pr_err("request_irq cib failed %d\n", r);
2325 pr_info("CIB interrupt controller probed: %llx %d\n",
2326 host_data->raw_reg, host_data->max_bits);
2330 int octeon_irq_ciu3_xlat(struct irq_domain *d,
2331 struct device_node *node,
2333 unsigned int intsize,
2334 unsigned long *out_hwirq,
2335 unsigned int *out_type)
2337 struct octeon_ciu3_info *ciu3_info = d->host_data;
2338 unsigned int hwirq, type, intsn_major;
2339 union cvmx_ciu3_iscx_ctl isc;
2346 if (hwirq >= (1 << 20))
2349 intsn_major = hwirq >> 12;
2350 switch (intsn_major) {
2351 case 0x04: /* Software handled separately. */
2357 isc.u64 = cvmx_read_csr(ciu3_info->ciu3_addr + CIU3_ISC_CTL(hwirq));
2362 case 4: /* official value for level triggering. */
2363 *out_type = IRQ_TYPE_LEVEL_HIGH;
2365 case 0: /* unofficial value, but we might as well let it work. */
2366 case 1: /* official value for edge triggering. */
2367 *out_type = IRQ_TYPE_EDGE_RISING;
2369 default: /* Nothing else is acceptable. */
2378 void octeon_irq_ciu3_enable(struct irq_data *data)
2381 union cvmx_ciu3_iscx_ctl isc_ctl;
2382 union cvmx_ciu3_iscx_w1c isc_w1c;
2385 struct octeon_ciu_chip_data *cd;
2387 cpu = next_cpu_for_irq(data);
2389 cd = irq_data_get_irq_chip_data(data);
2393 cvmx_write_csr(cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn), isc_w1c.u64);
2395 isc_ctl_addr = cd->ciu3_addr + CIU3_ISC_CTL(cd->intsn);
2398 isc_ctl.s.idt = per_cpu(octeon_irq_ciu3_idt_ip2, cpu);
2399 cvmx_write_csr(isc_ctl_addr, isc_ctl.u64);
2400 cvmx_read_csr(isc_ctl_addr);
2403 void octeon_irq_ciu3_disable(struct irq_data *data)
2406 union cvmx_ciu3_iscx_w1c isc_w1c;
2408 struct octeon_ciu_chip_data *cd;
2410 cd = irq_data_get_irq_chip_data(data);
2415 isc_ctl_addr = cd->ciu3_addr + CIU3_ISC_CTL(cd->intsn);
2416 cvmx_write_csr(cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn), isc_w1c.u64);
2417 cvmx_write_csr(isc_ctl_addr, 0);
2418 cvmx_read_csr(isc_ctl_addr);
2421 void octeon_irq_ciu3_ack(struct irq_data *data)
2424 union cvmx_ciu3_iscx_w1c isc_w1c;
2425 struct octeon_ciu_chip_data *cd;
2426 u32 trigger_type = irqd_get_trigger_type(data);
2429 * We use a single irq_chip, so we have to do nothing to ack a
2432 if (!(trigger_type & IRQ_TYPE_EDGE_BOTH))
2435 cd = irq_data_get_irq_chip_data(data);
2440 isc_w1c_addr = cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn);
2441 cvmx_write_csr(isc_w1c_addr, isc_w1c.u64);
2442 cvmx_read_csr(isc_w1c_addr);
2445 void octeon_irq_ciu3_mask(struct irq_data *data)
2447 union cvmx_ciu3_iscx_w1c isc_w1c;
2449 struct octeon_ciu_chip_data *cd;
2451 cd = irq_data_get_irq_chip_data(data);
2456 isc_w1c_addr = cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn);
2457 cvmx_write_csr(isc_w1c_addr, isc_w1c.u64);
2458 cvmx_read_csr(isc_w1c_addr);
2461 void octeon_irq_ciu3_mask_ack(struct irq_data *data)
2463 union cvmx_ciu3_iscx_w1c isc_w1c;
2465 struct octeon_ciu_chip_data *cd;
2466 u32 trigger_type = irqd_get_trigger_type(data);
2468 cd = irq_data_get_irq_chip_data(data);
2474 * We use a single irq_chip, so only ack an edge (!level)
2477 if (trigger_type & IRQ_TYPE_EDGE_BOTH)
2480 isc_w1c_addr = cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn);
2481 cvmx_write_csr(isc_w1c_addr, isc_w1c.u64);
2482 cvmx_read_csr(isc_w1c_addr);
2486 static int octeon_irq_ciu3_set_affinity(struct irq_data *data,
2487 const struct cpumask *dest, bool force)
2489 union cvmx_ciu3_iscx_ctl isc_ctl;
2490 union cvmx_ciu3_iscx_w1c isc_w1c;
2493 bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
2494 struct octeon_ciu_chip_data *cd = irq_data_get_irq_chip_data(data);
2496 if (!cpumask_subset(dest, cpumask_of_node(cd->ciu_node)))
2500 return IRQ_SET_MASK_OK;
2502 cd = irq_data_get_irq_chip_data(data);
2503 cpu = cpumask_first(dest);
2504 if (cpu >= nr_cpu_ids)
2505 cpu = smp_processor_id();
2506 cd->current_cpu = cpu;
2510 cvmx_write_csr(cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn), isc_w1c.u64);
2512 isc_ctl_addr = cd->ciu3_addr + CIU3_ISC_CTL(cd->intsn);
2515 isc_ctl.s.idt = per_cpu(octeon_irq_ciu3_idt_ip2, cpu);
2516 cvmx_write_csr(isc_ctl_addr, isc_ctl.u64);
2517 cvmx_read_csr(isc_ctl_addr);
2519 return IRQ_SET_MASK_OK;
2523 static struct irq_chip octeon_irq_chip_ciu3 = {
2525 .irq_startup = edge_startup,
2526 .irq_enable = octeon_irq_ciu3_enable,
2527 .irq_disable = octeon_irq_ciu3_disable,
2528 .irq_ack = octeon_irq_ciu3_ack,
2529 .irq_mask = octeon_irq_ciu3_mask,
2530 .irq_mask_ack = octeon_irq_ciu3_mask_ack,
2531 .irq_unmask = octeon_irq_ciu3_enable,
2532 .irq_set_type = octeon_irq_ciu_set_type,
2534 .irq_set_affinity = octeon_irq_ciu3_set_affinity,
2535 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
2539 int octeon_irq_ciu3_mapx(struct irq_domain *d, unsigned int virq,
2540 irq_hw_number_t hw, struct irq_chip *chip)
2542 struct octeon_ciu3_info *ciu3_info = d->host_data;
2543 struct octeon_ciu_chip_data *cd = kzalloc_node(sizeof(*cd), GFP_KERNEL,
2548 cd->current_cpu = -1;
2549 cd->ciu3_addr = ciu3_info->ciu3_addr;
2550 cd->ciu_node = ciu3_info->node;
2551 irq_set_chip_and_handler(virq, chip, handle_edge_irq);
2552 irq_set_chip_data(virq, cd);
2557 static int octeon_irq_ciu3_map(struct irq_domain *d,
2558 unsigned int virq, irq_hw_number_t hw)
2560 return octeon_irq_ciu3_mapx(d, virq, hw, &octeon_irq_chip_ciu3);
2563 static struct irq_domain_ops octeon_dflt_domain_ciu3_ops = {
2564 .map = octeon_irq_ciu3_map,
2565 .unmap = octeon_irq_free_cd,
2566 .xlate = octeon_irq_ciu3_xlat,
2569 static void octeon_irq_ciu3_ip2(void)
2571 union cvmx_ciu3_destx_pp_int dest_pp_int;
2572 struct octeon_ciu3_info *ciu3_info;
2575 ciu3_info = __this_cpu_read(octeon_ciu3_info);
2576 ciu3_addr = ciu3_info->ciu3_addr;
2578 dest_pp_int.u64 = cvmx_read_csr(ciu3_addr + CIU3_DEST_PP_INT(3 * cvmx_get_local_core_num()));
2580 if (likely(dest_pp_int.s.intr)) {
2581 irq_hw_number_t intsn = dest_pp_int.s.intsn;
2583 struct irq_domain *domain;
2584 /* Get the domain to use from the major block */
2585 int block = intsn >> 12;
2588 domain = ciu3_info->domain[block];
2589 if (ciu3_info->intsn2hw[block])
2590 hw = ciu3_info->intsn2hw[block](domain, intsn);
2594 ret = handle_domain_irq(domain, hw, NULL);
2596 union cvmx_ciu3_iscx_w1c isc_w1c;
2597 u64 isc_w1c_addr = ciu3_addr + CIU3_ISC_W1C(intsn);
2601 cvmx_write_csr(isc_w1c_addr, isc_w1c.u64);
2602 cvmx_read_csr(isc_w1c_addr);
2603 spurious_interrupt();
2606 spurious_interrupt();
2611 * 10 mbox per core starting from zero.
2612 * Base mbox is core * 10
2614 static unsigned int octeon_irq_ciu3_base_mbox_intsn(int core)
2616 /* SW (mbox) are 0x04 in bits 12..19 */
2617 return 0x04000 + CIU3_MBOX_PER_CORE * core;
2620 static unsigned int octeon_irq_ciu3_mbox_intsn_for_core(int core, unsigned int mbox)
2622 return octeon_irq_ciu3_base_mbox_intsn(core) + mbox;
2625 static unsigned int octeon_irq_ciu3_mbox_intsn_for_cpu(int cpu, unsigned int mbox)
2627 int local_core = octeon_coreid_for_cpu(cpu) & 0x3f;
2629 return octeon_irq_ciu3_mbox_intsn_for_core(local_core, mbox);
2632 static void octeon_irq_ciu3_mbox(void)
2634 union cvmx_ciu3_destx_pp_int dest_pp_int;
2635 struct octeon_ciu3_info *ciu3_info;
2637 int core = cvmx_get_local_core_num();
2639 ciu3_info = __this_cpu_read(octeon_ciu3_info);
2640 ciu3_addr = ciu3_info->ciu3_addr;
2642 dest_pp_int.u64 = cvmx_read_csr(ciu3_addr + CIU3_DEST_PP_INT(1 + 3 * core));
2644 if (likely(dest_pp_int.s.intr)) {
2645 irq_hw_number_t intsn = dest_pp_int.s.intsn;
2646 int mbox = intsn - octeon_irq_ciu3_base_mbox_intsn(core);
2648 if (likely(mbox >= 0 && mbox < CIU3_MBOX_PER_CORE)) {
2649 do_IRQ(mbox + OCTEON_IRQ_MBOX0);
2651 union cvmx_ciu3_iscx_w1c isc_w1c;
2652 u64 isc_w1c_addr = ciu3_addr + CIU3_ISC_W1C(intsn);
2656 cvmx_write_csr(isc_w1c_addr, isc_w1c.u64);
2657 cvmx_read_csr(isc_w1c_addr);
2658 spurious_interrupt();
2661 spurious_interrupt();
2665 void octeon_ciu3_mbox_send(int cpu, unsigned int mbox)
2667 struct octeon_ciu3_info *ciu3_info;
2669 union cvmx_ciu3_iscx_w1s isc_w1s;
2672 if (WARN_ON_ONCE(mbox >= CIU3_MBOX_PER_CORE))
2675 intsn = octeon_irq_ciu3_mbox_intsn_for_cpu(cpu, mbox);
2676 ciu3_info = per_cpu(octeon_ciu3_info, cpu);
2677 isc_w1s_addr = ciu3_info->ciu3_addr + CIU3_ISC_W1S(intsn);
2682 cvmx_write_csr(isc_w1s_addr, isc_w1s.u64);
2683 cvmx_read_csr(isc_w1s_addr);
2686 static void octeon_irq_ciu3_mbox_set_enable(struct irq_data *data, int cpu, bool en)
2688 struct octeon_ciu3_info *ciu3_info;
2690 u64 isc_ctl_addr, isc_w1c_addr;
2691 union cvmx_ciu3_iscx_ctl isc_ctl;
2692 unsigned int mbox = data->irq - OCTEON_IRQ_MBOX0;
2694 intsn = octeon_irq_ciu3_mbox_intsn_for_cpu(cpu, mbox);
2695 ciu3_info = per_cpu(octeon_ciu3_info, cpu);
2696 isc_w1c_addr = ciu3_info->ciu3_addr + CIU3_ISC_W1C(intsn);
2697 isc_ctl_addr = ciu3_info->ciu3_addr + CIU3_ISC_CTL(intsn);
2702 cvmx_write_csr(isc_w1c_addr, isc_ctl.u64);
2703 cvmx_write_csr(isc_ctl_addr, 0);
2705 unsigned int idt = per_cpu(octeon_irq_ciu3_idt_ip3, cpu);
2709 isc_ctl.s.idt = idt;
2710 cvmx_write_csr(isc_ctl_addr, isc_ctl.u64);
2712 cvmx_read_csr(isc_ctl_addr);
2715 static void octeon_irq_ciu3_mbox_enable(struct irq_data *data)
2718 unsigned int mbox = data->irq - OCTEON_IRQ_MBOX0;
2720 WARN_ON(mbox >= CIU3_MBOX_PER_CORE);
2722 for_each_online_cpu(cpu)
2723 octeon_irq_ciu3_mbox_set_enable(data, cpu, true);
2726 static void octeon_irq_ciu3_mbox_disable(struct irq_data *data)
2729 unsigned int mbox = data->irq - OCTEON_IRQ_MBOX0;
2731 WARN_ON(mbox >= CIU3_MBOX_PER_CORE);
2733 for_each_online_cpu(cpu)
2734 octeon_irq_ciu3_mbox_set_enable(data, cpu, false);
2737 static void octeon_irq_ciu3_mbox_ack(struct irq_data *data)
2739 struct octeon_ciu3_info *ciu3_info;
2742 union cvmx_ciu3_iscx_w1c isc_w1c;
2743 unsigned int mbox = data->irq - OCTEON_IRQ_MBOX0;
2745 intsn = octeon_irq_ciu3_mbox_intsn_for_core(cvmx_get_local_core_num(), mbox);
2750 ciu3_info = __this_cpu_read(octeon_ciu3_info);
2751 isc_w1c_addr = ciu3_info->ciu3_addr + CIU3_ISC_W1C(intsn);
2752 cvmx_write_csr(isc_w1c_addr, isc_w1c.u64);
2753 cvmx_read_csr(isc_w1c_addr);
2756 static void octeon_irq_ciu3_mbox_cpu_online(struct irq_data *data)
2758 octeon_irq_ciu3_mbox_set_enable(data, smp_processor_id(), true);
2761 static void octeon_irq_ciu3_mbox_cpu_offline(struct irq_data *data)
2763 octeon_irq_ciu3_mbox_set_enable(data, smp_processor_id(), false);
2766 static int octeon_irq_ciu3_alloc_resources(struct octeon_ciu3_info *ciu3_info)
2768 u64 b = ciu3_info->ciu3_addr;
2769 int idt_ip2, idt_ip3, idt_ip4;
2771 int core = cvmx_get_local_core_num();
2774 __this_cpu_write(octeon_ciu3_info, ciu3_info);
2777 * 4 idt per core starting from 1 because zero is reserved.
2778 * Base idt per core is 4 * core + 1
2780 idt_ip2 = core * 4 + 1;
2781 idt_ip3 = core * 4 + 2;
2782 idt_ip4 = core * 4 + 3;
2783 unused_idt2 = core * 4 + 4;
2784 __this_cpu_write(octeon_irq_ciu3_idt_ip2, idt_ip2);
2785 __this_cpu_write(octeon_irq_ciu3_idt_ip3, idt_ip3);
2787 /* ip2 interrupts for this CPU */
2788 cvmx_write_csr(b + CIU3_IDT_CTL(idt_ip2), 0);
2789 cvmx_write_csr(b + CIU3_IDT_PP(idt_ip2, 0), 1ull << core);
2790 cvmx_write_csr(b + CIU3_IDT_IO(idt_ip2), 0);
2792 /* ip3 interrupts for this CPU */
2793 cvmx_write_csr(b + CIU3_IDT_CTL(idt_ip3), 1);
2794 cvmx_write_csr(b + CIU3_IDT_PP(idt_ip3, 0), 1ull << core);
2795 cvmx_write_csr(b + CIU3_IDT_IO(idt_ip3), 0);
2797 /* ip4 interrupts for this CPU */
2798 cvmx_write_csr(b + CIU3_IDT_CTL(idt_ip4), 2);
2799 cvmx_write_csr(b + CIU3_IDT_PP(idt_ip4, 0), 0);
2800 cvmx_write_csr(b + CIU3_IDT_IO(idt_ip4), 0);
2802 cvmx_write_csr(b + CIU3_IDT_CTL(unused_idt2), 0);
2803 cvmx_write_csr(b + CIU3_IDT_PP(unused_idt2, 0), 0);
2804 cvmx_write_csr(b + CIU3_IDT_IO(unused_idt2), 0);
2806 for (i = 0; i < CIU3_MBOX_PER_CORE; i++) {
2807 unsigned int intsn = octeon_irq_ciu3_mbox_intsn_for_core(core, i);
2809 cvmx_write_csr(b + CIU3_ISC_W1C(intsn), 2);
2810 cvmx_write_csr(b + CIU3_ISC_CTL(intsn), 0);
2816 static void octeon_irq_setup_secondary_ciu3(void)
2818 struct octeon_ciu3_info *ciu3_info;
2820 ciu3_info = octeon_ciu3_info_per_node[cvmx_get_node_num()];
2821 octeon_irq_ciu3_alloc_resources(ciu3_info);
2824 /* Enable the CIU lines */
2825 set_c0_status(STATUSF_IP3 | STATUSF_IP2);
2826 if (octeon_irq_use_ip4)
2827 set_c0_status(STATUSF_IP4);
2829 clear_c0_status(STATUSF_IP4);
2832 static struct irq_chip octeon_irq_chip_ciu3_mbox = {
2834 .irq_enable = octeon_irq_ciu3_mbox_enable,
2835 .irq_disable = octeon_irq_ciu3_mbox_disable,
2836 .irq_ack = octeon_irq_ciu3_mbox_ack,
2838 .irq_cpu_online = octeon_irq_ciu3_mbox_cpu_online,
2839 .irq_cpu_offline = octeon_irq_ciu3_mbox_cpu_offline,
2840 .flags = IRQCHIP_ONOFFLINE_ENABLED,
2843 static int __init octeon_irq_init_ciu3(struct device_node *ciu_node,
2844 struct device_node *parent)
2848 struct irq_domain *domain;
2849 struct octeon_ciu3_info *ciu3_info;
2850 const __be32 *zero_addr;
2852 union cvmx_ciu3_const consts;
2854 node = 0; /* of_node_to_nid(ciu_node); */
2855 ciu3_info = kzalloc_node(sizeof(*ciu3_info), GFP_KERNEL, node);
2860 zero_addr = of_get_address(ciu_node, 0, NULL, NULL);
2861 if (WARN_ON(!zero_addr))
2864 base_addr = of_translate_address(ciu_node, zero_addr);
2865 base_addr = (u64)phys_to_virt(base_addr);
2867 ciu3_info->ciu3_addr = base_addr;
2868 ciu3_info->node = node;
2870 consts.u64 = cvmx_read_csr(base_addr + CIU3_CONST);
2872 octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu3;
2874 octeon_irq_ip2 = octeon_irq_ciu3_ip2;
2875 octeon_irq_ip3 = octeon_irq_ciu3_mbox;
2876 octeon_irq_ip4 = octeon_irq_ip4_mask;
2878 if (node == cvmx_get_node_num()) {
2880 octeon_irq_init_core();
2882 /* Only do per CPU things if it is the CIU of the boot node. */
2883 i = irq_alloc_descs_from(OCTEON_IRQ_MBOX0, 8, node);
2886 for (i = 0; i < 8; i++)
2887 irq_set_chip_and_handler(i + OCTEON_IRQ_MBOX0,
2888 &octeon_irq_chip_ciu3_mbox, handle_percpu_irq);
2892 * Initialize all domains to use the default domain. Specific major
2893 * blocks will overwrite the default domain as needed.
2895 domain = irq_domain_add_tree(ciu_node, &octeon_dflt_domain_ciu3_ops,
2897 for (i = 0; i < MAX_CIU3_DOMAINS; i++)
2898 ciu3_info->domain[i] = domain;
2900 octeon_ciu3_info_per_node[node] = ciu3_info;
2902 if (node == cvmx_get_node_num()) {
2903 /* Only do per CPU things if it is the CIU of the boot node. */
2904 octeon_irq_ciu3_alloc_resources(ciu3_info);
2906 irq_set_default_host(domain);
2908 octeon_irq_use_ip4 = false;
2909 /* Enable the CIU lines */
2910 set_c0_status(STATUSF_IP2 | STATUSF_IP3);
2911 clear_c0_status(STATUSF_IP4);
2917 static struct of_device_id ciu_types[] __initdata = {
2918 {.compatible = "cavium,octeon-3860-ciu", .data = octeon_irq_init_ciu},
2919 {.compatible = "cavium,octeon-3860-gpio", .data = octeon_irq_init_gpio},
2920 {.compatible = "cavium,octeon-6880-ciu2", .data = octeon_irq_init_ciu2},
2921 {.compatible = "cavium,octeon-7890-ciu3", .data = octeon_irq_init_ciu3},
2922 {.compatible = "cavium,octeon-7130-cib", .data = octeon_irq_init_cib},
2926 void __init arch_init_irq(void)
2929 /* Set the default affinity to the boot cpu. */
2930 cpumask_clear(irq_default_affinity);
2931 cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
2933 of_irq_init(ciu_types);
2936 asmlinkage void plat_irq_dispatch(void)
2938 unsigned long cop0_cause;
2939 unsigned long cop0_status;
2942 cop0_cause = read_c0_cause();
2943 cop0_status = read_c0_status();
2944 cop0_cause &= cop0_status;
2945 cop0_cause &= ST0_IM;
2947 if (cop0_cause & STATUSF_IP2)
2949 else if (cop0_cause & STATUSF_IP3)
2951 else if (cop0_cause & STATUSF_IP4)
2953 else if (cop0_cause)
2954 do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE);
2960 #ifdef CONFIG_HOTPLUG_CPU
2962 void octeon_fixup_irqs(void)
2967 #endif /* CONFIG_HOTPLUG_CPU */
2969 struct irq_domain *octeon_irq_get_block_domain(int node, uint8_t block)
2971 struct octeon_ciu3_info *ciu3_info;
2973 ciu3_info = octeon_ciu3_info_per_node[node & CVMX_NODE_MASK];
2974 return ciu3_info->domain[block];
2976 EXPORT_SYMBOL(octeon_irq_get_block_domain);