arch/mips/boot/dts/mscc/ocelot.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /* Copyright (c) 2017 Microsemi Corporation */
   3
   4 / {
   5         #address-cells = <1>;
   6         #size-cells = <1>;
   7         compatible = "mscc,ocelot";
   8
   9         cpus {
  10                 #address-cells = <1>;
  11                 #size-cells = <0>;
  12
  13                 cpu@0 {
  14                         compatible = "mips,mips24KEc";
  15                         device_type = "cpu";
  16                         clocks = <&cpu_clk>;
  17                         reg = <0>;
  18                 };
  19         };
  20
  21         aliases {
  22                 serial0 = &uart0;
  23         };
  24
  25         cpuintc: interrupt-controller {
  26                 #address-cells = <0>;
  27                 #interrupt-cells = <1>;
  28                 interrupt-controller;
  29                 compatible = "mti,cpu-interrupt-controller";
  30         };
  31
  32         cpu_clk: cpu-clock {
  33                 compatible = "fixed-clock";
  34                 #clock-cells = <0>;
  35                 clock-frequency = <500000000>;
  36         };
  37
  38         ahb_clk: ahb-clk {
  39                 compatible = "fixed-factor-clock";
  40                 #clock-cells = <0>;
  41                 clocks = <&cpu_clk>;
  42                 clock-div = <2>;
  43                 clock-mult = <1>;
  44         };
  45
  46         ahb@70000000 {
  47                 compatible = "simple-bus";
  48                 #address-cells = <1>;
  49                 #size-cells = <1>;
  50                 ranges = <0 0x70000000 0x2000000>;
  51
  52                 interrupt-parent = <&intc>;
  53
  54                 cpu_ctrl: syscon@0 {
  55                         compatible = "mscc,ocelot-cpu-syscon", "syscon";
  56                         reg = <0x0 0x2c>;
  57                 };
  58
  59                 intc: interrupt-controller@70 {
  60                         compatible = "mscc,ocelot-icpu-intr";
  61                         reg = <0x70 0x70>;
  62                         #interrupt-cells = <1>;
  63                         interrupt-controller;
  64                         interrupt-parent = <&cpuintc>;
  65                         interrupts = <2>;
  66                 };
  67
  68                 uart0: serial@100000 {
  69                         pinctrl-0 = <&uart_pins>;
  70                         pinctrl-names = "default";
  71                         compatible = "ns16550a";
  72                         reg = <0x100000 0x20>;
  73                         interrupts = <6>;
  74                         clocks = <&ahb_clk>;
  75                         reg-io-width = <4>;
  76                         reg-shift = <2>;
  77
  78                         status = "disabled";
  79                 };
  80
  81                 uart2: serial@100800 {
  82                         pinctrl-0 = <&uart2_pins>;
  83                         pinctrl-names = "default";
  84                         compatible = "ns16550a";
  85                         reg = <0x100800 0x20>;
  86                         interrupts = <7>;
  87                         clocks = <&ahb_clk>;
  88                         reg-io-width = <4>;
  89                         reg-shift = <2>;
  90
  91                         status = "disabled";
  92                 };
  93
  94                 switch@1010000 {
  95                         compatible = "mscc,vsc7514-switch";
  96                         reg = <0x1010000 0x10000>,
  97                               <0x1030000 0x10000>,
  98                               <0x1080000 0x100>,
  99                               <0x10d0000 0x10000>,
 100                               <0x11e0000 0x100>,
 101                               <0x11f0000 0x100>,
 102                               <0x1200000 0x100>,
 103                               <0x1210000 0x100>,
 104                               <0x1220000 0x100>,
 105                               <0x1230000 0x100>,
 106                               <0x1240000 0x100>,
 107                               <0x1250000 0x100>,
 108                               <0x1260000 0x100>,
 109                               <0x1270000 0x100>,
 110                               <0x1280000 0x100>,
 111                               <0x1800000 0x80000>,
 112                               <0x1880000 0x10000>;
 113                         reg-names = "sys", "rew", "qs", "hsio", "port0",
 114                                     "port1", "port2", "port3", "port4", "port5",
 115                                     "port6", "port7", "port8", "port9", "port10",
 116                                     "qsys", "ana";
 117                         interrupts = <21 22>;
 118                         interrupt-names = "xtr", "inj";
 119
 120                         ethernet-ports {
 121                                 #address-cells = <1>;
 122                                 #size-cells = <0>;
 123
 124                                 port0: port@0 {
 125                                         reg = <0>;
 126                                 };
 127                                 port1: port@1 {
 128                                         reg = <1>;
 129                                 };
 130                                 port2: port@2 {
 131                                         reg = <2>;
 132                                 };
 133                                 port3: port@3 {
 134                                         reg = <3>;
 135                                 };
 136                                 port4: port@4 {
 137                                         reg = <4>;
 138                                 };
 139                                 port5: port@5 {
 140                                         reg = <5>;
 141                                 };
 142                                 port6: port@6 {
 143                                         reg = <6>;
 144                                 };
 145                                 port7: port@7 {
 146                                         reg = <7>;
 147                                 };
 148                                 port8: port@8 {
 149                                         reg = <8>;
 150                                 };
 151                                 port9: port@9 {
 152                                         reg = <9>;
 153                                 };
 154                                 port10: port@10 {
 155                                         reg = <10>;
 156                                 };
 157                         };
 158                 };
 159
 160                 reset@1070008 {
 161                         compatible = "mscc,ocelot-chip-reset";
 162                         reg = <0x1070008 0x4>;
 163                 };
 164
 165                 gpio: pinctrl@1070034 {
 166                         compatible = "mscc,ocelot-pinctrl";
 167                         reg = <0x1070034 0x68>;
 168                         gpio-controller;
 169                         #gpio-cells = <2>;
 170                         gpio-ranges = <&gpio 0 0 22>;
 171
 172                         uart_pins: uart-pins {
 173                                 pins = "GPIO_6", "GPIO_7";
 174                                 function = "uart";
 175                         };
 176
 177                         uart2_pins: uart2-pins {
 178                                 pins = "GPIO_12", "GPIO_13";
 179                                 function = "uart2";
 180                         };
 181
 182                         miim1: miim1 {
 183                                 pins = "GPIO_14", "GPIO_15";
 184                                 function = "miim1";
 185                         };
 186                 };
 187
 188                 mdio0: mdio@107009c {
 189                         #address-cells = <1>;
 190                         #size-cells = <0>;
 191                         compatible = "mscc,ocelot-miim";
 192                         reg = <0x107009c 0x24>, <0x10700f0 0x8>;
 193                         interrupts = <14>;
 194                         status = "disabled";
 195
 196                         phy0: ethernet-phy@0 {
 197                                 reg = <0>;
 198                         };
 199                         phy1: ethernet-phy@1 {
 200                                 reg = <1>;
 201                         };
 202                         phy2: ethernet-phy@2 {
 203                                 reg = <2>;
 204                         };
 205                         phy3: ethernet-phy@3 {
 206                                 reg = <3>;
 207                         };
 208                 };
 209
 210                 mdio1: mdio@10700c0 {
 211                         #address-cells = <1>;
 212                         #size-cells = <0>;
 213                         compatible = "mscc,ocelot-miim";
 214                         reg = <0x10700c0 0x24>;
 215                         interrupts = <15>;
 216                         pinctrl-names = "default";
 217                         pinctrl-0 = <&miim1>;
 218                         status = "disabled";
 219                 };
 220         };
 221 };