2 * BRIEF MODULE DESCRIPTION
3 * Au1xx0 Power Management routines.
5 * Copyright 2001, 2008 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. <source@mvista.com>
8 * Some of the routines are right out of init/main.c, whose
9 * copyrights apply here.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 #include <linux/init.h>
34 #include <linux/sysctl.h>
35 #include <linux/jiffies.h>
37 #include <asm/uaccess.h>
38 #include <asm/mach-au1x00/au1000.h>
41 * We need to save/restore a bunch of core registers that are
42 * either volatile or reset to some state across a processor sleep.
43 * If reading a register doesn't provide a proper result for a
44 * later restore, we have to provide a function for loading that
45 * register and save a copy.
47 * We only have to save/restore registers that aren't otherwise
48 * done as part of a driver pm_* function.
50 static unsigned int sleep_usb[2];
51 static unsigned int sleep_sys_clocks[5];
52 static unsigned int sleep_sys_pinfunc;
53 static unsigned int sleep_static_memctlr[4][3];
56 static void save_core_regs(void)
58 #ifndef CONFIG_SOC_AU1200
59 /* Shutdown USB host/device. */
60 sleep_usb[0] = au_readl(USB_HOST_CONFIG);
62 /* There appears to be some undocumented reset register.... */
63 au_writel(0, 0xb0100004);
65 au_writel(0, USB_HOST_CONFIG);
68 sleep_usb[1] = au_readl(USBD_ENABLE);
69 au_writel(0, USBD_ENABLE);
74 /* enable access to OTG mmio so we can save OTG CAP/MUX.
75 * FIXME: write an OTG driver and move this stuff there!
77 au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
79 sleep_usb[0] = au_readl(0xb4020020); /* OTG_CAP */
80 sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */
83 /* Clocks and PLLs. */
84 sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0);
85 sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1);
86 sleep_sys_clocks[2] = au_readl(SYS_CLKSRC);
87 sleep_sys_clocks[3] = au_readl(SYS_CPUPLL);
88 sleep_sys_clocks[4] = au_readl(SYS_AUXPLL);
91 sleep_sys_pinfunc = au_readl(SYS_PINFUNC);
93 /* Save the static memory controller configuration. */
94 sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0);
95 sleep_static_memctlr[0][1] = au_readl(MEM_STTIME0);
96 sleep_static_memctlr[0][2] = au_readl(MEM_STADDR0);
97 sleep_static_memctlr[1][0] = au_readl(MEM_STCFG1);
98 sleep_static_memctlr[1][1] = au_readl(MEM_STTIME1);
99 sleep_static_memctlr[1][2] = au_readl(MEM_STADDR1);
100 sleep_static_memctlr[2][0] = au_readl(MEM_STCFG2);
101 sleep_static_memctlr[2][1] = au_readl(MEM_STTIME2);
102 sleep_static_memctlr[2][2] = au_readl(MEM_STADDR2);
103 sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3);
104 sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3);
105 sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3);
108 static void restore_core_regs(void)
110 /* restore clock configuration. Writing CPUPLL last will
111 * stall a bit and stabilize other clocks (unless this is
112 * one of those Au1000 with a write-only PLL, where we dont
113 * have a valid value)
115 au_writel(sleep_sys_clocks[0], SYS_FREQCTRL0);
116 au_writel(sleep_sys_clocks[1], SYS_FREQCTRL1);
117 au_writel(sleep_sys_clocks[2], SYS_CLKSRC);
118 au_writel(sleep_sys_clocks[4], SYS_AUXPLL);
119 if (!au1xxx_cpu_has_pll_wo())
120 au_writel(sleep_sys_clocks[3], SYS_CPUPLL);
123 au_writel(sleep_sys_pinfunc, SYS_PINFUNC);
126 #ifndef CONFIG_SOC_AU1200
127 au_writel(sleep_usb[0], USB_HOST_CONFIG);
128 au_writel(sleep_usb[1], USBD_ENABLE);
131 /* enable access to OTG memory */
132 au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
135 /* restore OTG caps and port mux. */
136 au_writel(sleep_usb[0], 0xb4020020 + 0); /* OTG_CAP */
138 au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */
142 /* Restore the static memory controller configuration. */
143 au_writel(sleep_static_memctlr[0][0], MEM_STCFG0);
144 au_writel(sleep_static_memctlr[0][1], MEM_STTIME0);
145 au_writel(sleep_static_memctlr[0][2], MEM_STADDR0);
146 au_writel(sleep_static_memctlr[1][0], MEM_STCFG1);
147 au_writel(sleep_static_memctlr[1][1], MEM_STTIME1);
148 au_writel(sleep_static_memctlr[1][2], MEM_STADDR1);
149 au_writel(sleep_static_memctlr[2][0], MEM_STCFG2);
150 au_writel(sleep_static_memctlr[2][1], MEM_STTIME2);
151 au_writel(sleep_static_memctlr[2][2], MEM_STADDR2);
152 au_writel(sleep_static_memctlr[3][0], MEM_STCFG3);
153 au_writel(sleep_static_memctlr[3][1], MEM_STTIME3);
154 au_writel(sleep_static_memctlr[3][2], MEM_STADDR3);
161 switch (alchemy_get_cputype()) {
162 case ALCHEMY_CPU_AU1000:
163 case ALCHEMY_CPU_AU1500:
164 case ALCHEMY_CPU_AU1100:
165 alchemy_sleep_au1000();
167 case ALCHEMY_CPU_AU1550:
168 case ALCHEMY_CPU_AU1200:
169 alchemy_sleep_au1550();