1 menu "MIPS architecture"
8 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
12 prompt "Target select"
15 config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
17 select ROM_EXCEPTION_VECTORS
18 select SUPPORTS_BIG_ENDIAN
19 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
21 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
23 select SUPPORTS_LITTLE_ENDIAN
29 select DYNAMIC_IO_PORT_BASE
31 select MIPS_L1_CACHE_SHIFT_6
35 select ROM_EXCEPTION_VECTORS
36 select SUPPORTS_BIG_ENDIAN
37 select SUPPORTS_CPU_MIPS32_R1
38 select SUPPORTS_CPU_MIPS32_R2
39 select SUPPORTS_CPU_MIPS32_R6
40 select SUPPORTS_CPU_MIPS64_R1
41 select SUPPORTS_CPU_MIPS64_R2
42 select SUPPORTS_CPU_MIPS64_R6
43 select SUPPORTS_LITTLE_ENDIAN
49 select ROM_EXCEPTION_VECTORS
50 select SUPPORTS_BIG_ENDIAN
51 select SUPPORTS_CPU_MIPS32_R1
52 select SUPPORTS_CPU_MIPS32_R2
53 select SYS_MIPS_CACHE_INIT_RAM_LOAD
56 bool "Support QCA/Atheros ath79"
62 bool "Support BMIPS SoCs"
72 bool "Support Microchip PIC32"
82 select MIPS_L1_CACHE_SHIFT_6
86 select ROM_EXCEPTION_VECTORS
87 select SUPPORTS_BIG_ENDIAN
88 select SUPPORTS_CPU_MIPS32_R1
89 select SUPPORTS_CPU_MIPS32_R2
90 select SUPPORTS_CPU_MIPS32_R6
91 select SUPPORTS_CPU_MIPS64_R1
92 select SUPPORTS_CPU_MIPS64_R2
93 select SUPPORTS_CPU_MIPS64_R6
94 select SUPPORTS_LITTLE_ENDIAN
98 bool "Support Imagination Xilfpga"
103 select MIPS_L1_CACHE_SHIFT_4
105 select ROM_EXCEPTION_VECTORS
106 select SUPPORTS_CPU_MIPS32_R1
107 select SUPPORTS_CPU_MIPS32_R2
108 select SUPPORTS_LITTLE_ENDIAN
111 This supports IMGTEC MIPSfpga platform
115 source "board/imgtec/boston/Kconfig"
116 source "board/imgtec/malta/Kconfig"
117 source "board/imgtec/xilfpga/Kconfig"
118 source "board/micronas/vct/Kconfig"
119 source "board/qemu-mips/Kconfig"
120 source "arch/mips/mach-ath79/Kconfig"
121 source "arch/mips/mach-bmips/Kconfig"
122 source "arch/mips/mach-pic32/Kconfig"
127 prompt "Endianness selection"
129 Some MIPS boards can be configured for either little or big endian
130 byte order. These modes require different U-Boot images. In general there
131 is one preferred byteorder for a particular system but some systems are
132 just as commonly used in the one or the other endianness.
134 config SYS_BIG_ENDIAN
136 depends on SUPPORTS_BIG_ENDIAN
138 config SYS_LITTLE_ENDIAN
140 depends on SUPPORTS_LITTLE_ENDIAN
145 prompt "CPU selection"
146 default CPU_MIPS32_R2
149 bool "MIPS32 Release 1"
150 depends on SUPPORTS_CPU_MIPS32_R1
153 Choose this option to build an U-Boot for release 1 through 5 of the
157 bool "MIPS32 Release 2"
158 depends on SUPPORTS_CPU_MIPS32_R2
161 Choose this option to build an U-Boot for release 2 through 5 of the
165 bool "MIPS32 Release 6"
166 depends on SUPPORTS_CPU_MIPS32_R6
169 Choose this option to build an U-Boot for release 6 or later of the
173 bool "MIPS64 Release 1"
174 depends on SUPPORTS_CPU_MIPS64_R1
177 Choose this option to build a kernel for release 1 through 5 of the
181 bool "MIPS64 Release 2"
182 depends on SUPPORTS_CPU_MIPS64_R2
185 Choose this option to build a kernel for release 2 through 5 of the
189 bool "MIPS64 Release 6"
190 depends on SUPPORTS_CPU_MIPS64_R6
193 Choose this option to build a kernel for release 6 or later of the
200 config ROM_EXCEPTION_VECTORS
201 bool "Build U-Boot image with exception vectors"
203 Enable this to include exception vectors in the U-Boot image. This is
204 required if the U-Boot entry point is equal to the address of the
205 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
206 U-Boot booted from parallel NOR flash).
207 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
208 In that case the image size will be reduced by 0x500 bytes.
211 hex "MIPS CM GCR Base Address"
213 default 0x16100000 if TARGET_BOSTON
216 The physical base address at which to map the MIPS Coherence Manager
217 Global Configuration Registers (GCRs). This should be set such that
218 the GCRs occupy a region of the physical address space which is
219 otherwise unused, or at minimum that software doesn't need to access.
223 menu "OS boot interface"
225 config MIPS_BOOT_CMDLINE_LEGACY
226 bool "Hand over legacy command line to Linux kernel"
229 Enable this option if you want U-Boot to hand over the Yamon-style
230 command line to the kernel. All bootargs will be prepared as argc/argv
231 compatible list. The argument count (argc) is stored in register $a0.
232 The address of the argument list (argv) is stored in register $a1.
234 config MIPS_BOOT_ENV_LEGACY
235 bool "Hand over legacy environment to Linux kernel"
238 Enable this option if you want U-Boot to hand over the Yamon-style
239 environment to the kernel. Information like memory size, initrd
240 address and size will be prepared as zero-terminated key/value list.
241 The address of the environment is stored in register $a2.
244 bool "Hand over a flattened device tree to Linux kernel"
247 Enable this option if you want U-Boot to hand over a flattened
248 device tree to the kernel. According to UHI register $a0 will be set
249 to -2 and the FDT address is stored in $a1.
253 config SUPPORTS_BIG_ENDIAN
256 config SUPPORTS_LITTLE_ENDIAN
259 config SUPPORTS_CPU_MIPS32_R1
262 config SUPPORTS_CPU_MIPS32_R2
265 config SUPPORTS_CPU_MIPS32_R6
268 config SUPPORTS_CPU_MIPS64_R1
271 config SUPPORTS_CPU_MIPS64_R2
274 config SUPPORTS_CPU_MIPS64_R6
279 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
283 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
288 config MIPS_TUNE_14KC
291 config MIPS_TUNE_24KC
294 config MIPS_TUNE_34KC
297 config MIPS_TUNE_74KC
309 config SYS_MIPS_CACHE_INIT_RAM_LOAD
312 config MIPS_INIT_STACK_IN_SRAM
316 Select this if the initial stack frame could be setup in SRAM.
317 Normally the initial stack frame is set up in DRAM which is often
318 only available after lowlevel_init. With this option the initial
319 stack frame and the early C environment is set up before
320 lowlevel_init. Thus lowlevel_init does not need to be implemented
323 config SYS_DCACHE_SIZE
327 The total size of the L1 Dcache, if known at compile time.
329 config SYS_DCACHE_LINE_SIZE
333 The size of L1 Dcache lines, if known at compile time.
335 config SYS_ICACHE_SIZE
339 The total size of the L1 ICache, if known at compile time.
341 config SYS_ICACHE_LINE_SIZE
345 The size of L1 Icache lines, if known at compile time.
347 config SYS_CACHE_SIZE_AUTO
348 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
349 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
351 Select this (or let it be auto-selected by not defining any cache
352 sizes) in order to allow U-Boot to automatically detect the sizes
353 of caches at runtime. This has a small cost in code size & runtime
354 so if you know the cache configuration for your system at compile
355 time it would be beneficial to configure it.
357 config MIPS_L1_CACHE_SHIFT_4
360 config MIPS_L1_CACHE_SHIFT_5
363 config MIPS_L1_CACHE_SHIFT_6
366 config MIPS_L1_CACHE_SHIFT_7
369 config MIPS_L1_CACHE_SHIFT
371 default "7" if MIPS_L1_CACHE_SHIFT_7
372 default "6" if MIPS_L1_CACHE_SHIFT_6
373 default "5" if MIPS_L1_CACHE_SHIFT_5
374 default "4" if MIPS_L1_CACHE_SHIFT_4
380 Select this if your system includes an L2 cache and you want U-Boot
381 to initialise & maintain it.
383 config DYNAMIC_IO_PORT_BASE
389 Select this if your system contains a MIPS Coherence Manager and you
390 wish U-Boot to configure it or make use of it to retrieve system
391 information such as cache configuration.