1 menu "MIPS architecture"
8 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
12 prompt "Target select"
15 config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
17 select ROM_EXCEPTION_VECTORS
18 select SUPPORTS_BIG_ENDIAN
19 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
21 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
23 select SUPPORTS_LITTLE_ENDIAN
29 select DYNAMIC_IO_PORT_BASE
31 select MIPS_INSERT_BOOT_CONFIG
32 select MIPS_L1_CACHE_SHIFT_6
36 select ROM_EXCEPTION_VECTORS
37 select SUPPORTS_BIG_ENDIAN
38 select SUPPORTS_CPU_MIPS32_R1
39 select SUPPORTS_CPU_MIPS32_R2
40 select SUPPORTS_CPU_MIPS32_R6
41 select SUPPORTS_CPU_MIPS64_R1
42 select SUPPORTS_CPU_MIPS64_R2
43 select SUPPORTS_CPU_MIPS64_R6
44 select SUPPORTS_LITTLE_ENDIAN
50 select ROM_EXCEPTION_VECTORS
51 select SUPPORTS_BIG_ENDIAN
52 select SUPPORTS_CPU_MIPS32_R1
53 select SUPPORTS_CPU_MIPS32_R2
54 select SYS_MIPS_CACHE_INIT_RAM_LOAD
57 bool "Support QCA/Atheros ath79"
63 bool "Support MSCC VCore-III"
68 bool "Support BMIPS SoCs"
78 bool "Support MediaTek MIPS platforms"
81 select DISPLAY_CPUINFO
93 select LAST_STAGE_INIT
96 select ROM_EXCEPTION_VECTORS
97 select SUPPORTS_CPU_MIPS32_R1
98 select SUPPORTS_CPU_MIPS32_R2
99 select SUPPORTS_LITTLE_ENDIAN
103 bool "Support Ingenic JZ47xx"
109 bool "Support Microchip PIC32"
115 bool "Support Boston"
119 select MIPS_L1_CACHE_SHIFT_6
121 select OF_BOARD_SETUP
123 select ROM_EXCEPTION_VECTORS
124 select SUPPORTS_BIG_ENDIAN
125 select SUPPORTS_CPU_MIPS32_R1
126 select SUPPORTS_CPU_MIPS32_R2
127 select SUPPORTS_CPU_MIPS32_R6
128 select SUPPORTS_CPU_MIPS64_R1
129 select SUPPORTS_CPU_MIPS64_R2
130 select SUPPORTS_CPU_MIPS64_R6
131 select SUPPORTS_LITTLE_ENDIAN
134 config TARGET_XILFPGA
135 bool "Support Imagination Xilfpga"
140 select MIPS_L1_CACHE_SHIFT_4
142 select ROM_EXCEPTION_VECTORS
143 select SUPPORTS_CPU_MIPS32_R1
144 select SUPPORTS_CPU_MIPS32_R2
145 select SUPPORTS_LITTLE_ENDIAN
148 This supports IMGTEC MIPSfpga platform
152 source "board/imgtec/boston/Kconfig"
153 source "board/imgtec/malta/Kconfig"
154 source "board/imgtec/xilfpga/Kconfig"
155 source "board/micronas/vct/Kconfig"
156 source "board/qemu-mips/Kconfig"
157 source "arch/mips/mach-ath79/Kconfig"
158 source "arch/mips/mach-mscc/Kconfig"
159 source "arch/mips/mach-bmips/Kconfig"
160 source "arch/mips/mach-jz47xx/Kconfig"
161 source "arch/mips/mach-pic32/Kconfig"
162 source "arch/mips/mach-mtmips/Kconfig"
167 prompt "Endianness selection"
169 Some MIPS boards can be configured for either little or big endian
170 byte order. These modes require different U-Boot images. In general there
171 is one preferred byteorder for a particular system but some systems are
172 just as commonly used in the one or the other endianness.
174 config SYS_BIG_ENDIAN
176 depends on SUPPORTS_BIG_ENDIAN
178 config SYS_LITTLE_ENDIAN
180 depends on SUPPORTS_LITTLE_ENDIAN
185 prompt "CPU selection"
186 default CPU_MIPS32_R2
189 bool "MIPS32 Release 1"
190 depends on SUPPORTS_CPU_MIPS32_R1
193 Choose this option to build an U-Boot for release 1 through 5 of the
197 bool "MIPS32 Release 2"
198 depends on SUPPORTS_CPU_MIPS32_R2
201 Choose this option to build an U-Boot for release 2 through 5 of the
205 bool "MIPS32 Release 6"
206 depends on SUPPORTS_CPU_MIPS32_R6
209 Choose this option to build an U-Boot for release 6 or later of the
213 bool "MIPS64 Release 1"
214 depends on SUPPORTS_CPU_MIPS64_R1
217 Choose this option to build a kernel for release 1 through 5 of the
221 bool "MIPS64 Release 2"
222 depends on SUPPORTS_CPU_MIPS64_R2
225 Choose this option to build a kernel for release 2 through 5 of the
229 bool "MIPS64 Release 6"
230 depends on SUPPORTS_CPU_MIPS64_R6
233 Choose this option to build a kernel for release 6 or later of the
240 config ROM_EXCEPTION_VECTORS
241 bool "Build U-Boot image with exception vectors"
243 Enable this to include exception vectors in the U-Boot image. This is
244 required if the U-Boot entry point is equal to the address of the
245 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
246 U-Boot booted from parallel NOR flash).
247 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
248 In that case the image size will be reduced by 0x500 bytes.
251 hex "MIPS CM GCR Base Address"
253 default 0x16100000 if TARGET_BOSTON
256 The physical base address at which to map the MIPS Coherence Manager
257 Global Configuration Registers (GCRs). This should be set such that
258 the GCRs occupy a region of the physical address space which is
259 otherwise unused, or at minimum that software doesn't need to access.
261 config MIPS_CACHE_INDEX_BASE
262 hex "Index base address for cache initialisation"
263 default 0x80000000 if CPU_MIPS32
264 default 0xffffffff80000000 if CPU_MIPS64
266 This is the base address for a memory block, which is used for
267 initialising the cache lines. This is also the base address of a memory
268 block which is used for loading and filling cache lines when
269 SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
270 Normally this is CKSEG0. If the MIPS system needs to move this block
271 to some SRAM or ScratchPad RAM, adapt this option accordingly.
273 config MIPS_RELOCATION_TABLE_SIZE
274 hex "Relocation table size"
278 A table of relocation data will be appended to the U-Boot binary
279 and parsed in relocate_code() to fix up all offsets in the relocated
282 This option allows the amount of space reserved for the table to be
283 adjusted in a range from 256 up to 64k. The default is 32k and should
284 be ok in most cases. Reduce this value to shrink the size of U-Boot
287 The build will fail and a valid size suggested if this is too small.
289 If unsure, leave at the default value.
293 menu "OS boot interface"
295 config MIPS_BOOT_CMDLINE_LEGACY
296 bool "Hand over legacy command line to Linux kernel"
299 Enable this option if you want U-Boot to hand over the Yamon-style
300 command line to the kernel. All bootargs will be prepared as argc/argv
301 compatible list. The argument count (argc) is stored in register $a0.
302 The address of the argument list (argv) is stored in register $a1.
304 config MIPS_BOOT_ENV_LEGACY
305 bool "Hand over legacy environment to Linux kernel"
308 Enable this option if you want U-Boot to hand over the Yamon-style
309 environment to the kernel. Information like memory size, initrd
310 address and size will be prepared as zero-terminated key/value list.
311 The address of the environment is stored in register $a2.
314 bool "Hand over a flattened device tree to Linux kernel"
317 Enable this option if you want U-Boot to hand over a flattened
318 device tree to the kernel. According to UHI register $a0 will be set
319 to -2 and the FDT address is stored in $a1.
323 config SUPPORTS_BIG_ENDIAN
326 config SUPPORTS_LITTLE_ENDIAN
329 config SUPPORTS_CPU_MIPS32_R1
332 config SUPPORTS_CPU_MIPS32_R2
335 config SUPPORTS_CPU_MIPS32_R6
338 config SUPPORTS_CPU_MIPS64_R1
341 config SUPPORTS_CPU_MIPS64_R2
344 config SUPPORTS_CPU_MIPS64_R6
349 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
353 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
358 config MIPS_TUNE_14KC
361 config MIPS_TUNE_24KC
364 config MIPS_TUNE_34KC
367 config MIPS_TUNE_74KC
379 config SYS_MIPS_CACHE_INIT_RAM_LOAD
382 config MIPS_INIT_STACK_IN_SRAM
386 Select this if the initial stack frame could be setup in SRAM.
387 Normally the initial stack frame is set up in DRAM which is often
388 only available after lowlevel_init. With this option the initial
389 stack frame and the early C environment is set up before
390 lowlevel_init. Thus lowlevel_init does not need to be implemented
393 config SYS_DCACHE_SIZE
397 The total size of the L1 Dcache, if known at compile time.
399 config SYS_DCACHE_LINE_SIZE
403 The size of L1 Dcache lines, if known at compile time.
405 config SYS_ICACHE_SIZE
409 The total size of the L1 ICache, if known at compile time.
411 config SYS_ICACHE_LINE_SIZE
415 The size of L1 Icache lines, if known at compile time.
417 config SYS_SCACHE_LINE_SIZE
421 The size of L2 cache lines, if known at compile time.
424 config SYS_CACHE_SIZE_AUTO
425 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
426 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \
427 SYS_SCACHE_LINE_SIZE = 0
429 Select this (or let it be auto-selected by not defining any cache
430 sizes) in order to allow U-Boot to automatically detect the sizes
431 of caches at runtime. This has a small cost in code size & runtime
432 so if you know the cache configuration for your system at compile
433 time it would be beneficial to configure it.
435 config MIPS_L1_CACHE_SHIFT_4
438 config MIPS_L1_CACHE_SHIFT_5
441 config MIPS_L1_CACHE_SHIFT_6
444 config MIPS_L1_CACHE_SHIFT_7
447 config MIPS_L1_CACHE_SHIFT
449 default "7" if MIPS_L1_CACHE_SHIFT_7
450 default "6" if MIPS_L1_CACHE_SHIFT_6
451 default "5" if MIPS_L1_CACHE_SHIFT_5
452 default "4" if MIPS_L1_CACHE_SHIFT_4
458 Select this if your system includes an L2 cache and you want U-Boot
459 to initialise & maintain it.
461 config DYNAMIC_IO_PORT_BASE
467 Select this if your system contains a MIPS Coherence Manager and you
468 wish U-Boot to configure it or make use of it to retrieve system
469 information such as cache configuration.
471 config MIPS_INSERT_BOOT_CONFIG
475 Enable this to insert some board-specific boot configuration in
476 the U-Boot binary at offset 0x10.
478 config MIPS_BOOT_CONFIG_WORD0
480 depends on MIPS_INSERT_BOOT_CONFIG
481 default 0x420 if TARGET_MALTA
484 Value which is inserted as boot config word 0.
486 config MIPS_BOOT_CONFIG_WORD1
488 depends on MIPS_INSERT_BOOT_CONFIG
491 Value which is inserted as boot config word 1.