1 menu "MIPS architecture"
8 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
12 prompt "Target select"
15 config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
17 select ROM_EXCEPTION_VECTORS
18 select SUPPORTS_BIG_ENDIAN
19 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
21 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
23 select SUPPORTS_LITTLE_ENDIAN
29 select DYNAMIC_IO_PORT_BASE
31 select MIPS_L1_CACHE_SHIFT_6
35 select ROM_EXCEPTION_VECTORS
36 select SUPPORTS_BIG_ENDIAN
37 select SUPPORTS_CPU_MIPS32_R1
38 select SUPPORTS_CPU_MIPS32_R2
39 select SUPPORTS_CPU_MIPS32_R6
40 select SUPPORTS_CPU_MIPS64_R1
41 select SUPPORTS_CPU_MIPS64_R2
42 select SUPPORTS_CPU_MIPS64_R6
43 select SUPPORTS_LITTLE_ENDIAN
49 select ROM_EXCEPTION_VECTORS
50 select SUPPORTS_BIG_ENDIAN
51 select SUPPORTS_CPU_MIPS32_R1
52 select SUPPORTS_CPU_MIPS32_R2
53 select SYS_MIPS_CACHE_INIT_RAM_LOAD
55 config TARGET_DBAU1X00
56 bool "Support dbau1x00"
58 select ROM_EXCEPTION_VECTORS
59 select SUPPORTS_BIG_ENDIAN
60 select SUPPORTS_CPU_MIPS32_R1
61 select SUPPORTS_CPU_MIPS32_R2
62 select SUPPORTS_LITTLE_ENDIAN
63 select SYS_MIPS_CACHE_INIT_RAM_LOAD
68 select ROM_EXCEPTION_VECTORS
69 select SUPPORTS_CPU_MIPS32_R1
70 select SUPPORTS_CPU_MIPS32_R2
71 select SUPPORTS_LITTLE_ENDIAN
72 select SYS_MIPS_CACHE_INIT_RAM_LOAD
75 bool "Support QCA/Atheros ath79"
81 bool "Support BMIPS SoCs"
91 bool "Support Microchip PIC32"
101 select MIPS_L1_CACHE_SHIFT_6
103 select OF_BOARD_SETUP
105 select ROM_EXCEPTION_VECTORS
106 select SUPPORTS_BIG_ENDIAN
107 select SUPPORTS_CPU_MIPS32_R1
108 select SUPPORTS_CPU_MIPS32_R2
109 select SUPPORTS_CPU_MIPS32_R6
110 select SUPPORTS_CPU_MIPS64_R1
111 select SUPPORTS_CPU_MIPS64_R2
112 select SUPPORTS_CPU_MIPS64_R6
113 select SUPPORTS_LITTLE_ENDIAN
116 config TARGET_XILFPGA
117 bool "Support Imagination Xilfpga"
122 select MIPS_L1_CACHE_SHIFT_4
124 select ROM_EXCEPTION_VECTORS
125 select SUPPORTS_CPU_MIPS32_R1
126 select SUPPORTS_CPU_MIPS32_R2
127 select SUPPORTS_LITTLE_ENDIAN
130 This supports IMGTEC MIPSfpga platform
134 source "board/dbau1x00/Kconfig"
135 source "board/imgtec/boston/Kconfig"
136 source "board/imgtec/malta/Kconfig"
137 source "board/imgtec/xilfpga/Kconfig"
138 source "board/micronas/vct/Kconfig"
139 source "board/pb1x00/Kconfig"
140 source "board/qemu-mips/Kconfig"
141 source "arch/mips/mach-ath79/Kconfig"
142 source "arch/mips/mach-bmips/Kconfig"
143 source "arch/mips/mach-pic32/Kconfig"
148 prompt "Endianness selection"
150 Some MIPS boards can be configured for either little or big endian
151 byte order. These modes require different U-Boot images. In general there
152 is one preferred byteorder for a particular system but some systems are
153 just as commonly used in the one or the other endianness.
155 config SYS_BIG_ENDIAN
157 depends on SUPPORTS_BIG_ENDIAN
159 config SYS_LITTLE_ENDIAN
161 depends on SUPPORTS_LITTLE_ENDIAN
166 prompt "CPU selection"
167 default CPU_MIPS32_R2
170 bool "MIPS32 Release 1"
171 depends on SUPPORTS_CPU_MIPS32_R1
174 Choose this option to build an U-Boot for release 1 through 5 of the
178 bool "MIPS32 Release 2"
179 depends on SUPPORTS_CPU_MIPS32_R2
182 Choose this option to build an U-Boot for release 2 through 5 of the
186 bool "MIPS32 Release 6"
187 depends on SUPPORTS_CPU_MIPS32_R6
190 Choose this option to build an U-Boot for release 6 or later of the
194 bool "MIPS64 Release 1"
195 depends on SUPPORTS_CPU_MIPS64_R1
198 Choose this option to build a kernel for release 1 through 5 of the
202 bool "MIPS64 Release 2"
203 depends on SUPPORTS_CPU_MIPS64_R2
206 Choose this option to build a kernel for release 2 through 5 of the
210 bool "MIPS64 Release 6"
211 depends on SUPPORTS_CPU_MIPS64_R6
214 Choose this option to build a kernel for release 6 or later of the
221 config ROM_EXCEPTION_VECTORS
222 bool "Build U-Boot image with exception vectors"
224 Enable this to include exception vectors in the U-Boot image. This is
225 required if the U-Boot entry point is equal to the address of the
226 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
227 U-Boot booted from parallel NOR flash).
228 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
229 In that case the image size will be reduced by 0x500 bytes.
232 hex "MIPS CM GCR Base Address"
234 default 0x16100000 if TARGET_BOSTON
237 The physical base address at which to map the MIPS Coherence Manager
238 Global Configuration Registers (GCRs). This should be set such that
239 the GCRs occupy a region of the physical address space which is
240 otherwise unused, or at minimum that software doesn't need to access.
244 menu "OS boot interface"
246 config MIPS_BOOT_CMDLINE_LEGACY
247 bool "Hand over legacy command line to Linux kernel"
250 Enable this option if you want U-Boot to hand over the Yamon-style
251 command line to the kernel. All bootargs will be prepared as argc/argv
252 compatible list. The argument count (argc) is stored in register $a0.
253 The address of the argument list (argv) is stored in register $a1.
255 config MIPS_BOOT_ENV_LEGACY
256 bool "Hand over legacy environment to Linux kernel"
259 Enable this option if you want U-Boot to hand over the Yamon-style
260 environment to the kernel. Information like memory size, initrd
261 address and size will be prepared as zero-terminated key/value list.
262 The address of the environment is stored in register $a2.
265 bool "Hand over a flattened device tree to Linux kernel"
268 Enable this option if you want U-Boot to hand over a flattened
269 device tree to the kernel. According to UHI register $a0 will be set
270 to -2 and the FDT address is stored in $a1.
274 config SUPPORTS_BIG_ENDIAN
277 config SUPPORTS_LITTLE_ENDIAN
280 config SUPPORTS_CPU_MIPS32_R1
283 config SUPPORTS_CPU_MIPS32_R2
286 config SUPPORTS_CPU_MIPS32_R6
289 config SUPPORTS_CPU_MIPS64_R1
292 config SUPPORTS_CPU_MIPS64_R2
295 config SUPPORTS_CPU_MIPS64_R6
300 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
304 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
309 config MIPS_TUNE_14KC
312 config MIPS_TUNE_24KC
315 config MIPS_TUNE_34KC
318 config MIPS_TUNE_74KC
330 config SYS_MIPS_CACHE_INIT_RAM_LOAD
333 config MIPS_INIT_STACK_IN_SRAM
337 Select this if the initial stack frame could be setup in SRAM.
338 Normally the initial stack frame is set up in DRAM which is often
339 only available after lowlevel_init. With this option the initial
340 stack frame and the early C environment is set up before
341 lowlevel_init. Thus lowlevel_init does not need to be implemented
344 config SYS_DCACHE_SIZE
348 The total size of the L1 Dcache, if known at compile time.
350 config SYS_DCACHE_LINE_SIZE
354 The size of L1 Dcache lines, if known at compile time.
356 config SYS_ICACHE_SIZE
360 The total size of the L1 ICache, if known at compile time.
362 config SYS_ICACHE_LINE_SIZE
366 The size of L1 Icache lines, if known at compile time.
368 config SYS_CACHE_SIZE_AUTO
369 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
370 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
372 Select this (or let it be auto-selected by not defining any cache
373 sizes) in order to allow U-Boot to automatically detect the sizes
374 of caches at runtime. This has a small cost in code size & runtime
375 so if you know the cache configuration for your system at compile
376 time it would be beneficial to configure it.
378 config MIPS_L1_CACHE_SHIFT_4
381 config MIPS_L1_CACHE_SHIFT_5
384 config MIPS_L1_CACHE_SHIFT_6
387 config MIPS_L1_CACHE_SHIFT_7
390 config MIPS_L1_CACHE_SHIFT
392 default "7" if MIPS_L1_CACHE_SHIFT_7
393 default "6" if MIPS_L1_CACHE_SHIFT_6
394 default "5" if MIPS_L1_CACHE_SHIFT_5
395 default "4" if MIPS_L1_CACHE_SHIFT_4
401 Select this if your system includes an L2 cache and you want U-Boot
402 to initialise & maintain it.
404 config DYNAMIC_IO_PORT_BASE
410 Select this if your system contains a MIPS Coherence Manager and you
411 wish U-Boot to configure it or make use of it to retrieve system
412 information such as cache configuration.