1 menu "MIPS architecture"
8 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
12 prompt "Target select"
19 select DYNAMIC_IO_PORT_BASE
21 select MIPS_INSERT_BOOT_CONFIG
22 select MIPS_L1_CACHE_SHIFT_6
26 select ROM_EXCEPTION_VECTORS
27 select SUPPORTS_BIG_ENDIAN
28 select SUPPORTS_CPU_MIPS32_R1
29 select SUPPORTS_CPU_MIPS32_R2
30 select SUPPORTS_CPU_MIPS32_R6
31 select SUPPORTS_CPU_MIPS64_R1
32 select SUPPORTS_CPU_MIPS64_R2
33 select SUPPORTS_CPU_MIPS64_R6
34 select SUPPORTS_LITTLE_ENDIAN
40 select ROM_EXCEPTION_VECTORS
41 select SUPPORTS_BIG_ENDIAN
42 select SUPPORTS_CPU_MIPS32_R1
43 select SUPPORTS_CPU_MIPS32_R2
44 select SYS_MIPS_CACHE_INIT_RAM_LOAD
47 bool "Support QCA/Atheros ath79"
53 bool "Support MSCC VCore-III"
58 bool "Support BMIPS SoCs"
68 bool "Support MediaTek MIPS platforms"
71 select DISPLAY_CPUINFO
83 select LAST_STAGE_INIT
86 select ROM_EXCEPTION_VECTORS
87 select SUPPORTS_CPU_MIPS32_R1
88 select SUPPORTS_CPU_MIPS32_R2
89 select SUPPORTS_LITTLE_ENDIAN
93 bool "Support Ingenic JZ47xx"
99 bool "Support Marvell Octeon CN7xxx platforms"
100 select CPU_CAVIUM_OCTEON
101 select DISPLAY_CPUINFO
102 select DMA_ADDR_T_64BIT
110 select MIPS_MACH_EARLY_INIT
111 select MIPS_TUNE_OCTEON3
112 select ROM_EXCEPTION_VECTORS
113 select SUPPORTS_BIG_ENDIAN
114 select SUPPORTS_CPU_MIPS64_OCTEON
121 bool "Support Microchip PIC32"
127 bool "Support Boston"
131 select MIPS_L1_CACHE_SHIFT_6
133 select OF_BOARD_SETUP
135 select ROM_EXCEPTION_VECTORS
136 select SUPPORTS_BIG_ENDIAN
137 select SUPPORTS_CPU_MIPS32_R1
138 select SUPPORTS_CPU_MIPS32_R2
139 select SUPPORTS_CPU_MIPS32_R6
140 select SUPPORTS_CPU_MIPS64_R1
141 select SUPPORTS_CPU_MIPS64_R2
142 select SUPPORTS_CPU_MIPS64_R6
143 select SUPPORTS_LITTLE_ENDIAN
146 config TARGET_XILFPGA
147 bool "Support Imagination Xilfpga"
152 select MIPS_L1_CACHE_SHIFT_4
154 select ROM_EXCEPTION_VECTORS
155 select SUPPORTS_CPU_MIPS32_R1
156 select SUPPORTS_CPU_MIPS32_R2
157 select SUPPORTS_LITTLE_ENDIAN
160 This supports IMGTEC MIPSfpga platform
164 source "board/imgtec/boston/Kconfig"
165 source "board/imgtec/malta/Kconfig"
166 source "board/imgtec/xilfpga/Kconfig"
167 source "arch/mips/mach-ath79/Kconfig"
168 source "arch/mips/mach-mscc/Kconfig"
169 source "arch/mips/mach-bmips/Kconfig"
170 source "arch/mips/mach-jz47xx/Kconfig"
171 source "arch/mips/mach-pic32/Kconfig"
172 source "arch/mips/mach-mtmips/Kconfig"
173 source "arch/mips/mach-octeon/Kconfig"
178 prompt "Endianness selection"
180 Some MIPS boards can be configured for either little or big endian
181 byte order. These modes require different U-Boot images. In general there
182 is one preferred byteorder for a particular system but some systems are
183 just as commonly used in the one or the other endianness.
185 config SYS_BIG_ENDIAN
187 depends on SUPPORTS_BIG_ENDIAN
189 config SYS_LITTLE_ENDIAN
191 depends on SUPPORTS_LITTLE_ENDIAN
196 prompt "CPU selection"
197 default CPU_MIPS32_R2
200 bool "MIPS32 Release 1"
201 depends on SUPPORTS_CPU_MIPS32_R1
204 Choose this option to build an U-Boot for release 1 through 5 of the
208 bool "MIPS32 Release 2"
209 depends on SUPPORTS_CPU_MIPS32_R2
212 Choose this option to build an U-Boot for release 2 through 5 of the
216 bool "MIPS32 Release 6"
217 depends on SUPPORTS_CPU_MIPS32_R6
220 Choose this option to build an U-Boot for release 6 or later of the
224 bool "MIPS64 Release 1"
225 depends on SUPPORTS_CPU_MIPS64_R1
228 Choose this option to build a kernel for release 1 through 5 of the
232 bool "MIPS64 Release 2"
233 depends on SUPPORTS_CPU_MIPS64_R2
236 Choose this option to build a kernel for release 2 through 5 of the
240 bool "MIPS64 Release 6"
241 depends on SUPPORTS_CPU_MIPS64_R6
244 Choose this option to build a kernel for release 6 or later of the
247 config CPU_MIPS64_OCTEON
248 bool "Marvell Octeon series of CPUs"
249 depends on SUPPORTS_CPU_MIPS64_OCTEON
252 Choose this option for Marvell Octeon CPUs. These CPUs are between
253 MIPS64 R5 and R6 with other extensions.
259 config ROM_EXCEPTION_VECTORS
260 bool "Build U-Boot image with exception vectors"
262 Enable this to include exception vectors in the U-Boot image. This is
263 required if the U-Boot entry point is equal to the address of the
264 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
265 U-Boot booted from parallel NOR flash).
266 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
267 In that case the image size will be reduced by 0x500 bytes.
270 hex "MIPS CM GCR Base Address"
272 default 0x16100000 if TARGET_BOSTON
275 The physical base address at which to map the MIPS Coherence Manager
276 Global Configuration Registers (GCRs). This should be set such that
277 the GCRs occupy a region of the physical address space which is
278 otherwise unused, or at minimum that software doesn't need to access.
280 config MIPS_CACHE_INDEX_BASE
281 hex "Index base address for cache initialisation"
282 default 0x80000000 if CPU_MIPS32
283 default 0xffffffff80000000 if CPU_MIPS64
285 This is the base address for a memory block, which is used for
286 initialising the cache lines. This is also the base address of a memory
287 block which is used for loading and filling cache lines when
288 SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
289 Normally this is CKSEG0. If the MIPS system needs to move this block
290 to some SRAM or ScratchPad RAM, adapt this option accordingly.
292 config MIPS_MACH_EARLY_INIT
293 bool "Enable mach specific very early init code"
295 Use this to enable the call to mips_mach_early_init() very early
296 from start.S. This function can be used e.g. to do some very early
297 CPU / SoC intitialization or image copying. Its called very early
298 and at this stage the PC might not match the linking address
299 (CONFIG_TEXT_BASE) - no absolute jump done until this call.
301 config MIPS_CACHE_SETUP
302 bool "Allow generic start code to initialize and setup caches"
303 default n if SKIP_LOWLEVEL_INIT
306 This allows the generic start code to invoke the generic initialization
307 of the CPU caches. Disabling this can be useful for RAM boot scenarios
308 (EJTAG, SPL payload) or for machines which don't need cache initialization
309 or which want to provide their own cache implementation.
313 config MIPS_CACHE_DISABLE
314 bool "Allow generic start code to initially disable caches"
315 default n if SKIP_LOWLEVEL_INIT
318 This allows the generic start code to initially disable the CPU caches
319 and run uncached until the caches are initialized and enabled. Disabling
320 this can be useful on machines which don't need cache initialization or
321 which want to provide their own cache implementation.
325 config MIPS_RELOCATION_TABLE_SIZE
326 hex "Relocation table size"
330 A table of relocation data will be appended to the U-Boot binary
331 and parsed in relocate_code() to fix up all offsets in the relocated
334 This option allows the amount of space reserved for the table to be
335 adjusted in a range from 256 up to 64k. The default is 32k and should
336 be ok in most cases. Reduce this value to shrink the size of U-Boot
339 The build will fail and a valid size suggested if this is too small.
341 If unsure, leave at the default value.
343 config RESTORE_EXCEPTION_VECTOR_BASE
344 bool "Restore exception vector base before booting linux kernel"
347 In U-Boot the exception vector base will be moved to top of memory,
348 to be used to display register dump when exception occurs.
349 But some old linux kernel does not honor the base set in CP0_EBASE.
350 A modified exception vector base will cause kernel crash.
352 This option will restore the exception vector base to its previous
357 config OVERRIDE_EXCEPTION_VECTOR_BASE
358 bool "Override the exception vector base to be restored"
359 depends on RESTORE_EXCEPTION_VECTOR_BASE
362 Enable this option if you want to use a different exception vector
363 base rather than the previously saved one.
365 config NEW_EXCEPTION_VECTOR_BASE
366 hex "New exception vector base"
367 depends on OVERRIDE_EXCEPTION_VECTOR_BASE
368 range 0x80000000 0xbffff000
371 The exception vector base to be restored before booting linux kernel
373 config INIT_STACK_WITHOUT_MALLOC_F
374 bool "Do not reserve malloc space on initial stack"
377 Enable this option if you don't want to reserve malloc space on
378 initial stack. This is useful if the initial stack can't hold large
379 malloc space. Platform should set the malloc_base later when DRAM is
382 config SPL_INIT_STACK_WITHOUT_MALLOC_F
383 bool "Do not reserve malloc space on initial stack in SPL"
386 Enable this option if you don't want to reserve malloc space on
387 initial stack. This is useful if the initial stack can't hold large
388 malloc space. Platform should set the malloc_base later when DRAM is
391 config SPL_LOADER_SUPPORT
395 Enable this option if you want to use SPL loaders without DM enabled.
399 menu "OS boot interface"
401 config MIPS_BOOT_CMDLINE_LEGACY
402 bool "Hand over legacy command line to Linux kernel"
405 Enable this option if you want U-Boot to hand over the Yamon-style
406 command line to the kernel. All bootargs will be prepared as argc/argv
407 compatible list. The argument count (argc) is stored in register $a0.
408 The address of the argument list (argv) is stored in register $a1.
410 config MIPS_BOOT_ENV_LEGACY
411 bool "Hand over legacy environment to Linux kernel"
414 Enable this option if you want U-Boot to hand over the Yamon-style
415 environment to the kernel. Information like memory size, initrd
416 address and size will be prepared as zero-terminated key/value list.
417 The address of the environment is stored in register $a2.
420 bool "Hand over a flattened device tree to Linux kernel"
423 Enable this option if you want U-Boot to hand over a flattened
424 device tree to the kernel. According to UHI register $a0 will be set
425 to -2 and the FDT address is stored in $a1.
429 config SUPPORTS_BIG_ENDIAN
432 config SUPPORTS_LITTLE_ENDIAN
435 config SUPPORTS_CPU_MIPS32_R1
438 config SUPPORTS_CPU_MIPS32_R2
441 config SUPPORTS_CPU_MIPS32_R6
444 config SUPPORTS_CPU_MIPS64_R1
447 config SUPPORTS_CPU_MIPS64_R2
450 config SUPPORTS_CPU_MIPS64_R6
453 config SUPPORTS_CPU_MIPS64_OCTEON
456 config CPU_CAVIUM_OCTEON
461 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
465 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
466 default y if CPU_MIPS64_OCTEON
471 config MIPS_TUNE_14KC
474 config MIPS_TUNE_24KC
477 config MIPS_TUNE_34KC
480 config MIPS_TUNE_74KC
483 config MIPS_TUNE_OCTEON3
495 config SYS_MIPS_CACHE_INIT_RAM_LOAD
498 config MIPS_INIT_STACK_IN_SRAM
502 Select this if the initial stack frame could be setup in SRAM.
503 Normally the initial stack frame is set up in DRAM which is often
504 only available after lowlevel_init. With this option the initial
505 stack frame and the early C environment is set up before
506 lowlevel_init. Thus lowlevel_init does not need to be implemented
509 config MIPS_SRAM_INIT
512 depends on MIPS_INIT_STACK_IN_SRAM
514 Select this if the SRAM for initial stack needs to be initialized
515 before it can be used. If enabled, a function mips_sram_init() will
516 be called just before setup_stack_gd.
518 config DMA_ADDR_T_64BIT
521 Select this to enable 64-bit DMA addressing
523 config SYS_DCACHE_SIZE
527 The total size of the L1 Dcache, if known at compile time.
529 config SYS_DCACHE_LINE_SIZE
533 The size of L1 Dcache lines, if known at compile time.
535 config SYS_ICACHE_SIZE
539 The total size of the L1 ICache, if known at compile time.
541 config SYS_ICACHE_LINE_SIZE
545 The size of L1 Icache lines, if known at compile time.
547 config SYS_SCACHE_LINE_SIZE
551 The size of L2 cache lines, if known at compile time.
554 config SYS_CACHE_SIZE_AUTO
555 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
556 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \
557 SYS_SCACHE_LINE_SIZE = 0
559 Select this (or let it be auto-selected by not defining any cache
560 sizes) in order to allow U-Boot to automatically detect the sizes
561 of caches at runtime. This has a small cost in code size & runtime
562 so if you know the cache configuration for your system at compile
563 time it would be beneficial to configure it.
565 config MIPS_L1_CACHE_SHIFT_4
568 config MIPS_L1_CACHE_SHIFT_5
571 config MIPS_L1_CACHE_SHIFT_6
574 config MIPS_L1_CACHE_SHIFT_7
577 config MIPS_L1_CACHE_SHIFT
579 default "7" if MIPS_L1_CACHE_SHIFT_7
580 default "6" if MIPS_L1_CACHE_SHIFT_6
581 default "5" if MIPS_L1_CACHE_SHIFT_5
582 default "4" if MIPS_L1_CACHE_SHIFT_4
588 Select this if your system includes an L2 cache and you want U-Boot
589 to initialise & maintain it.
591 config DYNAMIC_IO_PORT_BASE
597 Select this if your system contains a MIPS Coherence Manager and you
598 wish U-Boot to configure it or make use of it to retrieve system
599 information such as cache configuration.
601 config MIPS_INSERT_BOOT_CONFIG
605 Enable this to insert some board-specific boot configuration in
606 the U-Boot binary at offset 0x10.
608 config MIPS_BOOT_CONFIG_WORD0
610 depends on MIPS_INSERT_BOOT_CONFIG
611 default 0x420 if TARGET_MALTA
614 Value which is inserted as boot config word 0.
616 config MIPS_BOOT_CONFIG_WORD1
618 depends on MIPS_INSERT_BOOT_CONFIG
621 Value which is inserted as boot config word 1.