1 menu "MIPS architecture"
8 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
12 prompt "Target select"
15 config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
17 select ROM_EXCEPTION_VECTORS
18 select SUPPORTS_BIG_ENDIAN
19 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
21 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
23 select SUPPORTS_LITTLE_ENDIAN
29 select DYNAMIC_IO_PORT_BASE
31 select MIPS_INSERT_BOOT_CONFIG
32 select MIPS_L1_CACHE_SHIFT_6
36 select ROM_EXCEPTION_VECTORS
37 select SUPPORTS_BIG_ENDIAN
38 select SUPPORTS_CPU_MIPS32_R1
39 select SUPPORTS_CPU_MIPS32_R2
40 select SUPPORTS_CPU_MIPS32_R6
41 select SUPPORTS_CPU_MIPS64_R1
42 select SUPPORTS_CPU_MIPS64_R2
43 select SUPPORTS_CPU_MIPS64_R6
44 select SUPPORTS_LITTLE_ENDIAN
50 select ROM_EXCEPTION_VECTORS
51 select SUPPORTS_BIG_ENDIAN
52 select SUPPORTS_CPU_MIPS32_R1
53 select SUPPORTS_CPU_MIPS32_R2
54 select SYS_MIPS_CACHE_INIT_RAM_LOAD
57 bool "Support QCA/Atheros ath79"
63 bool "Support MSCC VCore-III"
68 bool "Support BMIPS SoCs"
78 bool "Support MediaTek MIPS platforms"
81 select DISPLAY_CPUINFO
93 select LAST_STAGE_INIT
96 select ROM_EXCEPTION_VECTORS
97 select SUPPORTS_CPU_MIPS32_R1
98 select SUPPORTS_CPU_MIPS32_R2
99 select SUPPORTS_LITTLE_ENDIAN
104 bool "Support Ingenic JZ47xx"
110 bool "Support Marvell Octeon CN7xxx platforms"
111 select CPU_CAVIUM_OCTEON
112 select DISPLAY_CPUINFO
113 select DMA_ADDR_T_64BIT
121 select MIPS_MACH_EARLY_INIT
122 select MIPS_TUNE_OCTEON3
123 select ROM_EXCEPTION_VECTORS
124 select SUPPORTS_BIG_ENDIAN
125 select SUPPORTS_CPU_MIPS64_OCTEON
132 bool "Support Microchip PIC32"
138 bool "Support Boston"
142 select MIPS_L1_CACHE_SHIFT_6
144 select OF_BOARD_SETUP
146 select ROM_EXCEPTION_VECTORS
147 select SUPPORTS_BIG_ENDIAN
148 select SUPPORTS_CPU_MIPS32_R1
149 select SUPPORTS_CPU_MIPS32_R2
150 select SUPPORTS_CPU_MIPS32_R6
151 select SUPPORTS_CPU_MIPS64_R1
152 select SUPPORTS_CPU_MIPS64_R2
153 select SUPPORTS_CPU_MIPS64_R6
154 select SUPPORTS_LITTLE_ENDIAN
157 config TARGET_XILFPGA
158 bool "Support Imagination Xilfpga"
163 select MIPS_L1_CACHE_SHIFT_4
165 select ROM_EXCEPTION_VECTORS
166 select SUPPORTS_CPU_MIPS32_R1
167 select SUPPORTS_CPU_MIPS32_R2
168 select SUPPORTS_LITTLE_ENDIAN
171 This supports IMGTEC MIPSfpga platform
175 source "board/imgtec/boston/Kconfig"
176 source "board/imgtec/malta/Kconfig"
177 source "board/imgtec/xilfpga/Kconfig"
178 source "board/qemu-mips/Kconfig"
179 source "arch/mips/mach-ath79/Kconfig"
180 source "arch/mips/mach-mscc/Kconfig"
181 source "arch/mips/mach-bmips/Kconfig"
182 source "arch/mips/mach-jz47xx/Kconfig"
183 source "arch/mips/mach-pic32/Kconfig"
184 source "arch/mips/mach-mtmips/Kconfig"
185 source "arch/mips/mach-octeon/Kconfig"
190 prompt "Endianness selection"
192 Some MIPS boards can be configured for either little or big endian
193 byte order. These modes require different U-Boot images. In general there
194 is one preferred byteorder for a particular system but some systems are
195 just as commonly used in the one or the other endianness.
197 config SYS_BIG_ENDIAN
199 depends on SUPPORTS_BIG_ENDIAN
201 config SYS_LITTLE_ENDIAN
203 depends on SUPPORTS_LITTLE_ENDIAN
208 prompt "CPU selection"
209 default CPU_MIPS32_R2
212 bool "MIPS32 Release 1"
213 depends on SUPPORTS_CPU_MIPS32_R1
216 Choose this option to build an U-Boot for release 1 through 5 of the
220 bool "MIPS32 Release 2"
221 depends on SUPPORTS_CPU_MIPS32_R2
224 Choose this option to build an U-Boot for release 2 through 5 of the
228 bool "MIPS32 Release 6"
229 depends on SUPPORTS_CPU_MIPS32_R6
232 Choose this option to build an U-Boot for release 6 or later of the
236 bool "MIPS64 Release 1"
237 depends on SUPPORTS_CPU_MIPS64_R1
240 Choose this option to build a kernel for release 1 through 5 of the
244 bool "MIPS64 Release 2"
245 depends on SUPPORTS_CPU_MIPS64_R2
248 Choose this option to build a kernel for release 2 through 5 of the
252 bool "MIPS64 Release 6"
253 depends on SUPPORTS_CPU_MIPS64_R6
256 Choose this option to build a kernel for release 6 or later of the
259 config CPU_MIPS64_OCTEON
260 bool "Marvell Octeon series of CPUs"
261 depends on SUPPORTS_CPU_MIPS64_OCTEON
264 Choose this option for Marvell Octeon CPUs. These CPUs are between
265 MIPS64 R5 and R6 with other extensions.
271 config ROM_EXCEPTION_VECTORS
272 bool "Build U-Boot image with exception vectors"
274 Enable this to include exception vectors in the U-Boot image. This is
275 required if the U-Boot entry point is equal to the address of the
276 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
277 U-Boot booted from parallel NOR flash).
278 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
279 In that case the image size will be reduced by 0x500 bytes.
282 hex "MIPS CM GCR Base Address"
284 default 0x16100000 if TARGET_BOSTON
287 The physical base address at which to map the MIPS Coherence Manager
288 Global Configuration Registers (GCRs). This should be set such that
289 the GCRs occupy a region of the physical address space which is
290 otherwise unused, or at minimum that software doesn't need to access.
292 config MIPS_CACHE_INDEX_BASE
293 hex "Index base address for cache initialisation"
294 default 0x80000000 if CPU_MIPS32
295 default 0xffffffff80000000 if CPU_MIPS64
297 This is the base address for a memory block, which is used for
298 initialising the cache lines. This is also the base address of a memory
299 block which is used for loading and filling cache lines when
300 SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
301 Normally this is CKSEG0. If the MIPS system needs to move this block
302 to some SRAM or ScratchPad RAM, adapt this option accordingly.
304 config MIPS_MACH_EARLY_INIT
305 bool "Enable mach specific very early init code"
307 Use this to enable the call to mips_mach_early_init() very early
308 from start.S. This function can be used e.g. to do some very early
309 CPU / SoC intitialization or image copying. Its called very early
310 and at this stage the PC might not match the linking address
311 (CONFIG_TEXT_BASE) - no absolute jump done until this call.
313 config MIPS_CACHE_SETUP
314 bool "Allow generic start code to initialize and setup caches"
315 default n if SKIP_LOWLEVEL_INIT
318 This allows the generic start code to invoke the generic initialization
319 of the CPU caches. Disabling this can be useful for RAM boot scenarios
320 (EJTAG, SPL payload) or for machines which don't need cache initialization
321 or which want to provide their own cache implementation.
325 config MIPS_CACHE_DISABLE
326 bool "Allow generic start code to initially disable caches"
327 default n if SKIP_LOWLEVEL_INIT
330 This allows the generic start code to initially disable the CPU caches
331 and run uncached until the caches are initialized and enabled. Disabling
332 this can be useful on machines which don't need cache initialization or
333 which want to provide their own cache implementation.
337 config MIPS_RELOCATION_TABLE_SIZE
338 hex "Relocation table size"
342 A table of relocation data will be appended to the U-Boot binary
343 and parsed in relocate_code() to fix up all offsets in the relocated
346 This option allows the amount of space reserved for the table to be
347 adjusted in a range from 256 up to 64k. The default is 32k and should
348 be ok in most cases. Reduce this value to shrink the size of U-Boot
351 The build will fail and a valid size suggested if this is too small.
353 If unsure, leave at the default value.
355 config RESTORE_EXCEPTION_VECTOR_BASE
356 bool "Restore exception vector base before booting linux kernel"
359 In U-Boot the exception vector base will be moved to top of memory,
360 to be used to display register dump when exception occurs.
361 But some old linux kernel does not honor the base set in CP0_EBASE.
362 A modified exception vector base will cause kernel crash.
364 This option will restore the exception vector base to its previous
369 config OVERRIDE_EXCEPTION_VECTOR_BASE
370 bool "Override the exception vector base to be restored"
371 depends on RESTORE_EXCEPTION_VECTOR_BASE
374 Enable this option if you want to use a different exception vector
375 base rather than the previously saved one.
377 config NEW_EXCEPTION_VECTOR_BASE
378 hex "New exception vector base"
379 depends on OVERRIDE_EXCEPTION_VECTOR_BASE
380 range 0x80000000 0xbffff000
383 The exception vector base to be restored before booting linux kernel
385 config INIT_STACK_WITHOUT_MALLOC_F
386 bool "Do not reserve malloc space on initial stack"
389 Enable this option if you don't want to reserve malloc space on
390 initial stack. This is useful if the initial stack can't hold large
391 malloc space. Platform should set the malloc_base later when DRAM is
394 config SPL_INIT_STACK_WITHOUT_MALLOC_F
395 bool "Do not reserve malloc space on initial stack in SPL"
398 Enable this option if you don't want to reserve malloc space on
399 initial stack. This is useful if the initial stack can't hold large
400 malloc space. Platform should set the malloc_base later when DRAM is
403 config SPL_LOADER_SUPPORT
407 Enable this option if you want to use SPL loaders without DM enabled.
411 menu "OS boot interface"
413 config MIPS_BOOT_CMDLINE_LEGACY
414 bool "Hand over legacy command line to Linux kernel"
417 Enable this option if you want U-Boot to hand over the Yamon-style
418 command line to the kernel. All bootargs will be prepared as argc/argv
419 compatible list. The argument count (argc) is stored in register $a0.
420 The address of the argument list (argv) is stored in register $a1.
422 config MIPS_BOOT_ENV_LEGACY
423 bool "Hand over legacy environment to Linux kernel"
426 Enable this option if you want U-Boot to hand over the Yamon-style
427 environment to the kernel. Information like memory size, initrd
428 address and size will be prepared as zero-terminated key/value list.
429 The address of the environment is stored in register $a2.
432 bool "Hand over a flattened device tree to Linux kernel"
435 Enable this option if you want U-Boot to hand over a flattened
436 device tree to the kernel. According to UHI register $a0 will be set
437 to -2 and the FDT address is stored in $a1.
441 config SUPPORTS_BIG_ENDIAN
444 config SUPPORTS_LITTLE_ENDIAN
447 config SUPPORTS_CPU_MIPS32_R1
450 config SUPPORTS_CPU_MIPS32_R2
453 config SUPPORTS_CPU_MIPS32_R6
456 config SUPPORTS_CPU_MIPS64_R1
459 config SUPPORTS_CPU_MIPS64_R2
462 config SUPPORTS_CPU_MIPS64_R6
465 config SUPPORTS_CPU_MIPS64_OCTEON
468 config CPU_CAVIUM_OCTEON
473 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
477 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
478 default y if CPU_MIPS64_OCTEON
483 config MIPS_TUNE_14KC
486 config MIPS_TUNE_24KC
489 config MIPS_TUNE_34KC
492 config MIPS_TUNE_74KC
495 config MIPS_TUNE_OCTEON3
507 config SYS_MIPS_CACHE_INIT_RAM_LOAD
510 config MIPS_INIT_STACK_IN_SRAM
514 Select this if the initial stack frame could be setup in SRAM.
515 Normally the initial stack frame is set up in DRAM which is often
516 only available after lowlevel_init. With this option the initial
517 stack frame and the early C environment is set up before
518 lowlevel_init. Thus lowlevel_init does not need to be implemented
521 config MIPS_SRAM_INIT
524 depends on MIPS_INIT_STACK_IN_SRAM
526 Select this if the SRAM for initial stack needs to be initialized
527 before it can be used. If enabled, a function mips_sram_init() will
528 be called just before setup_stack_gd.
530 config DMA_ADDR_T_64BIT
533 Select this to enable 64-bit DMA addressing
535 config SYS_DCACHE_SIZE
539 The total size of the L1 Dcache, if known at compile time.
541 config SYS_DCACHE_LINE_SIZE
545 The size of L1 Dcache lines, if known at compile time.
547 config SYS_ICACHE_SIZE
551 The total size of the L1 ICache, if known at compile time.
553 config SYS_ICACHE_LINE_SIZE
557 The size of L1 Icache lines, if known at compile time.
559 config SYS_SCACHE_LINE_SIZE
563 The size of L2 cache lines, if known at compile time.
566 config SYS_CACHE_SIZE_AUTO
567 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
568 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \
569 SYS_SCACHE_LINE_SIZE = 0
571 Select this (or let it be auto-selected by not defining any cache
572 sizes) in order to allow U-Boot to automatically detect the sizes
573 of caches at runtime. This has a small cost in code size & runtime
574 so if you know the cache configuration for your system at compile
575 time it would be beneficial to configure it.
577 config MIPS_L1_CACHE_SHIFT_4
580 config MIPS_L1_CACHE_SHIFT_5
583 config MIPS_L1_CACHE_SHIFT_6
586 config MIPS_L1_CACHE_SHIFT_7
589 config MIPS_L1_CACHE_SHIFT
591 default "7" if MIPS_L1_CACHE_SHIFT_7
592 default "6" if MIPS_L1_CACHE_SHIFT_6
593 default "5" if MIPS_L1_CACHE_SHIFT_5
594 default "4" if MIPS_L1_CACHE_SHIFT_4
600 Select this if your system includes an L2 cache and you want U-Boot
601 to initialise & maintain it.
603 config DYNAMIC_IO_PORT_BASE
609 Select this if your system contains a MIPS Coherence Manager and you
610 wish U-Boot to configure it or make use of it to retrieve system
611 information such as cache configuration.
613 config MIPS_INSERT_BOOT_CONFIG
617 Enable this to insert some board-specific boot configuration in
618 the U-Boot binary at offset 0x10.
620 config MIPS_BOOT_CONFIG_WORD0
622 depends on MIPS_INSERT_BOOT_CONFIG
623 default 0x420 if TARGET_MALTA
626 Value which is inserted as boot config word 0.
628 config MIPS_BOOT_CONFIG_WORD1
630 depends on MIPS_INSERT_BOOT_CONFIG
633 Value which is inserted as boot config word 1.