1 menu "MIPS architecture"
8 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
12 prompt "Target select"
15 config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
17 select ROM_EXCEPTION_VECTORS
18 select SUPPORTS_BIG_ENDIAN
19 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
21 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
23 select SUPPORTS_LITTLE_ENDIAN
29 select DYNAMIC_IO_PORT_BASE
31 select MIPS_INSERT_BOOT_CONFIG
32 select MIPS_L1_CACHE_SHIFT_6
36 select ROM_EXCEPTION_VECTORS
37 select SUPPORTS_BIG_ENDIAN
38 select SUPPORTS_CPU_MIPS32_R1
39 select SUPPORTS_CPU_MIPS32_R2
40 select SUPPORTS_CPU_MIPS32_R6
41 select SUPPORTS_CPU_MIPS64_R1
42 select SUPPORTS_CPU_MIPS64_R2
43 select SUPPORTS_CPU_MIPS64_R6
44 select SUPPORTS_LITTLE_ENDIAN
50 select ROM_EXCEPTION_VECTORS
51 select SUPPORTS_BIG_ENDIAN
52 select SUPPORTS_CPU_MIPS32_R1
53 select SUPPORTS_CPU_MIPS32_R2
54 select SYS_MIPS_CACHE_INIT_RAM_LOAD
57 bool "Support QCA/Atheros ath79"
63 bool "Support MSCC VCore-III"
68 bool "Support BMIPS SoCs"
78 bool "Support MediaTek MIPS platforms"
81 select DISPLAY_CPUINFO
93 select LAST_STAGE_INIT
96 select ROM_EXCEPTION_VECTORS
97 select SUPPORTS_CPU_MIPS32_R1
98 select SUPPORTS_CPU_MIPS32_R2
99 select SUPPORTS_LITTLE_ENDIAN
104 bool "Support Ingenic JZ47xx"
110 bool "Support Marvell Octeon CN7xxx platforms"
111 select CPU_CAVIUM_OCTEON
112 select DISPLAY_CPUINFO
113 select DMA_ADDR_T_64BIT
119 select MIPS_TUNE_OCTEON3
120 select ROM_EXCEPTION_VECTORS
121 select SUPPORTS_BIG_ENDIAN
122 select SUPPORTS_CPU_MIPS64_OCTEON
129 bool "Support Microchip PIC32"
135 bool "Support Boston"
139 select MIPS_L1_CACHE_SHIFT_6
141 select OF_BOARD_SETUP
143 select ROM_EXCEPTION_VECTORS
144 select SUPPORTS_BIG_ENDIAN
145 select SUPPORTS_CPU_MIPS32_R1
146 select SUPPORTS_CPU_MIPS32_R2
147 select SUPPORTS_CPU_MIPS32_R6
148 select SUPPORTS_CPU_MIPS64_R1
149 select SUPPORTS_CPU_MIPS64_R2
150 select SUPPORTS_CPU_MIPS64_R6
151 select SUPPORTS_LITTLE_ENDIAN
154 config TARGET_XILFPGA
155 bool "Support Imagination Xilfpga"
160 select MIPS_L1_CACHE_SHIFT_4
162 select ROM_EXCEPTION_VECTORS
163 select SUPPORTS_CPU_MIPS32_R1
164 select SUPPORTS_CPU_MIPS32_R2
165 select SUPPORTS_LITTLE_ENDIAN
168 This supports IMGTEC MIPSfpga platform
172 source "board/imgtec/boston/Kconfig"
173 source "board/imgtec/malta/Kconfig"
174 source "board/imgtec/xilfpga/Kconfig"
175 source "board/qemu-mips/Kconfig"
176 source "arch/mips/mach-ath79/Kconfig"
177 source "arch/mips/mach-mscc/Kconfig"
178 source "arch/mips/mach-bmips/Kconfig"
179 source "arch/mips/mach-jz47xx/Kconfig"
180 source "arch/mips/mach-pic32/Kconfig"
181 source "arch/mips/mach-mtmips/Kconfig"
182 source "arch/mips/mach-octeon/Kconfig"
187 prompt "Endianness selection"
189 Some MIPS boards can be configured for either little or big endian
190 byte order. These modes require different U-Boot images. In general there
191 is one preferred byteorder for a particular system but some systems are
192 just as commonly used in the one or the other endianness.
194 config SYS_BIG_ENDIAN
196 depends on SUPPORTS_BIG_ENDIAN
198 config SYS_LITTLE_ENDIAN
200 depends on SUPPORTS_LITTLE_ENDIAN
205 prompt "CPU selection"
206 default CPU_MIPS32_R2
209 bool "MIPS32 Release 1"
210 depends on SUPPORTS_CPU_MIPS32_R1
213 Choose this option to build an U-Boot for release 1 through 5 of the
217 bool "MIPS32 Release 2"
218 depends on SUPPORTS_CPU_MIPS32_R2
221 Choose this option to build an U-Boot for release 2 through 5 of the
225 bool "MIPS32 Release 6"
226 depends on SUPPORTS_CPU_MIPS32_R6
229 Choose this option to build an U-Boot for release 6 or later of the
233 bool "MIPS64 Release 1"
234 depends on SUPPORTS_CPU_MIPS64_R1
237 Choose this option to build a kernel for release 1 through 5 of the
241 bool "MIPS64 Release 2"
242 depends on SUPPORTS_CPU_MIPS64_R2
245 Choose this option to build a kernel for release 2 through 5 of the
249 bool "MIPS64 Release 6"
250 depends on SUPPORTS_CPU_MIPS64_R6
253 Choose this option to build a kernel for release 6 or later of the
256 config CPU_MIPS64_OCTEON
257 bool "Marvell Octeon series of CPUs"
258 depends on SUPPORTS_CPU_MIPS64_OCTEON
261 Choose this option for Marvell Octeon CPUs. These CPUs are between
262 MIPS64 R5 and R6 with other extensions.
268 config ROM_EXCEPTION_VECTORS
269 bool "Build U-Boot image with exception vectors"
271 Enable this to include exception vectors in the U-Boot image. This is
272 required if the U-Boot entry point is equal to the address of the
273 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
274 U-Boot booted from parallel NOR flash).
275 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
276 In that case the image size will be reduced by 0x500 bytes.
279 hex "MIPS CM GCR Base Address"
281 default 0x16100000 if TARGET_BOSTON
284 The physical base address at which to map the MIPS Coherence Manager
285 Global Configuration Registers (GCRs). This should be set such that
286 the GCRs occupy a region of the physical address space which is
287 otherwise unused, or at minimum that software doesn't need to access.
289 config MIPS_CACHE_INDEX_BASE
290 hex "Index base address for cache initialisation"
291 default 0x80000000 if CPU_MIPS32
292 default 0xffffffff80000000 if CPU_MIPS64
294 This is the base address for a memory block, which is used for
295 initialising the cache lines. This is also the base address of a memory
296 block which is used for loading and filling cache lines when
297 SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
298 Normally this is CKSEG0. If the MIPS system needs to move this block
299 to some SRAM or ScratchPad RAM, adapt this option accordingly.
301 config MIPS_MACH_EARLY_INIT
302 bool "Enable mach specific very early init code"
304 Use this to enable the call to mips_mach_early_init() very early
305 from start.S. This function can be used e.g. to do some very early
306 CPU / SoC intitialization or image copying. Its called very early
307 and at this stage the PC might not match the linking address
308 (CONFIG_TEXT_BASE) - no absolute jump done until this call.
310 config MIPS_CACHE_SETUP
311 bool "Allow generic start code to initialize and setup caches"
312 default n if SKIP_LOWLEVEL_INIT
315 This allows the generic start code to invoke the generic initialization
316 of the CPU caches. Disabling this can be useful for RAM boot scenarios
317 (EJTAG, SPL payload) or for machines which don't need cache initialization
318 or which want to provide their own cache implementation.
322 config MIPS_CACHE_DISABLE
323 bool "Allow generic start code to initially disable caches"
324 default n if SKIP_LOWLEVEL_INIT
327 This allows the generic start code to initially disable the CPU caches
328 and run uncached until the caches are initialized and enabled. Disabling
329 this can be useful on machines which don't need cache initialization or
330 which want to provide their own cache implementation.
334 config MIPS_RELOCATION_TABLE_SIZE
335 hex "Relocation table size"
339 A table of relocation data will be appended to the U-Boot binary
340 and parsed in relocate_code() to fix up all offsets in the relocated
343 This option allows the amount of space reserved for the table to be
344 adjusted in a range from 256 up to 64k. The default is 32k and should
345 be ok in most cases. Reduce this value to shrink the size of U-Boot
348 The build will fail and a valid size suggested if this is too small.
350 If unsure, leave at the default value.
352 config RESTORE_EXCEPTION_VECTOR_BASE
353 bool "Restore exception vector base before booting linux kernel"
356 In U-Boot the exception vector base will be moved to top of memory,
357 to be used to display register dump when exception occurs.
358 But some old linux kernel does not honor the base set in CP0_EBASE.
359 A modified exception vector base will cause kernel crash.
361 This option will restore the exception vector base to its previous
366 config OVERRIDE_EXCEPTION_VECTOR_BASE
367 bool "Override the exception vector base to be restored"
368 depends on RESTORE_EXCEPTION_VECTOR_BASE
371 Enable this option if you want to use a different exception vector
372 base rather than the previously saved one.
374 config NEW_EXCEPTION_VECTOR_BASE
375 hex "New exception vector base"
376 depends on OVERRIDE_EXCEPTION_VECTOR_BASE
377 range 0x80000000 0xbffff000
380 The exception vector base to be restored before booting linux kernel
382 config INIT_STACK_WITHOUT_MALLOC_F
383 bool "Do not reserve malloc space on initial stack"
386 Enable this option if you don't want to reserve malloc space on
387 initial stack. This is useful if the initial stack can't hold large
388 malloc space. Platform should set the malloc_base later when DRAM is
391 config SPL_INIT_STACK_WITHOUT_MALLOC_F
392 bool "Do not reserve malloc space on initial stack in SPL"
395 Enable this option if you don't want to reserve malloc space on
396 initial stack. This is useful if the initial stack can't hold large
397 malloc space. Platform should set the malloc_base later when DRAM is
400 config SPL_LOADER_SUPPORT
404 Enable this option if you want to use SPL loaders without DM enabled.
408 menu "OS boot interface"
410 config MIPS_BOOT_CMDLINE_LEGACY
411 bool "Hand over legacy command line to Linux kernel"
414 Enable this option if you want U-Boot to hand over the Yamon-style
415 command line to the kernel. All bootargs will be prepared as argc/argv
416 compatible list. The argument count (argc) is stored in register $a0.
417 The address of the argument list (argv) is stored in register $a1.
419 config MIPS_BOOT_ENV_LEGACY
420 bool "Hand over legacy environment to Linux kernel"
423 Enable this option if you want U-Boot to hand over the Yamon-style
424 environment to the kernel. Information like memory size, initrd
425 address and size will be prepared as zero-terminated key/value list.
426 The address of the environment is stored in register $a2.
429 bool "Hand over a flattened device tree to Linux kernel"
432 Enable this option if you want U-Boot to hand over a flattened
433 device tree to the kernel. According to UHI register $a0 will be set
434 to -2 and the FDT address is stored in $a1.
438 config SUPPORTS_BIG_ENDIAN
441 config SUPPORTS_LITTLE_ENDIAN
444 config SUPPORTS_CPU_MIPS32_R1
447 config SUPPORTS_CPU_MIPS32_R2
450 config SUPPORTS_CPU_MIPS32_R6
453 config SUPPORTS_CPU_MIPS64_R1
456 config SUPPORTS_CPU_MIPS64_R2
459 config SUPPORTS_CPU_MIPS64_R6
462 config SUPPORTS_CPU_MIPS64_OCTEON
465 config CPU_CAVIUM_OCTEON
470 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
474 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
475 default y if CPU_MIPS64_OCTEON
480 config MIPS_TUNE_14KC
483 config MIPS_TUNE_24KC
486 config MIPS_TUNE_34KC
489 config MIPS_TUNE_74KC
492 config MIPS_TUNE_OCTEON3
504 config SYS_MIPS_CACHE_INIT_RAM_LOAD
507 config MIPS_INIT_STACK_IN_SRAM
511 Select this if the initial stack frame could be setup in SRAM.
512 Normally the initial stack frame is set up in DRAM which is often
513 only available after lowlevel_init. With this option the initial
514 stack frame and the early C environment is set up before
515 lowlevel_init. Thus lowlevel_init does not need to be implemented
518 config MIPS_SRAM_INIT
521 depends on MIPS_INIT_STACK_IN_SRAM
523 Select this if the SRAM for initial stack needs to be initialized
524 before it can be used. If enabled, a function mips_sram_init() will
525 be called just before setup_stack_gd.
527 config DMA_ADDR_T_64BIT
530 Select this to enable 64-bit DMA addressing
532 config SYS_DCACHE_SIZE
536 The total size of the L1 Dcache, if known at compile time.
538 config SYS_DCACHE_LINE_SIZE
542 The size of L1 Dcache lines, if known at compile time.
544 config SYS_ICACHE_SIZE
548 The total size of the L1 ICache, if known at compile time.
550 config SYS_ICACHE_LINE_SIZE
554 The size of L1 Icache lines, if known at compile time.
556 config SYS_SCACHE_LINE_SIZE
560 The size of L2 cache lines, if known at compile time.
563 config SYS_CACHE_SIZE_AUTO
564 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
565 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \
566 SYS_SCACHE_LINE_SIZE = 0
568 Select this (or let it be auto-selected by not defining any cache
569 sizes) in order to allow U-Boot to automatically detect the sizes
570 of caches at runtime. This has a small cost in code size & runtime
571 so if you know the cache configuration for your system at compile
572 time it would be beneficial to configure it.
574 config MIPS_L1_CACHE_SHIFT_4
577 config MIPS_L1_CACHE_SHIFT_5
580 config MIPS_L1_CACHE_SHIFT_6
583 config MIPS_L1_CACHE_SHIFT_7
586 config MIPS_L1_CACHE_SHIFT
588 default "7" if MIPS_L1_CACHE_SHIFT_7
589 default "6" if MIPS_L1_CACHE_SHIFT_6
590 default "5" if MIPS_L1_CACHE_SHIFT_5
591 default "4" if MIPS_L1_CACHE_SHIFT_4
597 Select this if your system includes an L2 cache and you want U-Boot
598 to initialise & maintain it.
600 config DYNAMIC_IO_PORT_BASE
606 Select this if your system contains a MIPS Coherence Manager and you
607 wish U-Boot to configure it or make use of it to retrieve system
608 information such as cache configuration.
610 config MIPS_INSERT_BOOT_CONFIG
614 Enable this to insert some board-specific boot configuration in
615 the U-Boot binary at offset 0x10.
617 config MIPS_BOOT_CONFIG_WORD0
619 depends on MIPS_INSERT_BOOT_CONFIG
620 default 0x420 if TARGET_MALTA
623 Value which is inserted as boot config word 0.
625 config MIPS_BOOT_CONFIG_WORD1
627 depends on MIPS_INSERT_BOOT_CONFIG
630 Value which is inserted as boot config word 1.