1 menu "MIPS architecture"
8 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
12 prompt "Target select"
15 config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
17 select ROM_EXCEPTION_VECTORS
18 select SUPPORTS_BIG_ENDIAN
19 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
21 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
23 select SUPPORTS_LITTLE_ENDIAN
29 select DYNAMIC_IO_PORT_BASE
31 select MIPS_INSERT_BOOT_CONFIG
32 select MIPS_L1_CACHE_SHIFT_6
36 select ROM_EXCEPTION_VECTORS
37 select SUPPORTS_BIG_ENDIAN
38 select SUPPORTS_CPU_MIPS32_R1
39 select SUPPORTS_CPU_MIPS32_R2
40 select SUPPORTS_CPU_MIPS32_R6
41 select SUPPORTS_CPU_MIPS64_R1
42 select SUPPORTS_CPU_MIPS64_R2
43 select SUPPORTS_CPU_MIPS64_R6
44 select SUPPORTS_LITTLE_ENDIAN
50 select ROM_EXCEPTION_VECTORS
51 select SUPPORTS_BIG_ENDIAN
52 select SUPPORTS_CPU_MIPS32_R1
53 select SUPPORTS_CPU_MIPS32_R2
54 select SYS_MIPS_CACHE_INIT_RAM_LOAD
57 bool "Support QCA/Atheros ath79"
63 bool "Support MSCC VCore-III"
68 bool "Support BMIPS SoCs"
78 bool "Support MediaTek MIPS platforms"
81 select DISPLAY_CPUINFO
93 select LAST_STAGE_INIT
96 select ROM_EXCEPTION_VECTORS
97 select SUPPORTS_CPU_MIPS32_R1
98 select SUPPORTS_CPU_MIPS32_R2
99 select SUPPORTS_LITTLE_ENDIAN
103 bool "Support Ingenic JZ47xx"
109 bool "Support Microchip PIC32"
115 bool "Support Boston"
119 select MIPS_L1_CACHE_SHIFT_6
121 select OF_BOARD_SETUP
123 select ROM_EXCEPTION_VECTORS
124 select SUPPORTS_BIG_ENDIAN
125 select SUPPORTS_CPU_MIPS32_R1
126 select SUPPORTS_CPU_MIPS32_R2
127 select SUPPORTS_CPU_MIPS32_R6
128 select SUPPORTS_CPU_MIPS64_R1
129 select SUPPORTS_CPU_MIPS64_R2
130 select SUPPORTS_CPU_MIPS64_R6
131 select SUPPORTS_LITTLE_ENDIAN
134 config TARGET_XILFPGA
135 bool "Support Imagination Xilfpga"
140 select MIPS_L1_CACHE_SHIFT_4
142 select ROM_EXCEPTION_VECTORS
143 select SUPPORTS_CPU_MIPS32_R1
144 select SUPPORTS_CPU_MIPS32_R2
145 select SUPPORTS_LITTLE_ENDIAN
148 This supports IMGTEC MIPSfpga platform
152 source "board/imgtec/boston/Kconfig"
153 source "board/imgtec/malta/Kconfig"
154 source "board/imgtec/xilfpga/Kconfig"
155 source "board/qemu-mips/Kconfig"
156 source "arch/mips/mach-ath79/Kconfig"
157 source "arch/mips/mach-mscc/Kconfig"
158 source "arch/mips/mach-bmips/Kconfig"
159 source "arch/mips/mach-jz47xx/Kconfig"
160 source "arch/mips/mach-pic32/Kconfig"
161 source "arch/mips/mach-mtmips/Kconfig"
166 prompt "Endianness selection"
168 Some MIPS boards can be configured for either little or big endian
169 byte order. These modes require different U-Boot images. In general there
170 is one preferred byteorder for a particular system but some systems are
171 just as commonly used in the one or the other endianness.
173 config SYS_BIG_ENDIAN
175 depends on SUPPORTS_BIG_ENDIAN
177 config SYS_LITTLE_ENDIAN
179 depends on SUPPORTS_LITTLE_ENDIAN
184 prompt "CPU selection"
185 default CPU_MIPS32_R2
188 bool "MIPS32 Release 1"
189 depends on SUPPORTS_CPU_MIPS32_R1
192 Choose this option to build an U-Boot for release 1 through 5 of the
196 bool "MIPS32 Release 2"
197 depends on SUPPORTS_CPU_MIPS32_R2
200 Choose this option to build an U-Boot for release 2 through 5 of the
204 bool "MIPS32 Release 6"
205 depends on SUPPORTS_CPU_MIPS32_R6
208 Choose this option to build an U-Boot for release 6 or later of the
212 bool "MIPS64 Release 1"
213 depends on SUPPORTS_CPU_MIPS64_R1
216 Choose this option to build a kernel for release 1 through 5 of the
220 bool "MIPS64 Release 2"
221 depends on SUPPORTS_CPU_MIPS64_R2
224 Choose this option to build a kernel for release 2 through 5 of the
228 bool "MIPS64 Release 6"
229 depends on SUPPORTS_CPU_MIPS64_R6
232 Choose this option to build a kernel for release 6 or later of the
239 config ROM_EXCEPTION_VECTORS
240 bool "Build U-Boot image with exception vectors"
242 Enable this to include exception vectors in the U-Boot image. This is
243 required if the U-Boot entry point is equal to the address of the
244 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
245 U-Boot booted from parallel NOR flash).
246 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
247 In that case the image size will be reduced by 0x500 bytes.
250 hex "MIPS CM GCR Base Address"
252 default 0x16100000 if TARGET_BOSTON
255 The physical base address at which to map the MIPS Coherence Manager
256 Global Configuration Registers (GCRs). This should be set such that
257 the GCRs occupy a region of the physical address space which is
258 otherwise unused, or at minimum that software doesn't need to access.
260 config MIPS_CACHE_INDEX_BASE
261 hex "Index base address for cache initialisation"
262 default 0x80000000 if CPU_MIPS32
263 default 0xffffffff80000000 if CPU_MIPS64
265 This is the base address for a memory block, which is used for
266 initialising the cache lines. This is also the base address of a memory
267 block which is used for loading and filling cache lines when
268 SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
269 Normally this is CKSEG0. If the MIPS system needs to move this block
270 to some SRAM or ScratchPad RAM, adapt this option accordingly.
272 config MIPS_RELOCATION_TABLE_SIZE
273 hex "Relocation table size"
277 A table of relocation data will be appended to the U-Boot binary
278 and parsed in relocate_code() to fix up all offsets in the relocated
281 This option allows the amount of space reserved for the table to be
282 adjusted in a range from 256 up to 64k. The default is 32k and should
283 be ok in most cases. Reduce this value to shrink the size of U-Boot
286 The build will fail and a valid size suggested if this is too small.
288 If unsure, leave at the default value.
292 menu "OS boot interface"
294 config MIPS_BOOT_CMDLINE_LEGACY
295 bool "Hand over legacy command line to Linux kernel"
298 Enable this option if you want U-Boot to hand over the Yamon-style
299 command line to the kernel. All bootargs will be prepared as argc/argv
300 compatible list. The argument count (argc) is stored in register $a0.
301 The address of the argument list (argv) is stored in register $a1.
303 config MIPS_BOOT_ENV_LEGACY
304 bool "Hand over legacy environment to Linux kernel"
307 Enable this option if you want U-Boot to hand over the Yamon-style
308 environment to the kernel. Information like memory size, initrd
309 address and size will be prepared as zero-terminated key/value list.
310 The address of the environment is stored in register $a2.
313 bool "Hand over a flattened device tree to Linux kernel"
316 Enable this option if you want U-Boot to hand over a flattened
317 device tree to the kernel. According to UHI register $a0 will be set
318 to -2 and the FDT address is stored in $a1.
322 config SUPPORTS_BIG_ENDIAN
325 config SUPPORTS_LITTLE_ENDIAN
328 config SUPPORTS_CPU_MIPS32_R1
331 config SUPPORTS_CPU_MIPS32_R2
334 config SUPPORTS_CPU_MIPS32_R6
337 config SUPPORTS_CPU_MIPS64_R1
340 config SUPPORTS_CPU_MIPS64_R2
343 config SUPPORTS_CPU_MIPS64_R6
348 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
352 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
357 config MIPS_TUNE_14KC
360 config MIPS_TUNE_24KC
363 config MIPS_TUNE_34KC
366 config MIPS_TUNE_74KC
378 config SYS_MIPS_CACHE_INIT_RAM_LOAD
381 config MIPS_INIT_STACK_IN_SRAM
385 Select this if the initial stack frame could be setup in SRAM.
386 Normally the initial stack frame is set up in DRAM which is often
387 only available after lowlevel_init. With this option the initial
388 stack frame and the early C environment is set up before
389 lowlevel_init. Thus lowlevel_init does not need to be implemented
392 config SYS_DCACHE_SIZE
396 The total size of the L1 Dcache, if known at compile time.
398 config SYS_DCACHE_LINE_SIZE
402 The size of L1 Dcache lines, if known at compile time.
404 config SYS_ICACHE_SIZE
408 The total size of the L1 ICache, if known at compile time.
410 config SYS_ICACHE_LINE_SIZE
414 The size of L1 Icache lines, if known at compile time.
416 config SYS_SCACHE_LINE_SIZE
420 The size of L2 cache lines, if known at compile time.
423 config SYS_CACHE_SIZE_AUTO
424 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
425 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \
426 SYS_SCACHE_LINE_SIZE = 0
428 Select this (or let it be auto-selected by not defining any cache
429 sizes) in order to allow U-Boot to automatically detect the sizes
430 of caches at runtime. This has a small cost in code size & runtime
431 so if you know the cache configuration for your system at compile
432 time it would be beneficial to configure it.
434 config MIPS_L1_CACHE_SHIFT_4
437 config MIPS_L1_CACHE_SHIFT_5
440 config MIPS_L1_CACHE_SHIFT_6
443 config MIPS_L1_CACHE_SHIFT_7
446 config MIPS_L1_CACHE_SHIFT
448 default "7" if MIPS_L1_CACHE_SHIFT_7
449 default "6" if MIPS_L1_CACHE_SHIFT_6
450 default "5" if MIPS_L1_CACHE_SHIFT_5
451 default "4" if MIPS_L1_CACHE_SHIFT_4
457 Select this if your system includes an L2 cache and you want U-Boot
458 to initialise & maintain it.
460 config DYNAMIC_IO_PORT_BASE
466 Select this if your system contains a MIPS Coherence Manager and you
467 wish U-Boot to configure it or make use of it to retrieve system
468 information such as cache configuration.
470 config MIPS_INSERT_BOOT_CONFIG
474 Enable this to insert some board-specific boot configuration in
475 the U-Boot binary at offset 0x10.
477 config MIPS_BOOT_CONFIG_WORD0
479 depends on MIPS_INSERT_BOOT_CONFIG
480 default 0x420 if TARGET_MALTA
483 Value which is inserted as boot config word 0.
485 config MIPS_BOOT_CONFIG_WORD1
487 depends on MIPS_INSERT_BOOT_CONFIG
490 Value which is inserted as boot config word 1.