1 menu "MIPS architecture"
8 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
12 prompt "Target select"
15 config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
17 select SUPPORTS_BIG_ENDIAN
18 select SUPPORTS_LITTLE_ENDIAN
19 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
21 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
23 select ROM_EXCEPTION_VECTORS
29 select DYNAMIC_IO_PORT_BASE
34 select SUPPORTS_BIG_ENDIAN
35 select SUPPORTS_LITTLE_ENDIAN
36 select SUPPORTS_CPU_MIPS32_R1
37 select SUPPORTS_CPU_MIPS32_R2
38 select SUPPORTS_CPU_MIPS32_R6
39 select SUPPORTS_CPU_MIPS64_R1
40 select SUPPORTS_CPU_MIPS64_R2
41 select SUPPORTS_CPU_MIPS64_R6
43 select MIPS_L1_CACHE_SHIFT_6
44 select ROM_EXCEPTION_VECTORS
48 select SUPPORTS_BIG_ENDIAN
49 select SUPPORTS_CPU_MIPS32_R1
50 select SUPPORTS_CPU_MIPS32_R2
51 select SYS_MIPS_CACHE_INIT_RAM_LOAD
52 select ROM_EXCEPTION_VECTORS
54 config TARGET_DBAU1X00
55 bool "Support dbau1x00"
56 select SUPPORTS_BIG_ENDIAN
57 select SUPPORTS_LITTLE_ENDIAN
58 select SUPPORTS_CPU_MIPS32_R1
59 select SUPPORTS_CPU_MIPS32_R2
60 select SYS_MIPS_CACHE_INIT_RAM_LOAD
61 select ROM_EXCEPTION_VECTORS
66 select SUPPORTS_LITTLE_ENDIAN
67 select SUPPORTS_CPU_MIPS32_R1
68 select SUPPORTS_CPU_MIPS32_R2
69 select SYS_MIPS_CACHE_INIT_RAM_LOAD
70 select ROM_EXCEPTION_VECTORS
74 bool "Support QCA/Atheros ath79"
79 bool "Support BMIPS SoCs"
89 bool "Support Microchip PIC32"
99 select MIPS_L1_CACHE_SHIFT_6
101 select OF_BOARD_SETUP
102 select SUPPORTS_BIG_ENDIAN
103 select SUPPORTS_LITTLE_ENDIAN
104 select SUPPORTS_CPU_MIPS32_R1
105 select SUPPORTS_CPU_MIPS32_R2
106 select SUPPORTS_CPU_MIPS32_R6
107 select SUPPORTS_CPU_MIPS64_R1
108 select SUPPORTS_CPU_MIPS64_R2
109 select SUPPORTS_CPU_MIPS64_R6
110 select ROM_EXCEPTION_VECTORS
112 config TARGET_XILFPGA
113 bool "Support Imagination Xilfpga"
119 select SUPPORTS_LITTLE_ENDIAN
120 select SUPPORTS_CPU_MIPS32_R1
121 select SUPPORTS_CPU_MIPS32_R2
122 select MIPS_L1_CACHE_SHIFT_4
123 select ROM_EXCEPTION_VECTORS
125 This supports IMGTEC MIPSfpga platform
129 source "board/dbau1x00/Kconfig"
130 source "board/imgtec/boston/Kconfig"
131 source "board/imgtec/malta/Kconfig"
132 source "board/imgtec/xilfpga/Kconfig"
133 source "board/micronas/vct/Kconfig"
134 source "board/pb1x00/Kconfig"
135 source "board/qemu-mips/Kconfig"
136 source "arch/mips/mach-ath79/Kconfig"
137 source "arch/mips/mach-bmips/Kconfig"
138 source "arch/mips/mach-pic32/Kconfig"
143 prompt "Endianness selection"
145 Some MIPS boards can be configured for either little or big endian
146 byte order. These modes require different U-Boot images. In general there
147 is one preferred byteorder for a particular system but some systems are
148 just as commonly used in the one or the other endianness.
150 config SYS_BIG_ENDIAN
152 depends on SUPPORTS_BIG_ENDIAN
154 config SYS_LITTLE_ENDIAN
156 depends on SUPPORTS_LITTLE_ENDIAN
161 prompt "CPU selection"
162 default CPU_MIPS32_R2
165 bool "MIPS32 Release 1"
166 depends on SUPPORTS_CPU_MIPS32_R1
169 Choose this option to build an U-Boot for release 1 through 5 of the
173 bool "MIPS32 Release 2"
174 depends on SUPPORTS_CPU_MIPS32_R2
177 Choose this option to build an U-Boot for release 2 through 5 of the
181 bool "MIPS32 Release 6"
182 depends on SUPPORTS_CPU_MIPS32_R6
185 Choose this option to build an U-Boot for release 6 or later of the
189 bool "MIPS64 Release 1"
190 depends on SUPPORTS_CPU_MIPS64_R1
193 Choose this option to build a kernel for release 1 through 5 of the
197 bool "MIPS64 Release 2"
198 depends on SUPPORTS_CPU_MIPS64_R2
201 Choose this option to build a kernel for release 2 through 5 of the
205 bool "MIPS64 Release 6"
206 depends on SUPPORTS_CPU_MIPS64_R6
209 Choose this option to build a kernel for release 6 or later of the
216 config ROM_EXCEPTION_VECTORS
217 bool "Build U-Boot image with exception vectors"
219 Enable this to include exception vectors in the U-Boot image. This is
220 required if the U-Boot entry point is equal to the address of the
221 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
222 U-Boot booted from parallel NOR flash).
223 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
224 In that case the image size will be reduced by 0x500 bytes.
227 hex "MIPS CM GCR Base Address"
229 default 0x16100000 if TARGET_BOSTON
232 The physical base address at which to map the MIPS Coherence Manager
233 Global Configuration Registers (GCRs). This should be set such that
234 the GCRs occupy a region of the physical address space which is
235 otherwise unused, or at minimum that software doesn't need to access.
239 menu "OS boot interface"
241 config MIPS_BOOT_CMDLINE_LEGACY
242 bool "Hand over legacy command line to Linux kernel"
245 Enable this option if you want U-Boot to hand over the Yamon-style
246 command line to the kernel. All bootargs will be prepared as argc/argv
247 compatible list. The argument count (argc) is stored in register $a0.
248 The address of the argument list (argv) is stored in register $a1.
250 config MIPS_BOOT_ENV_LEGACY
251 bool "Hand over legacy environment to Linux kernel"
254 Enable this option if you want U-Boot to hand over the Yamon-style
255 environment to the kernel. Information like memory size, initrd
256 address and size will be prepared as zero-terminated key/value list.
257 The address of the environment is stored in register $a2.
260 bool "Hand over a flattened device tree to Linux kernel"
263 Enable this option if you want U-Boot to hand over a flattened
264 device tree to the kernel. According to UHI register $a0 will be set
265 to -2 and the FDT address is stored in $a1.
269 config SUPPORTS_BIG_ENDIAN
272 config SUPPORTS_LITTLE_ENDIAN
275 config SUPPORTS_CPU_MIPS32_R1
278 config SUPPORTS_CPU_MIPS32_R2
281 config SUPPORTS_CPU_MIPS32_R6
284 config SUPPORTS_CPU_MIPS64_R1
287 config SUPPORTS_CPU_MIPS64_R2
290 config SUPPORTS_CPU_MIPS64_R6
295 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
299 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
304 config MIPS_TUNE_14KC
307 config MIPS_TUNE_24KC
310 config MIPS_TUNE_34KC
313 config MIPS_TUNE_74KC
325 config SYS_MIPS_CACHE_INIT_RAM_LOAD
328 config MIPS_INIT_STACK_IN_SRAM
332 Select this if the initial stack frame could be setup in SRAM.
333 Normally the initial stack frame is set up in DRAM which is often
334 only available after lowlevel_init. With this option the initial
335 stack frame and the early C environment is set up before
336 lowlevel_init. Thus lowlevel_init does not need to be implemented
339 config SYS_DCACHE_SIZE
343 The total size of the L1 Dcache, if known at compile time.
345 config SYS_DCACHE_LINE_SIZE
349 The size of L1 Dcache lines, if known at compile time.
351 config SYS_ICACHE_SIZE
355 The total size of the L1 ICache, if known at compile time.
357 config SYS_ICACHE_LINE_SIZE
361 The size of L1 Icache lines, if known at compile time.
363 config SYS_CACHE_SIZE_AUTO
364 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
365 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
367 Select this (or let it be auto-selected by not defining any cache
368 sizes) in order to allow U-Boot to automatically detect the sizes
369 of caches at runtime. This has a small cost in code size & runtime
370 so if you know the cache configuration for your system at compile
371 time it would be beneficial to configure it.
373 config MIPS_L1_CACHE_SHIFT_4
376 config MIPS_L1_CACHE_SHIFT_5
379 config MIPS_L1_CACHE_SHIFT_6
382 config MIPS_L1_CACHE_SHIFT_7
385 config MIPS_L1_CACHE_SHIFT
387 default "7" if MIPS_L1_CACHE_SHIFT_7
388 default "6" if MIPS_L1_CACHE_SHIFT_6
389 default "5" if MIPS_L1_CACHE_SHIFT_5
390 default "4" if MIPS_L1_CACHE_SHIFT_4
396 Select this if your system includes an L2 cache and you want U-Boot
397 to initialise & maintain it.
399 config DYNAMIC_IO_PORT_BASE
405 Select this if your system contains a MIPS Coherence Manager and you
406 wish U-Boot to configure it or make use of it to retrieve system
407 information such as cache configuration.