1 menu "MIPS architecture"
8 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
12 prompt "Target select"
17 select HAS_FIXED_TIMER_FREQUENCY
18 select BOARD_EARLY_INIT_R
22 select DYNAMIC_IO_PORT_BASE
24 select MIPS_INSERT_BOOT_CONFIG
25 select SYS_CACHE_SHIFT_6
29 select PCI_MAP_SYSTEM_MEMORY
30 select ROM_EXCEPTION_VECTORS
31 select SUPPORTS_BIG_ENDIAN
32 select SUPPORTS_CPU_MIPS32_R1
33 select SUPPORTS_CPU_MIPS32_R2
34 select SUPPORTS_CPU_MIPS32_R6
35 select SUPPORTS_CPU_MIPS64_R1
36 select SUPPORTS_CPU_MIPS64_R2
37 select SUPPORTS_CPU_MIPS64_R6
38 select SUPPORTS_LITTLE_ENDIAN
43 bool "Support QCA/Atheros ath79"
44 select HAS_FIXED_TIMER_FREQUENCY
50 bool "Support MSCC VCore-III"
51 select HAS_FIXED_TIMER_FREQUENCY
56 bool "Support BMIPS SoCs"
57 select HAS_FIXED_TIMER_FREQUENCY
67 bool "Support MediaTek MIPS platforms"
68 select HAS_FIXED_TIMER_FREQUENCY
71 select DISPLAY_CPUINFO
82 select LAST_STAGE_INIT
85 select ROM_EXCEPTION_VECTORS
86 select SUPPORTS_CPU_MIPS32_R1
87 select SUPPORTS_CPU_MIPS32_R2
88 select SUPPORTS_LITTLE_ENDIAN
92 bool "Support Ingenic JZ47xx"
94 select HAS_FIXED_TIMER_FREQUENCY
99 bool "Support Marvell Octeon CN7xxx platforms"
100 select ARCH_EARLY_INIT_R
101 select CPU_CAVIUM_OCTEON
102 select DISPLAY_CPUINFO
103 select DMA_ADDR_T_64BIT
110 select MIPS_MACH_EARLY_INIT
111 select MIPS_TUNE_OCTEON3
112 select ROM_EXCEPTION_VECTORS
113 select SUPPORTS_BIG_ENDIAN
114 select SUPPORTS_CPU_MIPS64_OCTEON
121 bool "Support Microchip PIC32"
122 select HAS_FIXED_TIMER_FREQUENCY
129 bool "Support Boston"
130 select HAS_FIXED_TIMER_FREQUENCY
134 select SYS_CACHE_SHIFT_6
136 select OF_BOARD_SETUP
138 select ROM_EXCEPTION_VECTORS
139 select SUPPORTS_BIG_ENDIAN
140 select SUPPORTS_CPU_MIPS32_R1
141 select SUPPORTS_CPU_MIPS32_R2
142 select SUPPORTS_CPU_MIPS32_R6
143 select SUPPORTS_CPU_MIPS64_R1
144 select SUPPORTS_CPU_MIPS64_R2
145 select SUPPORTS_CPU_MIPS64_R6
146 select SUPPORTS_LITTLE_ENDIAN
149 config TARGET_XILFPGA
150 bool "Support Imagination Xilfpga"
151 select HAS_FIXED_TIMER_FREQUENCY
155 select SYS_CACHE_SHIFT_4
157 select ROM_EXCEPTION_VECTORS
158 select SUPPORTS_CPU_MIPS32_R1
159 select SUPPORTS_CPU_MIPS32_R2
160 select SUPPORTS_LITTLE_ENDIAN
163 This supports IMGTEC MIPSfpga platform
167 source "board/imgtec/boston/Kconfig"
168 source "board/imgtec/malta/Kconfig"
169 source "board/imgtec/xilfpga/Kconfig"
170 source "arch/mips/mach-ath79/Kconfig"
171 source "arch/mips/mach-mscc/Kconfig"
172 source "arch/mips/mach-bmips/Kconfig"
173 source "arch/mips/mach-jz47xx/Kconfig"
174 source "arch/mips/mach-pic32/Kconfig"
175 source "arch/mips/mach-mtmips/Kconfig"
176 source "arch/mips/mach-octeon/Kconfig"
181 prompt "CPU selection"
182 default CPU_MIPS32_R2
185 bool "MIPS32 Release 1"
186 depends on SUPPORTS_CPU_MIPS32_R1
189 Choose this option to build an U-Boot for release 1 through 5 of the
193 bool "MIPS32 Release 2"
194 depends on SUPPORTS_CPU_MIPS32_R2
197 Choose this option to build an U-Boot for release 2 through 5 of the
201 bool "MIPS32 Release 6"
202 depends on SUPPORTS_CPU_MIPS32_R6
205 Choose this option to build an U-Boot for release 6 or later of the
209 bool "MIPS64 Release 1"
210 depends on SUPPORTS_CPU_MIPS64_R1
213 Choose this option to build a kernel for release 1 through 5 of the
217 bool "MIPS64 Release 2"
218 depends on SUPPORTS_CPU_MIPS64_R2
221 Choose this option to build a kernel for release 2 through 5 of the
225 bool "MIPS64 Release 6"
226 depends on SUPPORTS_CPU_MIPS64_R6
229 Choose this option to build a kernel for release 6 or later of the
232 config CPU_MIPS64_OCTEON
233 bool "Marvell Octeon series of CPUs"
234 depends on SUPPORTS_CPU_MIPS64_OCTEON
237 Choose this option for Marvell Octeon CPUs. These CPUs are between
238 MIPS64 R5 and R6 with other extensions.
244 config ROM_EXCEPTION_VECTORS
245 bool "Build U-Boot image with exception vectors"
247 Enable this to include exception vectors in the U-Boot image. This is
248 required if the U-Boot entry point is equal to the address of the
249 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
250 U-Boot booted from parallel NOR flash).
251 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
252 In that case the image size will be reduced by 0x500 bytes.
254 config SYS_MIPS_TIMER_FREQ
255 int "Fixed MIPS CPU timer frequency in Hz"
256 depends on HAS_FIXED_TIMER_FREQUENCY
258 Configures a fixed CPU timer frequency.
261 hex "MIPS CM GCR Base Address"
263 default 0x16100000 if TARGET_BOSTON
266 The physical base address at which to map the MIPS Coherence Manager
267 Global Configuration Registers (GCRs). This should be set such that
268 the GCRs occupy a region of the physical address space which is
269 otherwise unused, or at minimum that software doesn't need to access.
271 config MIPS_CACHE_INDEX_BASE
272 hex "Index base address for cache initialisation"
273 default 0x80000000 if CPU_MIPS32
274 default 0xffffffff80000000 if CPU_MIPS64
276 This is the base address for a memory block, which is used for
277 initialising the cache lines. This is also the base address of a memory
278 block which is used for loading and filling cache lines when
279 SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
280 Normally this is CKSEG0. If the MIPS system needs to move this block
281 to some SRAM or ScratchPad RAM, adapt this option accordingly.
283 config MIPS_MACH_EARLY_INIT
284 bool "Enable mach specific very early init code"
286 Use this to enable the call to mips_mach_early_init() very early
287 from start.S. This function can be used e.g. to do some very early
288 CPU / SoC intitialization or image copying. Its called very early
289 and at this stage the PC might not match the linking address
290 (CONFIG_TEXT_BASE) - no absolute jump done until this call.
292 config MIPS_CACHE_SETUP
293 bool "Allow generic start code to initialize and setup caches"
294 default n if SKIP_LOWLEVEL_INIT
297 This allows the generic start code to invoke the generic initialization
298 of the CPU caches. Disabling this can be useful for RAM boot scenarios
299 (EJTAG, SPL payload) or for machines which don't need cache initialization
300 or which want to provide their own cache implementation.
304 config MIPS_CACHE_DISABLE
305 bool "Allow generic start code to initially disable caches"
306 default n if SKIP_LOWLEVEL_INIT
309 This allows the generic start code to initially disable the CPU caches
310 and run uncached until the caches are initialized and enabled. Disabling
311 this can be useful on machines which don't need cache initialization or
312 which want to provide their own cache implementation.
316 config MIPS_RELOCATION_TABLE_SIZE
317 hex "Relocation table size"
321 A table of relocation data will be appended to the U-Boot binary
322 and parsed in relocate_code() to fix up all offsets in the relocated
325 This option allows the amount of space reserved for the table to be
326 adjusted in a range from 256 up to 64k. The default is 32k and should
327 be ok in most cases. Reduce this value to shrink the size of U-Boot
330 The build will fail and a valid size suggested if this is too small.
332 If unsure, leave at the default value.
334 config RESTORE_EXCEPTION_VECTOR_BASE
335 bool "Restore exception vector base before booting linux kernel"
337 In U-Boot the exception vector base will be moved to top of memory,
338 to be used to display register dump when exception occurs.
339 But some old linux kernel does not honor the base set in CP0_EBASE.
340 A modified exception vector base will cause kernel crash.
342 This option will restore the exception vector base to its previous
347 config OVERRIDE_EXCEPTION_VECTOR_BASE
348 bool "Override the exception vector base to be restored"
349 depends on RESTORE_EXCEPTION_VECTOR_BASE
351 Enable this option if you want to use a different exception vector
352 base rather than the previously saved one.
354 config NEW_EXCEPTION_VECTOR_BASE
355 hex "New exception vector base"
356 depends on OVERRIDE_EXCEPTION_VECTOR_BASE
357 range 0x80000000 0xbffff000
360 The exception vector base to be restored before booting linux kernel
362 config INIT_STACK_WITHOUT_MALLOC_F
363 bool "Do not reserve malloc space on initial stack"
365 Enable this option if you don't want to reserve malloc space on
366 initial stack. This is useful if the initial stack can't hold large
367 malloc space. Platform should set the malloc_base later when DRAM is
370 config SPL_INIT_STACK_WITHOUT_MALLOC_F
371 bool "Do not reserve malloc space on initial stack in SPL"
373 Enable this option if you don't want to reserve malloc space on
374 initial stack. This is useful if the initial stack can't hold large
375 malloc space. Platform should set the malloc_base later when DRAM is
378 config SPL_LOADER_SUPPORT
381 Enable this option if you want to use SPL loaders without DM enabled.
385 menu "OS boot interface"
387 config MIPS_BOOT_CMDLINE_LEGACY
388 bool "Hand over legacy command line to Linux kernel"
391 Enable this option if you want U-Boot to hand over the Yamon-style
392 command line to the kernel. All bootargs will be prepared as argc/argv
393 compatible list. The argument count (argc) is stored in register $a0.
394 The address of the argument list (argv) is stored in register $a1.
396 config MIPS_BOOT_ENV_LEGACY
397 bool "Hand over legacy environment to Linux kernel"
400 Enable this option if you want U-Boot to hand over the Yamon-style
401 environment to the kernel. Information like memory size, initrd
402 address and size will be prepared as zero-terminated key/value list.
403 The address of the environment is stored in register $a2.
406 bool "Hand over a flattened device tree to Linux kernel"
408 Enable this option if you want U-Boot to hand over a flattened
409 device tree to the kernel. According to UHI register $a0 will be set
410 to -2 and the FDT address is stored in $a1.
414 config SUPPORTS_BIG_ENDIAN
417 config SUPPORTS_LITTLE_ENDIAN
420 config SUPPORTS_CPU_MIPS32_R1
423 config SUPPORTS_CPU_MIPS32_R2
426 config SUPPORTS_CPU_MIPS32_R6
429 config SUPPORTS_CPU_MIPS64_R1
432 config SUPPORTS_CPU_MIPS64_R2
435 config SUPPORTS_CPU_MIPS64_R6
438 config SUPPORTS_CPU_MIPS64_OCTEON
441 config HAS_FIXED_TIMER_FREQUENCY
444 config CPU_CAVIUM_OCTEON
449 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
453 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
454 default y if CPU_MIPS64_OCTEON
459 config MIPS_TUNE_14KC
462 config MIPS_TUNE_24KC
465 config MIPS_TUNE_34KC
468 config MIPS_TUNE_74KC
471 config MIPS_TUNE_OCTEON3
483 config SYS_MIPS_CACHE_INIT_RAM_LOAD
486 config MIPS_INIT_STACK_IN_SRAM
489 Select this if the initial stack frame could be setup in SRAM.
490 Normally the initial stack frame is set up in DRAM which is often
491 only available after lowlevel_init. With this option the initial
492 stack frame and the early C environment is set up before
493 lowlevel_init. Thus lowlevel_init does not need to be implemented
496 config MIPS_SRAM_INIT
498 depends on MIPS_INIT_STACK_IN_SRAM
500 Select this if the SRAM for initial stack needs to be initialized
501 before it can be used. If enabled, a function mips_sram_init() will
502 be called just before setup_stack_gd.
504 config DMA_ADDR_T_64BIT
507 Select this to enable 64-bit DMA addressing
509 config SYS_DCACHE_SIZE
513 The total size of the L1 Dcache, if known at compile time.
515 config SYS_DCACHE_LINE_SIZE
519 The size of L1 Dcache lines, if known at compile time.
521 config SYS_ICACHE_SIZE
525 The total size of the L1 ICache, if known at compile time.
527 config SYS_ICACHE_LINE_SIZE
531 The size of L1 Icache lines, if known at compile time.
533 config SYS_SCACHE_LINE_SIZE
537 The size of L2 cache lines, if known at compile time.
540 config SYS_CACHE_SIZE_AUTO
541 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
542 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \
543 SYS_SCACHE_LINE_SIZE = 0
545 Select this (or let it be auto-selected by not defining any cache
546 sizes) in order to allow U-Boot to automatically detect the sizes
547 of caches at runtime. This has a small cost in code size & runtime
548 so if you know the cache configuration for your system at compile
549 time it would be beneficial to configure it.
554 Select this if your system includes an L2 cache and you want U-Boot
555 to initialise & maintain it.
557 config DYNAMIC_IO_PORT_BASE
563 Select this if your system contains a MIPS Coherence Manager and you
564 wish U-Boot to configure it or make use of it to retrieve system
565 information such as cache configuration.
567 config MIPS_INSERT_BOOT_CONFIG
570 Enable this to insert some board-specific boot configuration in
571 the U-Boot binary at offset 0x10.
573 config MIPS_BOOT_CONFIG_WORD0
575 depends on MIPS_INSERT_BOOT_CONFIG
576 default 0x420 if TARGET_MALTA
579 Value which is inserted as boot config word 0.
581 config MIPS_BOOT_CONFIG_WORD1
583 depends on MIPS_INSERT_BOOT_CONFIG
586 Value which is inserted as boot config word 1.