2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
25 #include <linux/list.h>
26 #include <linux/syscalls.h>
27 #include <linux/irq.h>
28 #include <linux/vmalloc.h>
29 #include <linux/slab.h>
31 #include <linux/of_address.h>
32 #include <linux/of_pci.h>
33 #include <linux/export.h>
35 #include <asm/processor.h>
37 #include <asm/pci-bridge.h>
38 #include <asm/byteorder.h>
40 static DEFINE_SPINLOCK(hose_spinlock);
43 /* XXX kill that some day ... */
44 static int global_phb_number; /* Global phb counter */
46 /* ISA Memory physical address */
47 resource_size_t isa_mem_base;
49 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
51 unsigned long isa_io_base;
52 unsigned long pci_dram_offset;
53 static int pci_bus_count;
56 void set_pci_dma_ops(struct dma_map_ops *dma_ops)
58 pci_dma_ops = dma_ops;
61 struct dma_map_ops *get_pci_dma_ops(void)
65 EXPORT_SYMBOL(get_pci_dma_ops);
67 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
69 struct pci_controller *phb;
71 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
74 spin_lock(&hose_spinlock);
75 phb->global_number = global_phb_number++;
76 list_add_tail(&phb->list_node, &hose_list);
77 spin_unlock(&hose_spinlock);
79 phb->is_dynamic = mem_init_done;
83 void pcibios_free_controller(struct pci_controller *phb)
85 spin_lock(&hose_spinlock);
86 list_del(&phb->list_node);
87 spin_unlock(&hose_spinlock);
93 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
95 return resource_size(&hose->io_resource);
98 int pcibios_vaddr_is_ioport(void __iomem *address)
101 struct pci_controller *hose;
102 resource_size_t size;
104 spin_lock(&hose_spinlock);
105 list_for_each_entry(hose, &hose_list, list_node) {
106 size = pcibios_io_size(hose);
107 if (address >= hose->io_base_virt &&
108 address < (hose->io_base_virt + size)) {
113 spin_unlock(&hose_spinlock);
117 unsigned long pci_address_to_pio(phys_addr_t address)
119 struct pci_controller *hose;
120 resource_size_t size;
121 unsigned long ret = ~0;
123 spin_lock(&hose_spinlock);
124 list_for_each_entry(hose, &hose_list, list_node) {
125 size = pcibios_io_size(hose);
126 if (address >= hose->io_base_phys &&
127 address < (hose->io_base_phys + size)) {
129 (unsigned long)hose->io_base_virt - _IO_BASE;
130 ret = base + (address - hose->io_base_phys);
134 spin_unlock(&hose_spinlock);
138 EXPORT_SYMBOL_GPL(pci_address_to_pio);
141 * Return the domain number for this bus.
143 int pci_domain_nr(struct pci_bus *bus)
145 struct pci_controller *hose = pci_bus_to_host(bus);
147 return hose->global_number;
149 EXPORT_SYMBOL(pci_domain_nr);
151 /* This routine is meant to be used early during boot, when the
152 * PCI bus numbers have not yet been assigned, and you need to
153 * issue PCI config cycles to an OF device.
154 * It could also be used to "fix" RTAS config cycles if you want
155 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
158 struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
161 struct pci_controller *hose, *tmp;
162 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
163 if (hose->dn == node)
170 static ssize_t pci_show_devspec(struct device *dev,
171 struct device_attribute *attr, char *buf)
173 struct pci_dev *pdev;
174 struct device_node *np;
176 pdev = to_pci_dev(dev);
177 np = pci_device_to_OF_node(pdev);
178 if (np == NULL || np->full_name == NULL)
180 return sprintf(buf, "%s", np->full_name);
182 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
184 /* Add sysfs properties */
185 int pcibios_add_platform_entries(struct pci_dev *pdev)
187 return device_create_file(&pdev->dev, &dev_attr_devspec);
190 void pcibios_set_master(struct pci_dev *dev)
192 /* No special bus mastering setup handling */
196 * Reads the interrupt pin to determine if interrupt is use by card.
197 * If the interrupt is used, then gets the interrupt line from the
198 * openfirmware and sets it in the pci_dev and pci_config line.
200 int pci_read_irq_line(struct pci_dev *pci_dev)
205 /* The current device-tree that iSeries generates from the HV
206 * PCI informations doesn't contain proper interrupt routing,
207 * and all the fallback would do is print out crap, so we
208 * don't attempt to resolve the interrupts here at all, some
209 * iSeries specific fixup does it.
211 * In the long run, we will hopefully fix the generated device-tree
214 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
217 memset(&oirq, 0xff, sizeof(oirq));
219 /* Try to get a mapping from the device-tree */
220 if (of_irq_map_pci(pci_dev, &oirq)) {
223 /* If that fails, lets fallback to what is in the config
224 * space and map that through the default controller. We
225 * also set the type to level low since that's what PCI
226 * interrupts are. If your platform does differently, then
227 * either provide a proper interrupt tree or don't use this
230 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
234 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
235 line == 0xff || line == 0) {
238 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
241 virq = irq_create_mapping(NULL, line);
243 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
245 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
246 oirq.size, oirq.specifier[0], oirq.specifier[1],
247 of_node_full_name(oirq.controller));
249 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
253 pr_debug(" Failed to map !\n");
257 pr_debug(" Mapped to linux irq %d\n", virq);
263 EXPORT_SYMBOL(pci_read_irq_line);
266 * Platform support for /proc/bus/pci/X/Y mmap()s,
267 * modelled on the sparc64 implementation by Dave Miller.
272 * Adjust vm_pgoff of VMA such that it is the physical page offset
273 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
275 * Basically, the user finds the base address for his device which he wishes
276 * to mmap. They read the 32-bit value from the config space base register,
277 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
278 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
280 * Returns negative error code on failure, zero on success.
282 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
283 resource_size_t *offset,
284 enum pci_mmap_state mmap_state)
286 struct pci_controller *hose = pci_bus_to_host(dev->bus);
287 unsigned long io_offset = 0;
291 return NULL; /* should never happen */
293 /* If memory, add on the PCI bridge address offset */
294 if (mmap_state == pci_mmap_mem) {
295 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
296 *offset += hose->pci_mem_offset;
298 res_bit = IORESOURCE_MEM;
300 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
301 *offset += io_offset;
302 res_bit = IORESOURCE_IO;
306 * Check that the offset requested corresponds to one of the
307 * resources of the device.
309 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
310 struct resource *rp = &dev->resource[i];
311 int flags = rp->flags;
313 /* treat ROM as memory (should be already) */
314 if (i == PCI_ROM_RESOURCE)
315 flags |= IORESOURCE_MEM;
317 /* Active and same type? */
318 if ((flags & res_bit) == 0)
321 /* In the range of this resource? */
322 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
325 /* found it! construct the final physical address */
326 if (mmap_state == pci_mmap_io)
327 *offset += hose->io_base_phys - io_offset;
335 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
338 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
340 enum pci_mmap_state mmap_state,
343 pgprot_t prot = protection;
345 /* Write combine is always 0 on non-memory space mappings. On
346 * memory space, if the user didn't pass 1, we check for a
347 * "prefetchable" resource. This is a bit hackish, but we use
348 * this to workaround the inability of /sysfs to provide a write
351 if (mmap_state != pci_mmap_mem)
353 else if (write_combine == 0) {
354 if (rp->flags & IORESOURCE_PREFETCH)
358 return pgprot_noncached(prot);
362 * This one is used by /dev/mem and fbdev who have no clue about the
363 * PCI device, it tries to find the PCI device first and calls the
366 pgprot_t pci_phys_mem_access_prot(struct file *file,
371 struct pci_dev *pdev = NULL;
372 struct resource *found = NULL;
373 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
376 if (page_is_ram(pfn))
379 prot = pgprot_noncached(prot);
380 for_each_pci_dev(pdev) {
381 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
382 struct resource *rp = &pdev->resource[i];
383 int flags = rp->flags;
385 /* Active and same type? */
386 if ((flags & IORESOURCE_MEM) == 0)
388 /* In the range of this resource? */
389 if (offset < (rp->start & PAGE_MASK) ||
399 if (found->flags & IORESOURCE_PREFETCH)
400 prot = pgprot_noncached_wc(prot);
404 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
405 (unsigned long long)offset, pgprot_val(prot));
411 * Perform the actual remap of the pages for a PCI device mapping, as
412 * appropriate for this architecture. The region in the process to map
413 * is described by vm_start and vm_end members of VMA, the base physical
414 * address is found in vm_pgoff.
415 * The pci device structure is provided so that architectures may make mapping
416 * decisions on a per-device or per-bus basis.
418 * Returns a negative error code on failure, zero on success.
420 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
421 enum pci_mmap_state mmap_state, int write_combine)
423 resource_size_t offset =
424 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
428 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
432 vma->vm_pgoff = offset >> PAGE_SHIFT;
433 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
435 mmap_state, write_combine);
437 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
438 vma->vm_end - vma->vm_start, vma->vm_page_prot);
443 /* This provides legacy IO read access on a bus */
444 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
446 unsigned long offset;
447 struct pci_controller *hose = pci_bus_to_host(bus);
448 struct resource *rp = &hose->io_resource;
451 /* Check if port can be supported by that bus. We only check
452 * the ranges of the PHB though, not the bus itself as the rules
453 * for forwarding legacy cycles down bridges are not our problem
454 * here. So if the host bridge supports it, we do it.
456 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
459 if (!(rp->flags & IORESOURCE_IO))
461 if (offset < rp->start || (offset + size) > rp->end)
463 addr = hose->io_base_virt + port;
467 *((u8 *)val) = in_8(addr);
472 *((u16 *)val) = in_le16(addr);
477 *((u32 *)val) = in_le32(addr);
483 /* This provides legacy IO write access on a bus */
484 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
486 unsigned long offset;
487 struct pci_controller *hose = pci_bus_to_host(bus);
488 struct resource *rp = &hose->io_resource;
491 /* Check if port can be supported by that bus. We only check
492 * the ranges of the PHB though, not the bus itself as the rules
493 * for forwarding legacy cycles down bridges are not our problem
494 * here. So if the host bridge supports it, we do it.
496 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
499 if (!(rp->flags & IORESOURCE_IO))
501 if (offset < rp->start || (offset + size) > rp->end)
503 addr = hose->io_base_virt + port;
505 /* WARNING: The generic code is idiotic. It gets passed a pointer
506 * to what can be a 1, 2 or 4 byte quantity and always reads that
507 * as a u32, which means that we have to correct the location of
508 * the data read within those 32 bits for size 1 and 2
512 out_8(addr, val >> 24);
517 out_le16(addr, val >> 16);
528 /* This provides legacy IO or memory mmap access on a bus */
529 int pci_mmap_legacy_page_range(struct pci_bus *bus,
530 struct vm_area_struct *vma,
531 enum pci_mmap_state mmap_state)
533 struct pci_controller *hose = pci_bus_to_host(bus);
534 resource_size_t offset =
535 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
536 resource_size_t size = vma->vm_end - vma->vm_start;
539 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
540 pci_domain_nr(bus), bus->number,
541 mmap_state == pci_mmap_mem ? "MEM" : "IO",
542 (unsigned long long)offset,
543 (unsigned long long)(offset + size - 1));
545 if (mmap_state == pci_mmap_mem) {
548 * Because X is lame and can fail starting if it gets an error
549 * trying to mmap legacy_mem (instead of just moving on without
550 * legacy memory access) we fake it here by giving it anonymous
551 * memory, effectively behaving just like /dev/zero
553 if ((offset + size) > hose->isa_mem_size) {
556 "Process %s (pid:%d) mapped non-existing PCI"
557 "legacy memory for 0%04x:%02x\n",
558 current->comm, current->pid, pci_domain_nr(bus),
561 if (vma->vm_flags & VM_SHARED)
562 return shmem_zero_setup(vma);
565 offset += hose->isa_mem_phys;
567 unsigned long io_offset = (unsigned long)hose->io_base_virt - \
569 unsigned long roffset = offset + io_offset;
570 rp = &hose->io_resource;
571 if (!(rp->flags & IORESOURCE_IO))
573 if (roffset < rp->start || (roffset + size) > rp->end)
575 offset += hose->io_base_phys;
577 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
579 vma->vm_pgoff = offset >> PAGE_SHIFT;
580 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
581 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
582 vma->vm_end - vma->vm_start,
586 void pci_resource_to_user(const struct pci_dev *dev, int bar,
587 const struct resource *rsrc,
588 resource_size_t *start, resource_size_t *end)
590 struct pci_controller *hose = pci_bus_to_host(dev->bus);
591 resource_size_t offset = 0;
596 if (rsrc->flags & IORESOURCE_IO)
597 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
599 /* We pass a fully fixed up address to userland for MMIO instead of
600 * a BAR value because X is lame and expects to be able to use that
601 * to pass to /dev/mem !
603 * That means that we'll have potentially 64 bits values where some
604 * userland apps only expect 32 (like X itself since it thinks only
605 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
608 * Hopefully, the sysfs insterface is immune to that gunk. Once X
609 * has been fixed (and the fix spread enough), we can re-enable the
610 * 2 lines below and pass down a BAR value to userland. In that case
611 * we'll also have to re-enable the matching code in
612 * __pci_mmap_make_offset().
617 else if (rsrc->flags & IORESOURCE_MEM)
618 offset = hose->pci_mem_offset;
621 *start = rsrc->start - offset;
622 *end = rsrc->end - offset;
626 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
627 * @hose: newly allocated pci_controller to be setup
628 * @dev: device node of the host bridge
629 * @primary: set if primary bus (32 bits only, soon to be deprecated)
631 * This function will parse the "ranges" property of a PCI host bridge device
632 * node and setup the resource mapping of a pci controller based on its
635 * Life would be boring if it wasn't for a few issues that we have to deal
638 * - We can only cope with one IO space range and up to 3 Memory space
639 * ranges. However, some machines (thanks Apple !) tend to split their
640 * space into lots of small contiguous ranges. So we have to coalesce.
642 * - We can only cope with all memory ranges having the same offset
643 * between CPU addresses and PCI addresses. Unfortunately, some bridges
644 * are setup for a large 1:1 mapping along with a small "window" which
645 * maps PCI address 0 to some arbitrary high address of the CPU space in
646 * order to give access to the ISA memory hole.
647 * The way out of here that I've chosen for now is to always set the
648 * offset based on the first resource found, then override it if we
649 * have a different offset and the previous was set by an ISA hole.
651 * - Some busses have IO space not starting at 0, which causes trouble with
652 * the way we do our IO resource renumbering. The code somewhat deals with
653 * it for 64 bits but I would expect problems on 32 bits.
655 * - Some 32 bits platforms such as 4xx can have physical space larger than
656 * 32 bits so we need to use 64 bits values for the parsing
658 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
659 struct device_node *dev, int primary)
663 int pna = of_n_addr_cells(dev);
665 int memno = 0, isa_hole = -1;
667 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
668 unsigned long long isa_mb = 0;
669 struct resource *res;
671 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
672 dev->full_name, primary ? "(primary)" : "");
674 /* Get ranges property */
675 ranges = of_get_property(dev, "ranges", &rlen);
680 pr_debug("Parsing ranges property...\n");
681 while ((rlen -= np * 4) >= 0) {
682 /* Read next ranges element */
683 pci_space = ranges[0];
684 pci_addr = of_read_number(ranges + 1, 2);
685 cpu_addr = of_translate_address(dev, ranges + 3);
686 size = of_read_number(ranges + pna + 3, 2);
688 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx "
689 "cpu_addr:0x%016llx size:0x%016llx\n",
690 pci_space, pci_addr, cpu_addr, size);
694 /* If we failed translation or got a zero-sized region
695 * (some FW try to feed us with non sensical zero sized regions
696 * such as power3 which look like some kind of attempt
697 * at exposing the VGA memory hole)
699 if (cpu_addr == OF_BAD_ADDR || size == 0)
702 /* Now consume following elements while they are contiguous */
703 for (; rlen >= np * sizeof(u32);
704 ranges += np, rlen -= np * 4) {
705 if (ranges[0] != pci_space)
707 pci_next = of_read_number(ranges + 1, 2);
708 cpu_next = of_translate_address(dev, ranges + 3);
709 if (pci_next != pci_addr + size ||
710 cpu_next != cpu_addr + size)
712 size += of_read_number(ranges + pna + 3, 2);
715 /* Act based on address space type */
717 switch ((pci_space >> 24) & 0x3) {
718 case 1: /* PCI IO space */
720 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
721 cpu_addr, cpu_addr + size - 1, pci_addr);
723 /* We support only one IO range */
724 if (hose->pci_io_size) {
726 " \\--> Skipped (too many) !\n");
729 /* On 32 bits, limit I/O space to 16MB */
730 if (size > 0x01000000)
733 /* 32 bits needs to map IOs here */
734 hose->io_base_virt = ioremap(cpu_addr, size);
736 /* Expect trouble if pci_addr is not 0 */
739 (unsigned long)hose->io_base_virt;
740 /* pci_io_size and io_base_phys always represent IO
741 * space starting at 0 so we factor in pci_addr
743 hose->pci_io_size = pci_addr + size;
744 hose->io_base_phys = cpu_addr - pci_addr;
747 res = &hose->io_resource;
748 res->flags = IORESOURCE_IO;
749 res->start = pci_addr;
751 case 2: /* PCI Memory space */
752 case 3: /* PCI 64 bits Memory space */
754 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
755 cpu_addr, cpu_addr + size - 1, pci_addr,
756 (pci_space & 0x40000000) ? "Prefetch" : "");
758 /* We support only 3 memory ranges */
761 " \\--> Skipped (too many) !\n");
764 /* Handles ISA memory hole space here */
768 if (primary || isa_mem_base == 0)
769 isa_mem_base = cpu_addr;
770 hose->isa_mem_phys = cpu_addr;
771 hose->isa_mem_size = size;
774 /* We get the PCI/Mem offset from the first range or
775 * the, current one if the offset came from an ISA
776 * hole. If they don't match, bugger.
779 (isa_hole >= 0 && pci_addr != 0 &&
780 hose->pci_mem_offset == isa_mb))
781 hose->pci_mem_offset = cpu_addr - pci_addr;
782 else if (pci_addr != 0 &&
783 hose->pci_mem_offset != cpu_addr - pci_addr) {
785 " \\--> Skipped (offset mismatch) !\n");
790 res = &hose->mem_resources[memno++];
791 res->flags = IORESOURCE_MEM;
792 if (pci_space & 0x40000000)
793 res->flags |= IORESOURCE_PREFETCH;
794 res->start = cpu_addr;
798 res->name = dev->full_name;
799 res->end = res->start + size - 1;
806 /* If there's an ISA hole and the pci_mem_offset is -not- matching
807 * the ISA hole offset, then we need to remove the ISA hole from
808 * the resource list for that brige
810 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
811 unsigned int next = isa_hole + 1;
812 printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb);
814 memmove(&hose->mem_resources[isa_hole],
815 &hose->mem_resources[next],
816 sizeof(struct resource) * (memno - next));
817 hose->mem_resources[--memno].flags = 0;
821 /* Decide whether to display the domain number in /proc */
822 int pci_proc_domain(struct pci_bus *bus)
827 /* This header fixup will do the resource fixup for all devices as they are
828 * probed, but not for bridge ranges
830 static void pcibios_fixup_resources(struct pci_dev *dev)
832 struct pci_controller *hose = pci_bus_to_host(dev->bus);
836 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
840 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
841 struct resource *res = dev->resource + i;
844 if (res->start == 0) {
845 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]" \
848 (unsigned long long)res->start,
849 (unsigned long long)res->end,
850 (unsigned int)res->flags);
851 res->end -= res->start;
853 res->flags |= IORESOURCE_UNSET;
857 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
859 (unsigned long long)res->start,\
860 (unsigned long long)res->end,
861 (unsigned int)res->flags);
864 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
866 /* This function tries to figure out if a bridge resource has been initialized
867 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
868 * things go more smoothly when it gets it right. It should covers cases such
869 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
871 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
872 struct resource *res)
874 struct pci_controller *hose = pci_bus_to_host(bus);
875 struct pci_dev *dev = bus->self;
876 resource_size_t offset;
880 /* Job is a bit different between memory and IO */
881 if (res->flags & IORESOURCE_MEM) {
882 /* If the BAR is non-0 (res != pci_mem_offset) then it's
883 * probably been initialized by somebody
885 if (res->start != hose->pci_mem_offset)
888 /* The BAR is 0, let's check if memory decoding is enabled on
889 * the bridge. If not, we consider it unassigned
891 pci_read_config_word(dev, PCI_COMMAND, &command);
892 if ((command & PCI_COMMAND_MEMORY) == 0)
895 /* Memory decoding is enabled and the BAR is 0. If any of
896 * the bridge resources covers that starting address (0 then
897 * it's good enough for us for memory
899 for (i = 0; i < 3; i++) {
900 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
901 hose->mem_resources[i].start == hose->pci_mem_offset)
905 /* Well, it starts at 0 and we know it will collide so we may as
906 * well consider it as unassigned. That covers the Apple case.
910 /* If the BAR is non-0, then we consider it assigned */
911 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
912 if (((res->start - offset) & 0xfffffffful) != 0)
915 /* Here, we are a bit different than memory as typically IO
916 * space starting at low addresses -is- valid. What we do
917 * instead if that we consider as unassigned anything that
918 * doesn't have IO enabled in the PCI command register,
921 pci_read_config_word(dev, PCI_COMMAND, &command);
922 if (command & PCI_COMMAND_IO)
925 /* It's starting at 0 and IO is disabled in the bridge, consider
932 /* Fixup resources of a PCI<->PCI bridge */
933 static void pcibios_fixup_bridge(struct pci_bus *bus)
935 struct resource *res;
938 struct pci_dev *dev = bus->self;
940 pci_bus_for_each_resource(bus, res, i) {
945 if (i >= 3 && bus->self->transparent)
948 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
950 (unsigned long long)res->start,\
951 (unsigned long long)res->end,
952 (unsigned int)res->flags);
954 /* Try to detect uninitialized P2P bridge resources,
955 * and clear them out so they get re-assigned later
957 if (pcibios_uninitialized_bridge_resource(bus, res)) {
959 pr_debug("PCI:%s (unassigned)\n",
962 pr_debug("PCI:%s %016llx-%016llx\n",
964 (unsigned long long)res->start,
965 (unsigned long long)res->end);
970 void pcibios_setup_bus_self(struct pci_bus *bus)
972 /* Fix up the bus resources for P2P bridges */
973 if (bus->self != NULL)
974 pcibios_fixup_bridge(bus);
977 void pcibios_setup_bus_devices(struct pci_bus *bus)
981 pr_debug("PCI: Fixup bus devices %d (%s)\n",
982 bus->number, bus->self ? pci_name(bus->self) : "PHB");
984 list_for_each_entry(dev, &bus->devices, bus_list) {
985 /* Setup OF node pointer in archdata */
986 dev->dev.of_node = pci_device_to_OF_node(dev);
988 /* Fixup NUMA node as it may not be setup yet by the generic
989 * code and is needed by the DMA init
991 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
993 /* Hook up default DMA ops */
994 set_dma_ops(&dev->dev, pci_dma_ops);
995 dev->dev.archdata.dma_data = (void *)PCI_DRAM_OFFSET;
997 /* Read default IRQs and fixup if necessary */
998 pci_read_irq_line(dev);
1002 void pcibios_fixup_bus(struct pci_bus *bus)
1004 /* When called from the generic PCI probe, read PCI<->PCI bridge
1005 * bases. This is -not- called when generating the PCI tree from
1006 * the OF device-tree.
1008 if (bus->self != NULL)
1009 pci_read_bridge_bases(bus);
1011 /* Now fixup the bus bus */
1012 pcibios_setup_bus_self(bus);
1014 /* Now fixup devices on that bus */
1015 pcibios_setup_bus_devices(bus);
1017 EXPORT_SYMBOL(pcibios_fixup_bus);
1019 static int skip_isa_ioresource_align(struct pci_dev *dev)
1025 * We need to avoid collisions with `mirrored' VGA ports
1026 * and other strange ISA hardware, so we always want the
1027 * addresses to be allocated in the 0x000-0x0ff region
1030 * Why? Because some silly external IO cards only decode
1031 * the low 10 bits of the IO address. The 0x00-0xff region
1032 * is reserved for motherboard devices that decode all 16
1033 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1034 * but we want to try to avoid allocating at 0x2900-0x2bff
1035 * which might have be mirrored at 0x0100-0x03ff..
1037 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1038 resource_size_t size, resource_size_t align)
1040 struct pci_dev *dev = data;
1041 resource_size_t start = res->start;
1043 if (res->flags & IORESOURCE_IO) {
1044 if (skip_isa_ioresource_align(dev))
1047 start = (start + 0x3ff) & ~0x3ff;
1052 EXPORT_SYMBOL(pcibios_align_resource);
1055 * Reparent resource children of pr that conflict with res
1056 * under res, and make res replace those children.
1058 static int __init reparent_resources(struct resource *parent,
1059 struct resource *res)
1061 struct resource *p, **pp;
1062 struct resource **firstpp = NULL;
1064 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1065 if (p->end < res->start)
1067 if (res->end < p->start)
1069 if (p->start < res->start || p->end > res->end)
1070 return -1; /* not completely contained */
1071 if (firstpp == NULL)
1074 if (firstpp == NULL)
1075 return -1; /* didn't find any conflicting entries? */
1076 res->parent = parent;
1077 res->child = *firstpp;
1081 for (p = res->child; p != NULL; p = p->sibling) {
1083 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1085 (unsigned long long)p->start,
1086 (unsigned long long)p->end, res->name);
1092 * Handle resources of PCI devices. If the world were perfect, we could
1093 * just allocate all the resource regions and do nothing more. It isn't.
1094 * On the other hand, we cannot just re-allocate all devices, as it would
1095 * require us to know lots of host bridge internals. So we attempt to
1096 * keep as much of the original configuration as possible, but tweak it
1097 * when it's found to be wrong.
1099 * Known BIOS problems we have to work around:
1100 * - I/O or memory regions not configured
1101 * - regions configured, but not enabled in the command register
1102 * - bogus I/O addresses above 64K used
1103 * - expansion ROMs left enabled (this may sound harmless, but given
1104 * the fact the PCI specs explicitly allow address decoders to be
1105 * shared between expansion ROMs and other resource regions, it's
1106 * at least dangerous)
1109 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1110 * This gives us fixed barriers on where we can allocate.
1111 * (2) Allocate resources for all enabled devices. If there is
1112 * a collision, just mark the resource as unallocated. Also
1113 * disable expansion ROMs during this step.
1114 * (3) Try to allocate resources for disabled devices. If the
1115 * resources were assigned correctly, everything goes well,
1116 * if they weren't, they won't disturb allocation of other
1118 * (4) Assign new addresses to resources which were either
1119 * not configured at all or misconfigured. If explicitly
1120 * requested by the user, configure expansion ROM address
1124 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1128 struct resource *res, *pr;
1130 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1131 pci_domain_nr(bus), bus->number);
1133 pci_bus_for_each_resource(bus, res, i) {
1134 if (!res || !res->flags
1135 || res->start > res->end || res->parent)
1137 if (bus->parent == NULL)
1138 pr = (res->flags & IORESOURCE_IO) ?
1139 &ioport_resource : &iomem_resource;
1141 /* Don't bother with non-root busses when
1142 * re-assigning all resources. We clear the
1143 * resource flags as if they were colliding
1144 * and as such ensure proper re-allocation
1147 pr = pci_find_parent_resource(bus->self, res);
1149 /* this happens when the generic PCI
1150 * code (wrongly) decides that this
1151 * bridge is transparent -- paulus
1157 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1158 "[0x%x], parent %p (%s)\n",
1159 bus->self ? pci_name(bus->self) : "PHB",
1161 (unsigned long long)res->start,
1162 (unsigned long long)res->end,
1163 (unsigned int)res->flags,
1164 pr, (pr && pr->name) ? pr->name : "nil");
1166 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1167 if (request_resource(pr, res) == 0)
1170 * Must be a conflict with an existing entry.
1171 * Move that entry (or entries) under the
1172 * bridge resource and try again.
1174 if (reparent_resources(pr, res) == 0)
1177 printk(KERN_WARNING "PCI: Cannot allocate resource region "
1178 "%d of PCI bridge %d, will remap\n", i, bus->number);
1180 res->start = res->end = 0;
1184 list_for_each_entry(b, &bus->children, node)
1185 pcibios_allocate_bus_resources(b);
1188 static inline void alloc_resource(struct pci_dev *dev, int idx)
1190 struct resource *pr, *r = &dev->resource[idx];
1192 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1194 (unsigned long long)r->start,
1195 (unsigned long long)r->end,
1196 (unsigned int)r->flags);
1198 pr = pci_find_parent_resource(dev, r);
1199 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1200 request_resource(pr, r) < 0) {
1201 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1202 " of device %s, will remap\n", idx, pci_name(dev));
1204 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1206 (unsigned long long)pr->start,
1207 (unsigned long long)pr->end,
1208 (unsigned int)pr->flags);
1209 /* We'll assign a new address later */
1210 r->flags |= IORESOURCE_UNSET;
1216 static void __init pcibios_allocate_resources(int pass)
1218 struct pci_dev *dev = NULL;
1223 for_each_pci_dev(dev) {
1224 pci_read_config_word(dev, PCI_COMMAND, &command);
1225 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1226 r = &dev->resource[idx];
1227 if (r->parent) /* Already allocated */
1229 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1230 continue; /* Not assigned at all */
1231 /* We only allocate ROMs on pass 1 just in case they
1232 * have been screwed up by firmware
1234 if (idx == PCI_ROM_RESOURCE)
1236 if (r->flags & IORESOURCE_IO)
1237 disabled = !(command & PCI_COMMAND_IO);
1239 disabled = !(command & PCI_COMMAND_MEMORY);
1240 if (pass == disabled)
1241 alloc_resource(dev, idx);
1245 r = &dev->resource[PCI_ROM_RESOURCE];
1247 /* Turn the ROM off, leave the resource region,
1248 * but keep it unregistered.
1251 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1252 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1253 pr_debug("PCI: Switching off ROM of %s\n",
1255 r->flags &= ~IORESOURCE_ROM_ENABLE;
1256 pci_write_config_dword(dev, dev->rom_base_reg,
1257 reg & ~PCI_ROM_ADDRESS_ENABLE);
1263 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1265 struct pci_controller *hose = pci_bus_to_host(bus);
1266 resource_size_t offset;
1267 struct resource *res, *pres;
1270 pr_debug("Reserving legacy ranges for domain %04x\n",
1271 pci_domain_nr(bus));
1274 if (!(hose->io_resource.flags & IORESOURCE_IO))
1276 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1277 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1278 BUG_ON(res == NULL);
1279 res->name = "Legacy IO";
1280 res->flags = IORESOURCE_IO;
1281 res->start = offset;
1282 res->end = (offset + 0xfff) & 0xfffffffful;
1283 pr_debug("Candidate legacy IO: %pR\n", res);
1284 if (request_resource(&hose->io_resource, res)) {
1286 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1287 pci_domain_nr(bus), bus->number, res);
1292 /* Check for memory */
1293 offset = hose->pci_mem_offset;
1294 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
1295 for (i = 0; i < 3; i++) {
1296 pres = &hose->mem_resources[i];
1297 if (!(pres->flags & IORESOURCE_MEM))
1299 pr_debug("hose mem res: %pR\n", pres);
1300 if ((pres->start - offset) <= 0xa0000 &&
1301 (pres->end - offset) >= 0xbffff)
1306 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1307 BUG_ON(res == NULL);
1308 res->name = "Legacy VGA memory";
1309 res->flags = IORESOURCE_MEM;
1310 res->start = 0xa0000 + offset;
1311 res->end = 0xbffff + offset;
1312 pr_debug("Candidate VGA memory: %pR\n", res);
1313 if (request_resource(pres, res)) {
1315 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1316 pci_domain_nr(bus), bus->number, res);
1321 void __init pcibios_resource_survey(void)
1325 /* Allocate and assign resources. If we re-assign everything, then
1326 * we skip the allocate phase
1328 list_for_each_entry(b, &pci_root_buses, node)
1329 pcibios_allocate_bus_resources(b);
1331 pcibios_allocate_resources(0);
1332 pcibios_allocate_resources(1);
1334 /* Before we start assigning unassigned resource, we try to reserve
1335 * the low IO area and the VGA memory area if they intersect the
1336 * bus available resources to avoid allocating things on top of them
1338 list_for_each_entry(b, &pci_root_buses, node)
1339 pcibios_reserve_legacy_regions(b);
1341 /* Now proceed to assigning things that were left unassigned */
1342 pr_debug("PCI: Assigning unassigned resources...\n");
1343 pci_assign_unassigned_resources();
1346 /* This is used by the PCI hotplug driver to allocate resource
1347 * of newly plugged busses. We can try to consolidate with the
1348 * rest of the code later, for now, keep it as-is as our main
1349 * resource allocation function doesn't deal with sub-trees yet.
1351 void pcibios_claim_one_bus(struct pci_bus *bus)
1353 struct pci_dev *dev;
1354 struct pci_bus *child_bus;
1356 list_for_each_entry(dev, &bus->devices, bus_list) {
1359 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1360 struct resource *r = &dev->resource[i];
1362 if (r->parent || !r->start || !r->flags)
1365 pr_debug("PCI: Claiming %s: "
1366 "Resource %d: %016llx..%016llx [%x]\n",
1368 (unsigned long long)r->start,
1369 (unsigned long long)r->end,
1370 (unsigned int)r->flags);
1372 pci_claim_resource(dev, i);
1376 list_for_each_entry(child_bus, &bus->children, node)
1377 pcibios_claim_one_bus(child_bus);
1379 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1382 /* pcibios_finish_adding_to_bus
1384 * This is to be called by the hotplug code after devices have been
1385 * added to a bus, this include calling it for a PHB that is just
1388 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1390 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1391 pci_domain_nr(bus), bus->number);
1393 /* Allocate bus and devices resources */
1394 pcibios_allocate_bus_resources(bus);
1395 pcibios_claim_one_bus(bus);
1397 /* Add new devices to global lists. Register in proc, sysfs. */
1398 pci_bus_add_devices(bus);
1401 /* eeh_add_device_tree_late(bus); */
1403 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1405 int pcibios_enable_device(struct pci_dev *dev, int mask)
1407 return pci_enable_resources(dev, mask);
1410 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1411 struct list_head *resources)
1413 unsigned long io_offset;
1414 struct resource *res;
1417 /* Hookup PHB IO resource */
1418 res = &hose->io_resource;
1420 /* Fixup IO space offset */
1421 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1422 res->start = (res->start + io_offset) & 0xffffffffu;
1423 res->end = (res->end + io_offset) & 0xffffffffu;
1426 printk(KERN_WARNING "PCI: I/O resource not set for host"
1427 " bridge %s (domain %d)\n",
1428 hose->dn->full_name, hose->global_number);
1429 /* Workaround for lack of IO resource only on 32-bit */
1430 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1431 res->end = res->start + IO_SPACE_LIMIT;
1432 res->flags = IORESOURCE_IO;
1434 pci_add_resource_offset(resources, res,
1435 (__force resource_size_t)(hose->io_base_virt - _IO_BASE));
1437 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1438 (unsigned long long)res->start,
1439 (unsigned long long)res->end,
1440 (unsigned long)res->flags);
1442 /* Hookup PHB Memory resources */
1443 for (i = 0; i < 3; ++i) {
1444 res = &hose->mem_resources[i];
1448 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1449 "host bridge %s (domain %d)\n",
1450 hose->dn->full_name, hose->global_number);
1452 /* Workaround for lack of MEM resource only on 32-bit */
1453 res->start = hose->pci_mem_offset;
1454 res->end = (resource_size_t)-1LL;
1455 res->flags = IORESOURCE_MEM;
1458 pci_add_resource_offset(resources, res, hose->pci_mem_offset);
1460 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1461 i, (unsigned long long)res->start,
1462 (unsigned long long)res->end,
1463 (unsigned long)res->flags);
1466 pr_debug("PCI: PHB MEM offset = %016llx\n",
1467 (unsigned long long)hose->pci_mem_offset);
1468 pr_debug("PCI: PHB IO offset = %08lx\n",
1469 (unsigned long)hose->io_base_virt - _IO_BASE);
1472 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1474 struct pci_controller *hose = bus->sysdata;
1476 return of_node_get(hose->dn);
1479 static void pcibios_scan_phb(struct pci_controller *hose)
1481 LIST_HEAD(resources);
1482 struct pci_bus *bus;
1483 struct device_node *node = hose->dn;
1485 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1487 pcibios_setup_phb_resources(hose, &resources);
1489 bus = pci_scan_root_bus(hose->parent, hose->first_busno,
1490 hose->ops, hose, &resources);
1492 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
1493 hose->global_number);
1494 pci_free_resource_list(&resources);
1497 bus->busn_res.start = hose->first_busno;
1500 hose->last_busno = bus->busn_res.end;
1503 static int __init pcibios_init(void)
1505 struct pci_controller *hose, *tmp;
1508 printk(KERN_INFO "PCI: Probing PCI hardware\n");
1510 /* Scan all of the recorded PCI controllers. */
1511 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1512 hose->last_busno = 0xff;
1513 pcibios_scan_phb(hose);
1514 if (next_busno <= hose->last_busno)
1515 next_busno = hose->last_busno + 1;
1517 pci_bus_count = next_busno;
1519 /* Call common code to handle resource allocation */
1520 pcibios_resource_survey();
1525 subsys_initcall(pcibios_init);
1527 static struct pci_controller *pci_bus_to_hose(int bus)
1529 struct pci_controller *hose, *tmp;
1531 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1532 if (bus >= hose->first_busno && bus <= hose->last_busno)
1537 /* Provide information on locations of various I/O regions in physical
1538 * memory. Do this on a per-card basis so that we choose the right
1540 * Note that the returned IO or memory base is a physical address
1543 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1545 struct pci_controller *hose;
1546 long result = -EOPNOTSUPP;
1548 hose = pci_bus_to_hose(bus);
1553 case IOBASE_BRIDGE_NUMBER:
1554 return (long)hose->first_busno;
1556 return (long)hose->pci_mem_offset;
1558 return (long)hose->io_base_phys;
1560 return (long)isa_io_base;
1561 case IOBASE_ISA_MEM:
1562 return (long)isa_mem_base;
1569 * Null PCI config access functions, for the case when we can't
1572 #define NULL_PCI_OP(rw, size, type) \
1574 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1576 return PCIBIOS_DEVICE_NOT_FOUND; \
1580 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1583 return PCIBIOS_DEVICE_NOT_FOUND;
1587 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1590 return PCIBIOS_DEVICE_NOT_FOUND;
1593 static struct pci_ops null_pci_ops = {
1594 .read = null_read_config,
1595 .write = null_write_config,
1599 * These functions are used early on before PCI scanning is done
1600 * and all of the pci_dev and pci_bus structures have been created.
1602 static struct pci_bus *
1603 fake_pci_bus(struct pci_controller *hose, int busnr)
1605 static struct pci_bus bus;
1608 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1612 bus.ops = hose ? hose->ops : &null_pci_ops;
1616 #define EARLY_PCI_OP(rw, size, type) \
1617 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1618 int devfn, int offset, type value) \
1620 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1621 devfn, offset, value); \
1624 EARLY_PCI_OP(read, byte, u8 *)
1625 EARLY_PCI_OP(read, word, u16 *)
1626 EARLY_PCI_OP(read, dword, u32 *)
1627 EARLY_PCI_OP(write, byte, u8)
1628 EARLY_PCI_OP(write, word, u16)
1629 EARLY_PCI_OP(write, dword, u32)
1631 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1634 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);