1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2007 Michal Simek
4 * (C) Copyright 2004 Atmark Techno, Inc.
6 * Michal SIMEK <monstr@monstr.eu>
7 * Yasushi SHOJI <yashi@atmark-techno.com>
10 #include <asm-offsets.h>
16 mts rmsr, r0 /* disable cache */
21 #if defined(CONFIG_SPL_BUILD)
22 addi r1, r0, CONFIG_SPL_STACK_ADDR
24 addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
27 addi r1, r1, -4 /* Decrement SP to top of memory */
29 /* Call board_init_f_alloc_reserve with the current stack pointer as
32 bralid r15, board_init_f_alloc_reserve
35 /* board_init_f_alloc_reserve returns a pointer to the allocated area
36 * in r3. Set the new stack pointer below this area. */
41 /* Call board_init_f_init_reserve with the address returned by
42 * board_init_f_alloc_reserve as parameter. */
44 bralid r15, board_init_f_init_reserve
47 #if !defined(CONFIG_SPL_BUILD)
48 /* Setup vectors with pre-relocation symbols */
50 bralid r15, __setup_exceptions
54 /* Flush cache before enable cache */
56 addik r6, r0, XILINX_DCACHE_BYTE_SIZE
57 bralid r15, flush_cache
60 /* enable instruction and data cache */
66 /* clear BSS segments */
67 addi r5, r0, __bss_start
68 addi r4, r0, __bss_end
72 swi r0, r5, 0 /* write zero to loc */
73 addi r5, r5, 4 /* increment to next loc */
74 cmp r6, r5, r4 /* check if we have reach the end */
76 3: /* jumping to board_init */
77 #ifdef CONFIG_DEBUG_UART
78 bralid r15, debug_uart_init
81 #ifndef CONFIG_SPL_BUILD
82 or r5, r0, r0 /* flags - empty */
89 #ifndef CONFIG_SPL_BUILD
91 .ent __setup_exceptions
94 * Set up reset, interrupt, user exception and hardware exception vectors.
97 * r5 - relocation offset (zero when setting up vectors before
98 * relocation, and gd->reloc_off when setting up vectors after
100 * - the relocation offset is added to the _exception_handler,
101 * _interrupt_handler and _hw_exception_handler symbols to reflect the
102 * post-relocation memory addresses
105 * r10: Stores little/big endian offset for vectors
106 * r2: Stores imm opcode
107 * r3: Stores brai opcode
108 * r4: Stores the vector base address
120 /* Find-out if u-boot is running on BIG/LITTLE endian platform
121 * There are some steps which is necessary to keep in mind:
122 * 1. Setup offset value to r6
123 * 2. Store word offset value to address 0x0
124 * 3. Load just byte from address 0x0
125 * 4a) LITTLE endian - r10 contains 0x2 because it is the smallest
126 * value that's why is on address 0x0
127 * 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3
129 addik r6, r0, 0x2 /* BIG/LITTLE endian offset */
133 /* add opcode instruction for 32bit jump - 2 instruction imm & brai */
134 addi r2, r0, 0xb0000000 /* hex b000 opcode imm */
135 addi r3, r0, 0xb8080000 /* hew b808 opcode brai */
137 /* Store the vector base address in r4 */
138 addi r4, r0, CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR
141 swi r2, r4, 0x0 /* reset address - imm opcode */
142 swi r3, r4, 0x4 /* reset address - brai opcode */
144 addik r6, r0, CONFIG_SYS_TEXT_BASE
152 #if CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USR_EXCEP)
153 /* user_vector_exception */
154 swi r2, r4, 0x8 /* user vector exception - imm opcode */
155 swi r3, r4, 0xC /* user vector exception - brai opcode */
157 addik r6, r5, _exception_handler
160 * BIG ENDIAN memory map for user exception
164 * then it is necessary to count address for storing the most significant
165 * 16bits from _exception_handler address and copy it to
166 * 0xa address. Big endian use offset in r10=0 that's why is it just
167 * 0xa address. The same is done for the least significant 16 bits
170 * LITTLE ENDIAN memory map for user exception
174 * Offset is for little endian setup to 0x2. rsubi instruction decrease
175 * address value to ensure that points to proper place which is
176 * 0x8 for the most significant 16 bits and
177 * 0xC for the least significant 16 bits
186 /* interrupt_handler */
187 swi r2, r4, 0x10 /* interrupt - imm opcode */
188 swi r3, r4, 0x14 /* interrupt - brai opcode */
190 addik r6, r5, _interrupt_handler
198 /* hardware exception */
199 swi r2, r4, 0x20 /* hardware exception - imm opcode */
200 swi r3, r4, 0x24 /* hardware exception - brai opcode */
202 addik r6, r5, _hw_exception_handler
221 .end __setup_exceptions
224 * Read 16bit little endian
240 * Write 16bit little endian
241 * first parameter(r5) - address, second(r6) - short value
247 out16: bslli r3, r6, 8
260 .global relocate_code
269 addi r1, r5, 0 /* Start to use new SP */
270 addi r31, r6, 0 /* Start to use new GD */
272 add r23, r0, r7 /* Move reloc addr to r23 */
273 /* Relocate text and data - r12 temp value */
275 addi r22, r0, _end - 4 /* Include BSS too */
279 1: lw r12, r21, r5 /* Load u-boot data */
280 sw r12, r23, r5 /* Write zero to loc */
281 cmp r12, r5, r6 /* Check if we have reach the end */
283 addi r5, r5, 4 /* Increment to next loc - relocate code */
285 /* R23 points to the base address. */
286 add r23, r0, r7 /* Move reloc addr to r23 */
287 addi r24, r0, CONFIG_SYS_TEXT_BASE /* Get reloc offset */
288 rsub r23, r24, r23 /* keep - this is already here gd->reloc_off */
290 /* Setup vectors with post-relocation symbols */
291 add r5, r0, r23 /* load gd->reloc_off to r5 */
292 bralid r15, __setup_exceptions
295 /* Check if GOT exist */
296 addik r21, r23, _got_start
297 addik r22, r23, _got_end
299 beqi r12, 2f /* No GOT table - jump over */
301 /* Skip last 3 entries plus 1 because of loop boundary below */
302 addik r22, r22, -0x10
304 /* Relocate the GOT. */
305 3: lw r12, r21, r0 /* Load entry */
306 addk r12, r12, r23 /* Add reloc offset */
307 sw r12, r21, r0 /* Save entry back */
309 cmpu r12, r21, r22 /* Check if this cross boundary */
313 /* Update pointer to GOT */
315 addik r20, r20, _GLOBAL_OFFSET_TABLE_ + 8
318 /* Flush caches to ensure consistency */
320 addik r6, r0, XILINX_DCACHE_BYTE_SIZE
321 bralid r15, flush_cache
324 2: addi r5, r31, 0 /* gd is initialized in board_r.c */
325 addi r6, r0, CONFIG_SYS_TEXT_BASE
326 addi r12, r23, board_init_r
327 bra r12 /* Jump to relocated code */