1 /***************************************************************************/
4 * linux/arch/m68knommu/platform/532x/config.c
6 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
7 * Copyright (C) 2000, Lineo (www.lineo.com)
8 * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
9 * Copyright Freescale Semiconductor, Inc 2006
10 * Copyright (c) 2006, emlix, Sebastian Hess <sh@emlix.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
18 /***************************************************************************/
20 #include <linux/kernel.h>
21 #include <linux/param.h>
22 #include <linux/init.h>
24 #include <linux/spi/spi.h>
25 #include <linux/gpio.h>
26 #include <asm/machdep.h>
27 #include <asm/coldfire.h>
28 #include <asm/mcfsim.h>
29 #include <asm/mcfuart.h>
30 #include <asm/mcfdma.h>
31 #include <asm/mcfwdebug.h>
32 #include <asm/mcfqspi.h>
34 /***************************************************************************/
36 static struct mcf_platform_uart m532x_uart_platform[] = {
38 .mapbase = MCFUART_BASE1,
39 .irq = MCFINT_VECBASE + MCFINT_UART0,
42 .mapbase = MCFUART_BASE2,
43 .irq = MCFINT_VECBASE + MCFINT_UART1,
46 .mapbase = MCFUART_BASE3,
47 .irq = MCFINT_VECBASE + MCFINT_UART2,
52 static struct platform_device m532x_uart = {
55 .dev.platform_data = m532x_uart_platform,
58 static struct resource m532x_fec_resources[] = {
62 .flags = IORESOURCE_MEM,
67 .flags = IORESOURCE_IRQ,
72 .flags = IORESOURCE_IRQ,
77 .flags = IORESOURCE_IRQ,
81 static struct platform_device m532x_fec = {
84 .num_resources = ARRAY_SIZE(m532x_fec_resources),
85 .resource = m532x_fec_resources,
88 #if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
89 static struct resource m532x_qspi_resources[] = {
91 .start = MCFQSPI_IOBASE,
92 .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
93 .flags = IORESOURCE_MEM,
96 .start = MCFINT_VECBASE + MCFINT_QSPI,
97 .end = MCFINT_VECBASE + MCFINT_QSPI,
98 .flags = IORESOURCE_IRQ,
102 #define MCFQSPI_CS0 84
103 #define MCFQSPI_CS1 85
104 #define MCFQSPI_CS2 86
106 static int m532x_cs_setup(struct mcfqspi_cs_control *cs_control)
110 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
112 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
115 status = gpio_direction_output(MCFQSPI_CS0, 1);
117 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
121 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
123 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
126 status = gpio_direction_output(MCFQSPI_CS1, 1);
128 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
132 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
134 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
137 status = gpio_direction_output(MCFQSPI_CS2, 1);
139 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
146 gpio_free(MCFQSPI_CS2);
148 gpio_free(MCFQSPI_CS1);
150 gpio_free(MCFQSPI_CS0);
155 static void m532x_cs_teardown(struct mcfqspi_cs_control *cs_control)
157 gpio_free(MCFQSPI_CS2);
158 gpio_free(MCFQSPI_CS1);
159 gpio_free(MCFQSPI_CS0);
162 static void m532x_cs_select(struct mcfqspi_cs_control *cs_control,
163 u8 chip_select, bool cs_high)
165 gpio_set_value(MCFQSPI_CS0 + chip_select, cs_high);
168 static void m532x_cs_deselect(struct mcfqspi_cs_control *cs_control,
169 u8 chip_select, bool cs_high)
171 gpio_set_value(MCFQSPI_CS0 + chip_select, !cs_high);
174 static struct mcfqspi_cs_control m532x_cs_control = {
175 .setup = m532x_cs_setup,
176 .teardown = m532x_cs_teardown,
177 .select = m532x_cs_select,
178 .deselect = m532x_cs_deselect,
181 static struct mcfqspi_platform_data m532x_qspi_data = {
184 .cs_control = &m532x_cs_control,
187 static struct platform_device m532x_qspi = {
190 .num_resources = ARRAY_SIZE(m532x_qspi_resources),
191 .resource = m532x_qspi_resources,
192 .dev.platform_data = &m532x_qspi_data,
195 static void __init m532x_qspi_init(void)
197 /* setup QSPS pins for QSPI with gpio CS control */
198 writew(0x01f0, MCF_GPIO_PAR_QSPI);
200 #endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
203 static struct platform_device *m532x_devices[] __initdata = {
206 #if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
211 /***************************************************************************/
213 static void __init m532x_uart_init_line(int line, int irq)
216 /* GPIO initialization */
217 MCF_GPIO_PAR_UART |= 0x000F;
218 } else if (line == 1) {
219 /* GPIO initialization */
220 MCF_GPIO_PAR_UART |= 0x0FF0;
224 static void __init m532x_uarts_init(void)
226 const int nrlines = ARRAY_SIZE(m532x_uart_platform);
229 for (line = 0; (line < nrlines); line++)
230 m532x_uart_init_line(line, m532x_uart_platform[line].irq);
232 /***************************************************************************/
234 static void __init m532x_fec_init(void)
236 /* Set multi-function pins to ethernet mode for fec0 */
237 MCF_GPIO_PAR_FECI2C |= (MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
238 MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
239 MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
240 MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
243 /***************************************************************************/
245 static void m532x_cpu_reset(void)
248 __raw_writeb(MCF_RCR_SWRESET, MCF_RCR);
251 /***************************************************************************/
253 void __init config_BSP(char *commandp, int size)
255 #if !defined(CONFIG_BOOTPARAM)
256 /* Copy command line from FLASH to local buffer... */
257 memcpy(commandp, (char *) 0x4000, 4);
258 if(strncmp(commandp, "kcl ", 4) == 0){
259 memcpy(commandp, (char *) 0x4004, size);
260 commandp[size-1] = 0;
262 memset(commandp, 0, size);
266 #ifdef CONFIG_BDM_DISABLE
268 * Disable the BDM clocking. This also turns off most of the rest of
269 * the BDM device. This is good for EMC reasons. This option is not
270 * incompatible with the memory protection option.
272 wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
276 /***************************************************************************/
278 static int __init init_BSP(void)
282 #if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
285 platform_add_devices(m532x_devices, ARRAY_SIZE(m532x_devices));
289 arch_initcall(init_BSP);
291 /***************************************************************************/
292 /* Board initialization */
293 /***************************************************************************/
295 * PLL min/max specifications
297 #define MAX_FVCO 500000 /* KHz */
298 #define MAX_FSYS 80000 /* KHz */
299 #define MIN_FSYS 58333 /* KHz */
300 #define FREF 16000 /* KHz */
303 #define MAX_MFD 135 /* Multiplier */
304 #define MIN_MFD 88 /* Multiplier */
305 #define BUSDIV 6 /* Divider */
308 * Low Power Divider specifications
310 #define MIN_LPD (1 << 0) /* Divider (not encoded) */
311 #define MAX_LPD (1 << 15) /* Divider (not encoded) */
312 #define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
314 #define SYS_CLK_KHZ 80000
315 #define SYSTEM_PERIOD 12.5
317 * SDRAM Timing Parameters
319 #define SDRAM_BL 8 /* # of beats in a burst */
320 #define SDRAM_TWR 2 /* in clocks */
321 #define SDRAM_CASL 2.5 /* CASL in clocks */
322 #define SDRAM_TRCD 2 /* in clocks */
323 #define SDRAM_TRP 2 /* in clocks */
324 #define SDRAM_TRFC 7 /* in clocks */
325 #define SDRAM_TREFI 7800 /* in ns */
327 #define EXT_SRAM_ADDRESS (0xC0000000)
328 #define FLASH_ADDRESS (0x00000000)
329 #define SDRAM_ADDRESS (0x40000000)
331 #define NAND_FLASH_ADDRESS (0xD0000000)
338 void gpio_init(void);
339 void fbcs_init(void);
340 void sdramc_init(void);
341 int clock_pll (int fsys, int flags);
342 int clock_limp (int);
343 int clock_exit_limp (void);
344 int get_sys_clock (void);
346 asmlinkage void __init sysinit(void)
348 sys_clk_khz = clock_pll(0, 0);
349 sys_clk_mhz = sys_clk_khz/1000;
360 /* Disable watchdog timer */
364 #define MCF_SCM_BCR_GBW (0x00000100)
365 #define MCF_SCM_BCR_GBR (0x00000200)
369 /* All masters are trusted */
370 MCF_SCM_MPR = 0x77777777;
372 /* Allow supervisor/user, read/write, and trusted/untrusted
373 access to all slaves */
382 MCF_SCM_BCR = (MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW);
388 MCF_GPIO_PAR_CS = 0x0000003E;
390 /* Latch chip select */
391 MCF_FBCS1_CSAR = 0x10080000;
393 MCF_FBCS1_CSCR = 0x002A3780;
394 MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V);
396 /* Initialize latch to drive signals to inactive states */
397 *((u16 *)(0x10080000)) = 0xFFFF;
400 MCF_FBCS1_CSAR = EXT_SRAM_ADDRESS;
401 MCF_FBCS1_CSCR = (MCF_FBCS_CSCR_PS_16
404 | MCF_FBCS_CSCR_WS(1));
405 MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_512K
408 /* Boot Flash connected to FBCS0 */
409 MCF_FBCS0_CSAR = FLASH_ADDRESS;
410 MCF_FBCS0_CSCR = (MCF_FBCS_CSCR_PS_16
414 | MCF_FBCS_CSCR_WS(7));
415 MCF_FBCS0_CSMR = (MCF_FBCS_CSMR_BAM_32M
419 void sdramc_init(void)
422 * Check to see if the SDRAM has already been initialized
423 * by a run control tool
425 if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) {
426 /* SDRAM chip select initialization */
428 /* Initialize SDRAM chip select */
429 MCF_SDRAMC_SDCS0 = (0
430 | MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS)
431 | MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE));
434 * Basic configuration and initialization
436 MCF_SDRAMC_SDCFG1 = (0
437 | MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5 ))
438 | MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1)
439 | MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL*2) + 2))
440 | MCF_SDRAMC_SDCFG1_ACT2RW((int)((SDRAM_TRCD ) + 0.5))
441 | MCF_SDRAMC_SDCFG1_PRE2ACT((int)((SDRAM_TRP ) + 0.5))
442 | MCF_SDRAMC_SDCFG1_REF2ACT((int)(((SDRAM_TRFC) ) + 0.5))
443 | MCF_SDRAMC_SDCFG1_WTLAT(3));
444 MCF_SDRAMC_SDCFG2 = (0
445 | MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL/2 + 1)
446 | MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL/2 + SDRAM_TWR)
447 | MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL+SDRAM_BL/2-1.0)+0.5))
448 | MCF_SDRAMC_SDCFG2_BL(SDRAM_BL-1));
452 * Precharge and enable write to SDMR
455 | MCF_SDRAMC_SDCR_MODE_EN
456 | MCF_SDRAMC_SDCR_CKE
457 | MCF_SDRAMC_SDCR_DDR
458 | MCF_SDRAMC_SDCR_MUX(1)
459 | MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI/(SYSTEM_PERIOD*64)) - 1) + 0.5))
460 | MCF_SDRAMC_SDCR_PS_16
461 | MCF_SDRAMC_SDCR_IPALL);
464 * Write extended mode register
467 | MCF_SDRAMC_SDMR_BNKAD_LEMR
468 | MCF_SDRAMC_SDMR_AD(0x0)
469 | MCF_SDRAMC_SDMR_CMD);
472 * Write mode register and reset DLL
475 | MCF_SDRAMC_SDMR_BNKAD_LMR
476 | MCF_SDRAMC_SDMR_AD(0x163)
477 | MCF_SDRAMC_SDMR_CMD);
480 * Execute a PALL command
482 MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;
485 * Perform two REF cycles
487 MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
488 MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
491 * Write mode register and clear reset DLL
494 | MCF_SDRAMC_SDMR_BNKAD_LMR
495 | MCF_SDRAMC_SDMR_AD(0x063)
496 | MCF_SDRAMC_SDMR_CMD);
499 * Enable auto refresh and lock SDMR
501 MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
502 MCF_SDRAMC_SDCR |= (0
503 | MCF_SDRAMC_SDCR_REF
504 | MCF_SDRAMC_SDCR_DQS_OE(0xC));
510 /* Enable UART0 pins */
511 MCF_GPIO_PAR_UART = ( 0
512 | MCF_GPIO_PAR_UART_PAR_URXD0
513 | MCF_GPIO_PAR_UART_PAR_UTXD0);
515 /* Initialize TIN3 as a GPIO output to enable the write
517 MCF_GPIO_PAR_TIMER = 0x00;
518 __raw_writeb(0x08, MCFGPIO_PDDR_TIMER);
519 __raw_writeb(0x00, MCFGPIO_PCLRR_TIMER);
523 int clock_pll(int fsys, int flags)
525 int fref, temp, fout, mfd;
531 /* Return current PLL output */
534 return (fref * mfd / (BUSDIV * 4));
537 /* Check bounds of requested system clock */
543 /* Multiplying by 100 when calculating the temp value,
544 and then dividing by 100 to calculate the mfd allows
545 for exact values without needing to include floating
547 temp = 100 * fsys / fref;
548 mfd = 4 * BUSDIV * temp / 100;
550 /* Determine the output frequency for selected values */
551 fout = (fref * mfd / (BUSDIV * 4));
554 * Check to see if the SDRAM has already been initialized.
555 * If it has then the SDRAM needs to be put into self refresh
556 * mode before reprogramming the PLL.
558 if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
559 /* Put SDRAM into self refresh mode */
560 MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE;
563 * Initialize the PLL to generate the new system clock frequency.
564 * The device must be put into LIMP mode to reprogram the PLL.
567 /* Enter LIMP mode */
568 clock_limp(DEFAULT_LPD);
570 /* Reprogram PLL for desired fsys */
572 | MCF_PLL_PODR_CPUDIV(BUSDIV/3)
573 | MCF_PLL_PODR_BUSDIV(BUSDIV));
581 * Return the SDRAM to normal operation if it is in use.
583 if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
584 /* Exit self refresh mode */
585 MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_CKE;
587 /* Errata - workaround for SDRAM opeartion after exiting LIMP mode */
588 MCF_SDRAMC_LIMP_FIX = MCF_SDRAMC_REFRESH;
590 /* wait for DQS logic to relock */
591 for (i = 0; i < 0x200; i++)
597 int clock_limp(int div)
601 /* Check bounds of divider */
607 /* Save of the current value of the SSIDIV so we don't
608 overwrite the value*/
609 temp = (MCF_CCM_CDR & MCF_CCM_CDR_SSIDIV(0xF));
611 /* Apply the divider to the system clock */
613 | MCF_CCM_CDR_LPDIV(div)
614 | MCF_CCM_CDR_SSIDIV(temp));
616 MCF_CCM_MISCCR |= MCF_CCM_MISCCR_LIMP;
618 return (FREF/(3*(1 << div)));
621 int clock_exit_limp(void)
626 MCF_CCM_MISCCR = (MCF_CCM_MISCCR & ~ MCF_CCM_MISCCR_LIMP);
628 /* Wait for PLL to lock */
629 while (!(MCF_CCM_MISCCR & MCF_CCM_MISCCR_PLL_LOCK))
632 fout = get_sys_clock();
637 int get_sys_clock(void)
641 /* Test to see if device is in LIMP mode */
642 if (MCF_CCM_MISCCR & MCF_CCM_MISCCR_LIMP) {
643 divider = MCF_CCM_CDR & MCF_CCM_CDR_LPDIV(0xF);
644 return (FREF/(2 << divider));
647 return ((FREF * MCF_PLL_PFDR) / (BUSDIV * 4));