1 /***************************************************************************/
4 * linux/arch/m68knommu/platform/527x/config.c
6 * Sub-architcture dependant initialization code for the Freescale
9 * Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com)
10 * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
13 /***************************************************************************/
15 #include <linux/kernel.h>
16 #include <linux/param.h>
17 #include <linux/init.h>
19 #include <linux/spi/spi.h>
20 #include <linux/gpio.h>
21 #include <asm/machdep.h>
22 #include <asm/coldfire.h>
23 #include <asm/mcfsim.h>
24 #include <asm/mcfuart.h>
25 #include <asm/mcfqspi.h>
27 /***************************************************************************/
29 static struct mcf_platform_uart m527x_uart_platform[] = {
31 .mapbase = MCF_MBAR + MCFUART_BASE1,
32 .irq = MCFINT_VECBASE + MCFINT_UART0,
35 .mapbase = MCF_MBAR + MCFUART_BASE2,
36 .irq = MCFINT_VECBASE + MCFINT_UART1,
39 .mapbase = MCF_MBAR + MCFUART_BASE3,
40 .irq = MCFINT_VECBASE + MCFINT_UART2,
45 static struct platform_device m527x_uart = {
48 .dev.platform_data = m527x_uart_platform,
51 static struct resource m527x_fec0_resources[] = {
53 .start = MCF_MBAR + 0x1000,
54 .end = MCF_MBAR + 0x1000 + 0x7ff,
55 .flags = IORESOURCE_MEM,
60 .flags = IORESOURCE_IRQ,
65 .flags = IORESOURCE_IRQ,
70 .flags = IORESOURCE_IRQ,
74 static struct resource m527x_fec1_resources[] = {
76 .start = MCF_MBAR + 0x1800,
77 .end = MCF_MBAR + 0x1800 + 0x7ff,
78 .flags = IORESOURCE_MEM,
83 .flags = IORESOURCE_IRQ,
88 .flags = IORESOURCE_IRQ,
93 .flags = IORESOURCE_IRQ,
97 static struct platform_device m527x_fec[] = {
101 .num_resources = ARRAY_SIZE(m527x_fec0_resources),
102 .resource = m527x_fec0_resources,
107 .num_resources = ARRAY_SIZE(m527x_fec1_resources),
108 .resource = m527x_fec1_resources,
112 #if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
113 static struct resource m527x_qspi_resources[] = {
115 .start = MCFQSPI_IOBASE,
116 .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
117 .flags = IORESOURCE_MEM,
120 .start = MCFINT_VECBASE + MCFINT_QSPI,
121 .end = MCFINT_VECBASE + MCFINT_QSPI,
122 .flags = IORESOURCE_IRQ,
126 #if defined(CONFIG_M5271)
127 #define MCFQSPI_CS0 91
128 #define MCFQSPI_CS1 92
129 #define MCFQSPI_CS2 99
130 #define MCFQSPI_CS3 103
131 #elif defined(CONFIG_M5275)
132 #define MCFQSPI_CS0 59
133 #define MCFQSPI_CS1 60
134 #define MCFQSPI_CS2 61
135 #define MCFQSPI_CS3 62
138 static int m527x_cs_setup(struct mcfqspi_cs_control *cs_control)
142 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
144 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
147 status = gpio_direction_output(MCFQSPI_CS0, 1);
149 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
153 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
155 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
158 status = gpio_direction_output(MCFQSPI_CS1, 1);
160 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
164 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
166 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
169 status = gpio_direction_output(MCFQSPI_CS2, 1);
171 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
175 status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
177 pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
180 status = gpio_direction_output(MCFQSPI_CS3, 1);
182 pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
189 gpio_free(MCFQSPI_CS3);
191 gpio_free(MCFQSPI_CS2);
193 gpio_free(MCFQSPI_CS1);
195 gpio_free(MCFQSPI_CS0);
200 static void m527x_cs_teardown(struct mcfqspi_cs_control *cs_control)
202 gpio_free(MCFQSPI_CS3);
203 gpio_free(MCFQSPI_CS2);
204 gpio_free(MCFQSPI_CS1);
205 gpio_free(MCFQSPI_CS0);
208 static void m527x_cs_select(struct mcfqspi_cs_control *cs_control,
209 u8 chip_select, bool cs_high)
211 switch (chip_select) {
213 gpio_set_value(MCFQSPI_CS0, cs_high);
216 gpio_set_value(MCFQSPI_CS1, cs_high);
219 gpio_set_value(MCFQSPI_CS2, cs_high);
222 gpio_set_value(MCFQSPI_CS3, cs_high);
227 static void m527x_cs_deselect(struct mcfqspi_cs_control *cs_control,
228 u8 chip_select, bool cs_high)
230 switch (chip_select) {
232 gpio_set_value(MCFQSPI_CS0, !cs_high);
235 gpio_set_value(MCFQSPI_CS1, !cs_high);
238 gpio_set_value(MCFQSPI_CS2, !cs_high);
241 gpio_set_value(MCFQSPI_CS3, !cs_high);
246 static struct mcfqspi_cs_control m527x_cs_control = {
247 .setup = m527x_cs_setup,
248 .teardown = m527x_cs_teardown,
249 .select = m527x_cs_select,
250 .deselect = m527x_cs_deselect,
253 static struct mcfqspi_platform_data m527x_qspi_data = {
256 .cs_control = &m527x_cs_control,
259 static struct platform_device m527x_qspi = {
262 .num_resources = ARRAY_SIZE(m527x_qspi_resources),
263 .resource = m527x_qspi_resources,
264 .dev.platform_data = &m527x_qspi_data,
267 static void __init m527x_qspi_init(void)
269 #if defined(CONFIG_M5271)
272 /* setup QSPS pins for QSPI with gpio CS control */
273 writeb(0x1f, MCFGPIO_PAR_QSPI);
274 /* and CS2 & CS3 as gpio */
275 par = readw(MCFGPIO_PAR_TIMER);
277 writew(par, MCFGPIO_PAR_TIMER);
278 #elif defined(CONFIG_M5275)
279 /* setup QSPS pins for QSPI with gpio CS control */
280 writew(0x003e, MCFGPIO_PAR_QSPI);
283 #endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
285 static struct platform_device *m527x_devices[] __initdata = {
291 #if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
296 /***************************************************************************/
298 static void __init m527x_uart_init_line(int line, int irq)
302 if ((line < 0) || (line > 2))
306 * External Pin Mask Setting & Enable External Pin for Interface
308 sepmask = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
310 sepmask |= UART0_ENABLE_MASK;
312 sepmask |= UART1_ENABLE_MASK;
314 sepmask |= UART2_ENABLE_MASK;
315 writew(sepmask, MCF_IPSBAR + MCF_GPIO_PAR_UART);
318 static void __init m527x_uarts_init(void)
320 const int nrlines = ARRAY_SIZE(m527x_uart_platform);
323 for (line = 0; (line < nrlines); line++)
324 m527x_uart_init_line(line, m527x_uart_platform[line].irq);
327 /***************************************************************************/
329 static void __init m527x_fec_init(void)
334 /* Set multi-function pins to ethernet mode for fec0 */
335 #if defined(CONFIG_M5271)
336 v = readb(MCF_IPSBAR + 0x100047);
337 writeb(v | 0xf0, MCF_IPSBAR + 0x100047);
339 par = readw(MCF_IPSBAR + 0x100082);
340 writew(par | 0xf00, MCF_IPSBAR + 0x100082);
341 v = readb(MCF_IPSBAR + 0x100078);
342 writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
346 /* Set multi-function pins to ethernet mode for fec1 */
347 par = readw(MCF_IPSBAR + 0x100082);
348 writew(par | 0xa0, MCF_IPSBAR + 0x100082);
349 v = readb(MCF_IPSBAR + 0x100079);
350 writeb(v | 0xc0, MCF_IPSBAR + 0x100079);
354 /***************************************************************************/
356 static void m527x_cpu_reset(void)
359 __raw_writeb(MCF_RCR_SWRESET, MCF_IPSBAR + MCF_RCR);
362 /***************************************************************************/
364 void __init config_BSP(char *commandp, int size)
366 mach_reset = m527x_cpu_reset;
369 #if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
374 /***************************************************************************/
376 static int __init init_BSP(void)
378 platform_add_devices(m527x_devices, ARRAY_SIZE(m527x_devices));
382 arch_initcall(init_BSP);
384 /***************************************************************************/