1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
13 #include <asm/global_data.h>
14 #include <linux/delay.h>
16 #include <asm/timer.h>
17 #include <asm/immap.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 static volatile ulong timestamp = 0;
24 #ifndef CFG_SYS_WATCHDOG_FREQ
25 #define CFG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
28 #if CONFIG_IS_ENABLED(MCFTMR)
29 #ifndef CFG_SYS_UDELAY_BASE
30 # error "uDelay base not defined!"
33 #if !defined(CFG_SYS_TMR_BASE) || !defined(CFG_SYS_INTR_BASE) || !defined(CFG_SYS_TMRINTR_NO) || !defined(CFG_SYS_TMRINTR_MASK)
34 # error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
36 extern void dtimer_intr_setup(void);
38 void __udelay(unsigned long usec)
40 volatile dtmr_t *timerp = (dtmr_t *) (CFG_SYS_UDELAY_BASE);
50 /* Set up TIMER 3 as timebase clock */
51 timerp->tmr = DTIM_DTMR_RST_RST;
53 /* set period to 1 us */
55 CFG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR |
58 start = now = timerp->tcn;
59 while (now < start + tmp)
64 void dtimer_interrupt(void *not_used)
66 volatile dtmr_t *timerp = (dtmr_t *) (CFG_SYS_TMR_BASE);
68 /* check for timer interrupt asserted */
69 if ((CFG_SYS_TMRPND_REG & CFG_SYS_TMRINTR_MASK) == CFG_SYS_TMRINTR_PEND) {
70 timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF);
73 #if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
74 if (CFG_SYS_WATCHDOG_FREQ && (timestamp % (CFG_SYS_WATCHDOG_FREQ)) == 0) {
77 #endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
84 volatile dtmr_t *timerp = (dtmr_t *) (CFG_SYS_TMR_BASE);
91 /* Set up TIMER 4 as clock */
92 timerp->tmr = DTIM_DTMR_RST_RST;
94 /* initialize and enable timer interrupt */
95 irq_install_handler(CFG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
98 timerp->trr = 1000; /* Interrupt every ms */
102 /* set a period of 1us, set timer mode to restart and enable timer and interrupt */
103 timerp->tmr = CFG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 |
104 DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN;
109 ulong get_timer(ulong base)
111 return (timestamp - base);
115 * This function is derived from PowerPC code (read timebase as long long).
116 * On M68K it just returns the timer value.
118 unsigned long long get_ticks(void)
123 static u64 timer64 __section(".data");
124 static u16 timer16 __section(".data");
126 uint64_t __weak get_ticks(void)
128 volatile pit_t *timerp = (pit_t *) (CFG_SYS_UDELAY_BASE);
129 u16 val = ~timerp->pcntr;
132 timer64 += 0xffff - timer16 + val;
134 timer64 += val - timer16;
144 volatile pit_t *timerp = (pit_t *) (CFG_SYS_UDELAY_BASE);
149 /* Set up PIT as timebase clock */
150 timerp->pmr = 0xffff;
151 timerp->pcsr = PIT_PCSR_EN | PIT_PCSR_OVW;
155 #endif /* CONFIG_MCFTMR */
157 unsigned long usec2ticks(unsigned long usec)
159 return get_timer(usec);
163 * This function is derived from PowerPC code (timebase clock frequency).
164 * On M68K it returns the number of timer ticks per second.
166 ulong get_tbclk(void)
168 return CONFIG_SYS_HZ;