1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
13 #include <asm/timer.h>
14 #include <asm/immap.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 static volatile ulong timestamp = 0;
21 #ifndef CONFIG_SYS_WATCHDOG_FREQ
22 #define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
25 #if defined(CONFIG_MCFTMR)
26 #ifndef CONFIG_SYS_UDELAY_BASE
27 # error "uDelay base not defined!"
30 #if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK)
31 # error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
33 extern void dtimer_intr_setup(void);
35 void __udelay(unsigned long usec)
37 volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_UDELAY_BASE);
47 /* Set up TIMER 3 as timebase clock */
48 timerp->tmr = DTIM_DTMR_RST_RST;
50 /* set period to 1 us */
52 CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR |
55 start = now = timerp->tcn;
56 while (now < start + tmp)
61 void dtimer_interrupt(void *not_used)
63 volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE);
65 /* check for timer interrupt asserted */
66 if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) {
67 timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF);
70 #if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
71 if ((timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0) {
74 #endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
81 volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE);
88 /* Set up TIMER 4 as clock */
89 timerp->tmr = DTIM_DTMR_RST_RST;
91 /* initialize and enable timer interrupt */
92 irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
95 timerp->trr = 1000; /* Interrupt every ms */
99 /* set a period of 1us, set timer mode to restart and enable timer and interrupt */
100 timerp->tmr = CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 |
101 DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN;
106 ulong get_timer(ulong base)
108 return (timestamp - base);
111 #endif /* CONFIG_MCFTMR */
113 #if defined(CONFIG_MCFPIT)
114 #if !defined(CONFIG_SYS_PIT_BASE)
115 # error "CONFIG_SYS_PIT_BASE not defined!"
118 static unsigned short lastinc;
120 void __udelay(unsigned long usec)
122 volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_UDELAY_BASE);
132 /* Set up TIMER 3 as timebase clock */
133 timerp->pcsr = PIT_PCSR_OVW;
135 /* set period to 1 us */
136 timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN;
139 while (timerp->pcntr > 0) ;
143 void timer_init(void)
145 volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE);
148 /* Set up TIMER 4 as poll clock */
149 timerp->pcsr = PIT_PCSR_OVW;
150 timerp->pmr = lastinc = 0;
151 timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN;
156 ulong get_timer(ulong base)
158 unsigned short now, diff;
159 volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE);
162 diff = -(now - lastinc);
166 return timestamp - base;
169 void wait_ticks(unsigned long ticks)
171 u32 start = get_timer(0);
172 while (get_timer(start) < ticks) ;
174 #endif /* CONFIG_MCFPIT */
177 * This function is derived from PowerPC code (read timebase as long long).
178 * On M68K it just returns the timer value.
180 unsigned long long get_ticks(void)
185 unsigned long usec2ticks(unsigned long usec)
187 return get_timer(usec);
191 * This function is derived from PowerPC code (timebase clock frequency).
192 * On M68K it returns the number of timer ticks per second.
194 ulong get_tbclk(void)
196 return CONFIG_SYS_HZ;