1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * ColdFire Internal Memory Map and Defines
5 * Copyright 2004-2012 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
12 #if defined(CONFIG_MCF520x)
13 #include <asm/immap_520x.h>
14 #include <asm/m520x.h>
16 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
19 #if CONFIG_IS_ENABLED(MCFTMR)
20 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
21 #define CFG_SYS_TMR_BASE (MMAP_DTMR1)
22 #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
23 #define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
24 #define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
25 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
26 #define CFG_SYS_TMRINTR_PRI (6)
27 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
29 #define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
32 #define CFG_SYS_INTR_BASE (MMAP_INTC0)
33 #define CFG_SYS_NUM_IRQS (128)
34 #endif /* CONFIG_M520x */
37 #include <asm/immap_5235.h>
38 #include <asm/m5235.h>
40 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
43 #if CONFIG_IS_ENABLED(MCFTMR)
44 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
45 #define CFG_SYS_TMR_BASE (MMAP_DTMR3)
46 #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
47 #define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
48 #define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
49 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
50 #define CFG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
51 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
53 #define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
56 #define CFG_SYS_INTR_BASE (MMAP_INTC0)
57 #define CFG_SYS_NUM_IRQS (128)
58 #endif /* CONFIG_M5235 */
61 #include <asm/immap_5249.h>
62 #include <asm/m5249.h>
64 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
66 #define CFG_SYS_INTR_BASE (MMAP_INTC)
67 #define CFG_SYS_NUM_IRQS (64)
70 #if CONFIG_IS_ENABLED(MCFTMR)
71 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
72 #define CFG_SYS_TMR_BASE (MMAP_DTMR1)
73 #define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
74 #define CFG_SYS_TMRINTR_NO (31)
75 #define CFG_SYS_TMRINTR_MASK (0x00000400)
76 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
77 #define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
78 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
80 #define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
82 #endif /* CONFIG_M5249 */
85 #include <asm/immap_5253.h>
86 #include <asm/m5249.h>
87 #include <asm/m5253.h>
89 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
91 #define CFG_SYS_INTR_BASE (MMAP_INTC)
92 #define CFG_SYS_NUM_IRQS (64)
95 #if CONFIG_IS_ENABLED(MCFTMR)
96 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
97 #define CFG_SYS_TMR_BASE (MMAP_DTMR1)
98 #define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
99 #define CFG_SYS_TMRINTR_NO (27)
100 #define CFG_SYS_TMRINTR_MASK (0x00000400)
101 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
102 #define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
103 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
105 #define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
107 #endif /* CONFIG_M5253 */
110 #include <asm/immap_5271.h>
111 #include <asm/m5271.h>
113 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
116 #if CONFIG_IS_ENABLED(MCFTMR)
117 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
118 #define CFG_SYS_TMR_BASE (MMAP_DTMR3)
119 #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
120 #define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
121 #define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
122 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
123 #define CFG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */
124 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
126 #define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
129 #define CFG_SYS_INTR_BASE (MMAP_INTC0)
130 #define CFG_SYS_NUM_IRQS (128)
131 #endif /* CONFIG_M5271 */
134 #include <asm/immap_5272.h>
135 #include <asm/m5272.h>
137 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
139 #define CFG_SYS_INTR_BASE (MMAP_INTC)
140 #define CFG_SYS_NUM_IRQS (64)
143 #if CONFIG_IS_ENABLED(MCFTMR)
144 #define CFG_SYS_UDELAY_BASE (MMAP_TMR0)
145 #define CFG_SYS_TMR_BASE (MMAP_TMR3)
146 #define CFG_SYS_TMRPND_REG (((volatile intctrl_t *)(CFG_SYS_INTR_BASE))->int_isr)
147 #define CFG_SYS_TMRINTR_NO (INT_TMR3)
148 #define CFG_SYS_TMRINTR_MASK (INT_ISR_INT24)
149 #define CFG_SYS_TMRINTR_PEND (0)
150 #define CFG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
151 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
153 #define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
155 #endif /* CONFIG_M5272 */
158 #include <asm/immap_5275.h>
159 #include <asm/m5275.h>
161 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
163 #define CFG_SYS_INTR_BASE (MMAP_INTC0)
164 #define CFG_SYS_NUM_IRQS (192)
167 #if CONFIG_IS_ENABLED(MCFTMR)
168 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
169 #define CFG_SYS_TMR_BASE (MMAP_DTMR3)
170 #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
171 #define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
172 #define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
173 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
174 #define CFG_SYS_TMRINTR_PRI (0x1E)
175 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
177 #define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
179 #endif /* CONFIG_M5275 */
182 #include <asm/immap_5282.h>
183 #include <asm/m5282.h>
185 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
187 #define CFG_SYS_INTR_BASE (MMAP_INTC0)
188 #define CFG_SYS_NUM_IRQS (128)
191 #if CONFIG_IS_ENABLED(MCFTMR)
192 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
193 #define CFG_SYS_TMR_BASE (MMAP_DTMR3)
194 #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
195 #define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
196 #define CFG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3)
197 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
198 #define CFG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
199 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
201 #define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
203 #endif /* CONFIG_M5282 */
206 #include <asm/immap_5307.h>
207 #include <asm/m5307.h>
209 #define CFG_SYS_UART_BASE (MMAP_UART0 + \
210 (CFG_SYS_UART_PORT * 0x40))
211 #define CFG_SYS_INTR_BASE (MMAP_INTC)
212 #define CFG_SYS_NUM_IRQS (64)
215 #if CONFIG_IS_ENABLED(MCFTMR)
216 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
217 #define CFG_SYS_TMR_BASE (MMAP_DTMR1)
218 #define CFG_SYS_TMRPND_REG (((volatile intctrl_t *) \
219 (CFG_SYS_INTR_BASE))->ipr)
220 #define CFG_SYS_TMRINTR_NO (31)
221 #define CFG_SYS_TMRINTR_MASK (0x00000400)
222 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
223 #define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \
224 MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
225 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
227 #define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
229 #endif /* CONFIG_M5307 */
231 #if defined(CONFIG_MCF5301x)
232 #include <asm/immap_5301x.h>
233 #include <asm/m5301x.h>
235 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
238 #if CONFIG_IS_ENABLED(MCFTMR)
239 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
240 #define CFG_SYS_TMR_BASE (MMAP_DTMR1)
241 #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
242 #define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
243 #define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
244 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
245 #define CFG_SYS_TMRINTR_PRI (6)
246 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
248 #define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
251 #define CFG_SYS_INTR_BASE (MMAP_INTC0)
252 #define CFG_SYS_NUM_IRQS (128)
253 #endif /* CONFIG_M5301x */
255 #if defined(CONFIG_M5329) || defined(CONFIG_M5373)
256 #include <asm/immap_5329.h>
257 #include <asm/m5329.h>
259 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
262 #if CONFIG_IS_ENABLED(MCFTMR)
263 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
264 #define CFG_SYS_TMR_BASE (MMAP_DTMR1)
265 #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
266 #define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
267 #define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
268 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
269 #define CFG_SYS_TMRINTR_PRI (6)
270 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
272 #define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
275 #define CFG_SYS_INTR_BASE (MMAP_INTC0)
276 #define CFG_SYS_NUM_IRQS (128)
277 #endif /* CONFIG_M5329 && CONFIG_M5373 */
279 #if defined(CONFIG_M54418)
280 #include <asm/immap_5441x.h>
281 #include <asm/m5441x.h>
283 #if (CFG_SYS_UART_PORT < 4)
284 #define CFG_SYS_UART_BASE (MMAP_UART0 + \
285 (CFG_SYS_UART_PORT * 0x4000))
287 #define CFG_SYS_UART_BASE (MMAP_UART4 + \
288 ((CFG_SYS_UART_PORT - 4) * 0x4000))
291 #define MMAP_DSPI MMAP_DSPI0
294 #if CONFIG_IS_ENABLED(MCFTMR)
295 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
296 #define CFG_SYS_TMR_BASE (MMAP_DTMR1)
297 #define CFG_SYS_TMRPND_REG (((int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
298 #define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
299 #define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
300 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
301 #define CFG_SYS_TMRINTR_PRI (6)
302 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
304 #define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
307 #define CFG_SYS_INTR_BASE (MMAP_INTC0)
308 #define CFG_SYS_NUM_IRQS (192)
310 #endif /* CONFIG_M54418 */
313 #include <asm/immap_547x_8x.h>
314 #include <asm/m547x_8x.h>
316 #ifdef CONFIG_FSLDMAFEC
317 #define FEC0_RX_TASK 0
318 #define FEC0_TX_TASK 1
319 #define FEC0_RX_PRIORITY 6
320 #define FEC0_TX_PRIORITY 7
321 #define FEC0_RX_INIT 16
322 #define FEC0_TX_INIT 17
323 #define FEC1_RX_TASK 2
324 #define FEC1_TX_TASK 3
325 #define FEC1_RX_PRIORITY 6
326 #define FEC1_TX_PRIORITY 7
327 #define FEC1_RX_INIT 30
328 #define FEC1_TX_INIT 31
331 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100))
334 #define CFG_SYS_UDELAY_BASE (MMAP_SLT1)
335 #define CFG_SYS_TMR_BASE (MMAP_SLT0)
336 #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
337 #define CFG_SYS_TMRINTR_NO (INT0_HI_SLT0)
338 #define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
339 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
340 #define CFG_SYS_TMRINTR_PRI (0x1E)
341 #define CFG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
344 #define CFG_SYS_INTR_BASE (MMAP_INTC0)
345 #define CFG_SYS_NUM_IRQS (128)
348 #define CFG_SYS_PCI_BAR0 (0x40000000)
349 #define CFG_SYS_PCI_BAR1 (CFG_SYS_SDRAM_BASE)
350 #define CFG_SYS_PCI_TBATR0 (CFG_SYS_MBAR)
351 #define CFG_SYS_PCI_TBATR1 (CFG_SYS_SDRAM_BASE)
353 #endif /* CONFIG_M547x */
355 #endif /* __IMMAP_H */