1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * ColdFire Internal Memory Map and Defines
5 * Copyright 2004-2012 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
12 #if defined(CONFIG_MCF520x)
13 #include <asm/immap_520x.h>
14 #include <asm/m520x.h>
16 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
17 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
21 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
22 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
23 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
24 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
25 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
26 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
27 #define CONFIG_SYS_TMRINTR_PRI (6)
28 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
31 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
32 #define CONFIG_SYS_NUM_IRQS (128)
33 #endif /* CONFIG_M520x */
36 #include <asm/immap_5235.h>
37 #include <asm/m5235.h>
39 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
40 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
44 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
45 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
46 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
47 #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
48 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
49 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
50 #define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
51 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
54 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
55 #define CONFIG_SYS_NUM_IRQS (128)
56 #endif /* CONFIG_M5235 */
59 #include <asm/immap_5249.h>
60 #include <asm/m5249.h>
62 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
64 #define CONFIG_SYS_INTR_BASE (MMAP_INTC)
65 #define CONFIG_SYS_NUM_IRQS (64)
69 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
70 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
71 #define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
72 #define CONFIG_SYS_TMRINTR_NO (31)
73 #define CONFIG_SYS_TMRINTR_MASK (0x00000400)
74 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
75 #define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
76 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
78 #endif /* CONFIG_M5249 */
81 #include <asm/immap_5253.h>
82 #include <asm/m5249.h>
83 #include <asm/m5253.h>
85 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
87 #define CONFIG_SYS_INTR_BASE (MMAP_INTC)
88 #define CONFIG_SYS_NUM_IRQS (64)
92 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
93 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
94 #define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
95 #define CONFIG_SYS_TMRINTR_NO (27)
96 #define CONFIG_SYS_TMRINTR_MASK (0x00000400)
97 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
98 #define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
99 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
101 #endif /* CONFIG_M5253 */
104 #include <asm/immap_5271.h>
105 #include <asm/m5271.h>
107 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
108 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
112 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
113 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
114 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
115 #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
116 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
117 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
118 #define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */
119 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
122 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
123 #define CONFIG_SYS_NUM_IRQS (128)
124 #endif /* CONFIG_M5271 */
127 #include <asm/immap_5272.h>
128 #include <asm/m5272.h>
130 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
131 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
133 #define CONFIG_SYS_INTR_BASE (MMAP_INTC)
134 #define CONFIG_SYS_NUM_IRQS (64)
138 #define CONFIG_SYS_UDELAY_BASE (MMAP_TMR0)
139 #define CONFIG_SYS_TMR_BASE (MMAP_TMR3)
140 #define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *)(CONFIG_SYS_INTR_BASE))->int_isr)
141 #define CONFIG_SYS_TMRINTR_NO (INT_TMR3)
142 #define CONFIG_SYS_TMRINTR_MASK (INT_ISR_INT24)
143 #define CONFIG_SYS_TMRINTR_PEND (0)
144 #define CONFIG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
145 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
147 #endif /* CONFIG_M5272 */
150 #include <asm/immap_5275.h>
151 #include <asm/m5275.h>
153 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
154 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
155 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
157 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
158 #define CONFIG_SYS_NUM_IRQS (192)
162 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
163 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
164 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
165 #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
166 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
167 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
168 #define CONFIG_SYS_TMRINTR_PRI (0x1E)
169 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
171 #endif /* CONFIG_M5275 */
174 #include <asm/immap_5282.h>
175 #include <asm/m5282.h>
177 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
178 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
180 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
181 #define CONFIG_SYS_NUM_IRQS (128)
185 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
186 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
187 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
188 #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
189 #define CONFIG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3)
190 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
191 #define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
192 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
194 #endif /* CONFIG_M5282 */
197 #include <asm/immap_5307.h>
198 #include <asm/m5307.h>
200 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
201 (CONFIG_SYS_UART_PORT * 0x40))
202 #define CONFIG_SYS_INTR_BASE (MMAP_INTC)
203 #define CONFIG_SYS_NUM_IRQS (64)
207 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
208 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
209 #define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *) \
210 (CONFIG_SYS_INTR_BASE))->ipr)
211 #define CONFIG_SYS_TMRINTR_NO (31)
212 #define CONFIG_SYS_TMRINTR_MASK (0x00000400)
213 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
214 #define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \
215 MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
216 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
218 #endif /* CONFIG_M5307 */
220 #if defined(CONFIG_MCF5301x)
221 #include <asm/immap_5301x.h>
222 #include <asm/m5301x.h>
224 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
225 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
226 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
228 #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
232 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
233 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
234 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
235 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
236 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
237 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
238 #define CONFIG_SYS_TMRINTR_PRI (6)
239 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
242 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
243 #define CONFIG_SYS_NUM_IRQS (128)
244 #endif /* CONFIG_M5301x */
246 #if defined(CONFIG_M5329) || defined(CONFIG_M5373)
247 #include <asm/immap_5329.h>
248 #include <asm/m5329.h>
250 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
251 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
252 #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
256 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
257 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
258 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
259 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
260 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
261 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
262 #define CONFIG_SYS_TMRINTR_PRI (6)
263 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
266 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
267 #define CONFIG_SYS_NUM_IRQS (128)
268 #endif /* CONFIG_M5329 && CONFIG_M5373 */
270 #if defined(CONFIG_M54418)
271 #include <asm/immap_5441x.h>
272 #include <asm/m5441x.h>
274 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
275 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
277 #if (CONFIG_SYS_UART_PORT < 4)
278 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
279 (CONFIG_SYS_UART_PORT * 0x4000))
281 #define CONFIG_SYS_UART_BASE (MMAP_UART4 + \
282 ((CONFIG_SYS_UART_PORT - 4) * 0x4000))
285 #define MMAP_DSPI MMAP_DSPI0
286 #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
290 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
291 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
292 #define CONFIG_SYS_TMRPND_REG (((int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
293 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
294 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
295 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
296 #define CONFIG_SYS_TMRINTR_PRI (6)
297 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
300 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
301 #define CONFIG_SYS_NUM_IRQS (192)
303 #endif /* CONFIG_M54418 */
306 #include <asm/immap_547x_8x.h>
307 #include <asm/m547x_8x.h>
309 #ifdef CONFIG_FSLDMAFEC
310 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
311 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
313 #define FEC0_RX_TASK 0
314 #define FEC0_TX_TASK 1
315 #define FEC0_RX_PRIORITY 6
316 #define FEC0_TX_PRIORITY 7
317 #define FEC0_RX_INIT 16
318 #define FEC0_TX_INIT 17
319 #define FEC1_RX_TASK 2
320 #define FEC1_TX_TASK 3
321 #define FEC1_RX_PRIORITY 6
322 #define FEC1_TX_PRIORITY 7
323 #define FEC1_RX_INIT 30
324 #define FEC1_TX_INIT 31
327 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
330 #define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1)
331 #define CONFIG_SYS_TMR_BASE (MMAP_SLT0)
332 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
333 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0)
334 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
335 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
336 #define CONFIG_SYS_TMRINTR_PRI (0x1E)
337 #define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
340 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
341 #define CONFIG_SYS_NUM_IRQS (128)
344 #define CONFIG_SYS_PCI_BAR0 (0x40000000)
345 #define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE)
346 #define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
347 #define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE)
349 #endif /* CONFIG_M547x */
351 #endif /* __IMMAP_H */