1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * ColdFire Internal Memory Map and Defines
5 * Copyright 2004-2012 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
12 #if defined(CONFIG_MCF520x)
13 #include <asm/immap_520x.h>
14 #include <asm/m520x.h>
16 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
20 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
21 #define CFG_SYS_TMR_BASE (MMAP_DTMR1)
22 #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
23 #define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
24 #define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
25 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
26 #define CFG_SYS_TMRINTR_PRI (6)
27 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
30 #define CFG_SYS_INTR_BASE (MMAP_INTC0)
31 #define CFG_SYS_NUM_IRQS (128)
32 #endif /* CONFIG_M520x */
35 #include <asm/immap_5235.h>
36 #include <asm/m5235.h>
38 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
42 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
43 #define CFG_SYS_TMR_BASE (MMAP_DTMR3)
44 #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
45 #define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
46 #define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
47 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
48 #define CFG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
49 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
52 #define CFG_SYS_INTR_BASE (MMAP_INTC0)
53 #define CFG_SYS_NUM_IRQS (128)
54 #endif /* CONFIG_M5235 */
57 #include <asm/immap_5249.h>
58 #include <asm/m5249.h>
60 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
62 #define CFG_SYS_INTR_BASE (MMAP_INTC)
63 #define CFG_SYS_NUM_IRQS (64)
67 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
68 #define CFG_SYS_TMR_BASE (MMAP_DTMR1)
69 #define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
70 #define CFG_SYS_TMRINTR_NO (31)
71 #define CFG_SYS_TMRINTR_MASK (0x00000400)
72 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
73 #define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
74 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
76 #endif /* CONFIG_M5249 */
79 #include <asm/immap_5253.h>
80 #include <asm/m5249.h>
81 #include <asm/m5253.h>
83 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
85 #define CFG_SYS_INTR_BASE (MMAP_INTC)
86 #define CFG_SYS_NUM_IRQS (64)
90 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
91 #define CFG_SYS_TMR_BASE (MMAP_DTMR1)
92 #define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
93 #define CFG_SYS_TMRINTR_NO (27)
94 #define CFG_SYS_TMRINTR_MASK (0x00000400)
95 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
96 #define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
97 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
99 #endif /* CONFIG_M5253 */
102 #include <asm/immap_5271.h>
103 #include <asm/m5271.h>
105 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
109 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
110 #define CFG_SYS_TMR_BASE (MMAP_DTMR3)
111 #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
112 #define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
113 #define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
114 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
115 #define CFG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */
116 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
119 #define CFG_SYS_INTR_BASE (MMAP_INTC0)
120 #define CFG_SYS_NUM_IRQS (128)
121 #endif /* CONFIG_M5271 */
124 #include <asm/immap_5272.h>
125 #include <asm/m5272.h>
127 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
129 #define CFG_SYS_INTR_BASE (MMAP_INTC)
130 #define CFG_SYS_NUM_IRQS (64)
134 #define CFG_SYS_UDELAY_BASE (MMAP_TMR0)
135 #define CFG_SYS_TMR_BASE (MMAP_TMR3)
136 #define CFG_SYS_TMRPND_REG (((volatile intctrl_t *)(CFG_SYS_INTR_BASE))->int_isr)
137 #define CFG_SYS_TMRINTR_NO (INT_TMR3)
138 #define CFG_SYS_TMRINTR_MASK (INT_ISR_INT24)
139 #define CFG_SYS_TMRINTR_PEND (0)
140 #define CFG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
141 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
143 #endif /* CONFIG_M5272 */
146 #include <asm/immap_5275.h>
147 #include <asm/m5275.h>
149 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
151 #define CFG_SYS_INTR_BASE (MMAP_INTC0)
152 #define CFG_SYS_NUM_IRQS (192)
156 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
157 #define CFG_SYS_TMR_BASE (MMAP_DTMR3)
158 #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
159 #define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
160 #define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
161 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
162 #define CFG_SYS_TMRINTR_PRI (0x1E)
163 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
165 #endif /* CONFIG_M5275 */
168 #include <asm/immap_5282.h>
169 #include <asm/m5282.h>
171 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
173 #define CFG_SYS_INTR_BASE (MMAP_INTC0)
174 #define CFG_SYS_NUM_IRQS (128)
178 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
179 #define CFG_SYS_TMR_BASE (MMAP_DTMR3)
180 #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
181 #define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
182 #define CFG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3)
183 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
184 #define CFG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
185 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
187 #endif /* CONFIG_M5282 */
190 #include <asm/immap_5307.h>
191 #include <asm/m5307.h>
193 #define CFG_SYS_UART_BASE (MMAP_UART0 + \
194 (CFG_SYS_UART_PORT * 0x40))
195 #define CFG_SYS_INTR_BASE (MMAP_INTC)
196 #define CFG_SYS_NUM_IRQS (64)
200 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
201 #define CFG_SYS_TMR_BASE (MMAP_DTMR1)
202 #define CFG_SYS_TMRPND_REG (((volatile intctrl_t *) \
203 (CFG_SYS_INTR_BASE))->ipr)
204 #define CFG_SYS_TMRINTR_NO (31)
205 #define CFG_SYS_TMRINTR_MASK (0x00000400)
206 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
207 #define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \
208 MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
209 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
211 #endif /* CONFIG_M5307 */
213 #if defined(CONFIG_MCF5301x)
214 #include <asm/immap_5301x.h>
215 #include <asm/m5301x.h>
217 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
221 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
222 #define CFG_SYS_TMR_BASE (MMAP_DTMR1)
223 #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
224 #define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
225 #define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
226 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
227 #define CFG_SYS_TMRINTR_PRI (6)
228 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
231 #define CFG_SYS_INTR_BASE (MMAP_INTC0)
232 #define CFG_SYS_NUM_IRQS (128)
233 #endif /* CONFIG_M5301x */
235 #if defined(CONFIG_M5329) || defined(CONFIG_M5373)
236 #include <asm/immap_5329.h>
237 #include <asm/m5329.h>
239 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
243 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
244 #define CFG_SYS_TMR_BASE (MMAP_DTMR1)
245 #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
246 #define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
247 #define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
248 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
249 #define CFG_SYS_TMRINTR_PRI (6)
250 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
253 #define CFG_SYS_INTR_BASE (MMAP_INTC0)
254 #define CFG_SYS_NUM_IRQS (128)
255 #endif /* CONFIG_M5329 && CONFIG_M5373 */
257 #if defined(CONFIG_M54418)
258 #include <asm/immap_5441x.h>
259 #include <asm/m5441x.h>
261 #if (CFG_SYS_UART_PORT < 4)
262 #define CFG_SYS_UART_BASE (MMAP_UART0 + \
263 (CFG_SYS_UART_PORT * 0x4000))
265 #define CFG_SYS_UART_BASE (MMAP_UART4 + \
266 ((CFG_SYS_UART_PORT - 4) * 0x4000))
269 #define MMAP_DSPI MMAP_DSPI0
273 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
274 #define CFG_SYS_TMR_BASE (MMAP_DTMR1)
275 #define CFG_SYS_TMRPND_REG (((int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
276 #define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
277 #define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
278 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
279 #define CFG_SYS_TMRINTR_PRI (6)
280 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
283 #define CFG_SYS_INTR_BASE (MMAP_INTC0)
284 #define CFG_SYS_NUM_IRQS (192)
286 #endif /* CONFIG_M54418 */
289 #include <asm/immap_547x_8x.h>
290 #include <asm/m547x_8x.h>
292 #ifdef CONFIG_FSLDMAFEC
293 #define FEC0_RX_TASK 0
294 #define FEC0_TX_TASK 1
295 #define FEC0_RX_PRIORITY 6
296 #define FEC0_TX_PRIORITY 7
297 #define FEC0_RX_INIT 16
298 #define FEC0_TX_INIT 17
299 #define FEC1_RX_TASK 2
300 #define FEC1_TX_TASK 3
301 #define FEC1_RX_PRIORITY 6
302 #define FEC1_TX_PRIORITY 7
303 #define FEC1_RX_INIT 30
304 #define FEC1_TX_INIT 31
307 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100))
310 #define CFG_SYS_UDELAY_BASE (MMAP_SLT1)
311 #define CFG_SYS_TMR_BASE (MMAP_SLT0)
312 #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
313 #define CFG_SYS_TMRINTR_NO (INT0_HI_SLT0)
314 #define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
315 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
316 #define CFG_SYS_TMRINTR_PRI (0x1E)
317 #define CFG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
320 #define CFG_SYS_INTR_BASE (MMAP_INTC0)
321 #define CFG_SYS_NUM_IRQS (128)
324 #define CFG_SYS_PCI_BAR0 (0x40000000)
325 #define CFG_SYS_PCI_BAR1 (CFG_SYS_SDRAM_BASE)
326 #define CFG_SYS_PCI_TBATR0 (CFG_SYS_MBAR)
327 #define CFG_SYS_PCI_TBATR1 (CFG_SYS_SDRAM_BASE)
329 #endif /* CONFIG_M547x */
331 #endif /* __IMMAP_H */