1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright 2004-2012 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
12 #if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \
13 defined(CONFIG_MCF52x2) || defined(CONFIG_MCF5227x)
17 #if defined(CONFIG_MCF530x) || defined(CONFIG_MCF532x) || \
18 defined(CONFIG_MCF5301x)
22 #if defined(CONFIG_MCF5441x)
23 #define CONFIG_CF_V4E /* Four Extra ACRn */
26 /* ***** CACR ***** */
30 #define CF_CACR_CENB (1 << 31)
31 #define CF_CACR_CPD (1 << 28)
32 #define CF_CACR_CFRZ (1 << 27)
33 #define CF_CACR_CEIB (1 << 10)
34 #define CF_CACR_DCM (1 << 9)
35 #define CF_CACR_DBWE (1 << 8)
37 #if defined(CONFIG_MCF5249) || defined(CONFIG_MCF5253)
38 #define CF_CACR_DWP (1 << 6)
40 #define CF_CACR_CINV (1 << 24)
41 #define CF_CACR_DISI (1 << 23)
42 #define CF_CACR_DISD (1 << 22)
43 #define CF_CACR_INVI (1 << 21)
44 #define CF_CACR_INVD (1 << 20)
45 #define CF_CACR_DWP (1 << 5)
46 #define CF_CACR_EUSP (1 << 4)
47 #endif /* CONFIG_MCF5249 || CONFIG_MCF5253 */
49 #endif /* CONFIG_CF_V2 */
54 #define CF_CACR_EC (1 << 31)
55 #define CF_CACR_ESB (1 << 29)
56 #define CF_CACR_DPI (1 << 28)
57 #define CF_CACR_HLCK (1 << 27)
58 #define CF_CACR_CINVA (1 << 24)
59 #define CF_CACR_DNFB (1 << 10)
60 #define CF_CACR_DCM_UNMASK 0xFFFFFCFF
61 #define CF_CACR_DCM_WT (0 << 8)
62 #define CF_CACR_DCM_CB (1 << 8)
63 #define CF_CACR_DCM_P (2 << 8)
64 #define CF_CACR_DCM_IP (3 << 8)
65 #define CF_CACR_DW (1 << 5)
66 #define CF_CACR_EUSP (1 << 4)
68 #endif /* CONFIG_CF_V3 */
71 #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
73 #define CF_CACR_DEC (1 << 31)
74 #define CF_CACR_DW (1 << 30)
75 #define CF_CACR_DESB (1 << 29)
76 #define CF_CACR_DDPI (1 << 28)
77 #define CF_CACR_DHLCK (1 << 27)
78 #define CF_CACR_DDCM_UNMASK (0xF9FFFFFF)
79 #define CF_CACR_DDCM_WT (0 << 25)
80 #define CF_CACR_DDCM_CB (1 << 25)
81 #define CF_CACR_DDCM_P (2 << 25)
82 #define CF_CACR_DDCM_IP (3 << 25)
83 #define CF_CACR_DCINVA (1 << 24)
85 #define CF_CACR_DDSP (1 << 23)
86 #define CF_CACR_BEC (1 << 19)
87 #define CF_CACR_BCINVA (1 << 18)
88 #define CF_CACR_IEC (1 << 15)
89 #define CF_CACR_DNFB (1 << 13)
90 #define CF_CACR_IDPI (1 << 12)
91 #define CF_CACR_IHLCK (1 << 11)
92 #define CF_CACR_IDCM (1 << 10)
93 #define CF_CACR_ICINVA (1 << 8)
94 #define CF_CACR_IDSP (1 << 7)
95 #define CF_CACR_EUSP (1 << 5)
97 #if defined(CONFIG_MCF5445x) || defined(CONFIG_MCF5441x)
98 #define CF_CACR_IVO (1 << 20)
99 #define CF_CACR_SPA (1 << 14)
101 #define CF_CACR_DF (1 << 4)
104 #endif /* CONFIG_CF_V4 */
106 /* ***** ACR ***** */
107 #define CF_ACR_ADR_UNMASK (0x00FFFFFF)
108 #define CF_ACR_ADR(x) ((x & 0xFF) << 24)
109 #define CF_ACR_ADRMSK_UNMASK (0xFF00FFFF)
110 #define CF_ACR_ADRMSK(x) ((x & 0xFF) << 16)
111 #define CF_ACR_EN (1 << 15)
112 #define CF_ACR_SM_UNMASK (0xFFFF9FFF)
113 #define CF_ACR_SM_UM (0 << 13)
114 #define CF_ACR_SM_SM (1 << 13)
115 #define CF_ACR_SM_ALL (3 << 13)
116 #define CF_ACR_WP (1 << 2)
120 #define CF_ACR_CM (1 << 6)
121 #define CF_ACR_BWE (1 << 5)
124 #define CF_ACR_CM_UNMASK (0xFFFFFF9F)
125 #define CF_ACR_CM_WT (0 << 5)
126 #define CF_ACR_CM_CB (1 << 5)
127 #define CF_ACR_CM_P (2 << 5)
128 #define CF_ACR_CM_IP (3 << 5)
129 #endif /* CONFIG_CF_V2 */
132 #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
133 #define CF_ACR_AMM (1 << 10)
134 #define CF_ACR_SP (1 << 3)
135 #endif /* CONFIG_CF_V4 */
138 #ifndef CONFIG_SYS_CACHE_ICACR
139 #define CONFIG_SYS_CACHE_ICACR 0
142 #ifndef CONFIG_SYS_CACHE_DCACR
143 #ifdef CONFIG_SYS_CACHE_ICACR
144 #define CONFIG_SYS_CACHE_DCACR CONFIG_SYS_CACHE_ICACR
146 #define CONFIG_SYS_CACHE_DCACR 0
150 #ifndef CONFIG_SYS_CACHE_ACR0
151 #define CONFIG_SYS_CACHE_ACR0 0
154 #ifndef CONFIG_SYS_CACHE_ACR1
155 #define CONFIG_SYS_CACHE_ACR1 0
158 #ifndef CONFIG_SYS_CACHE_ACR2
159 #define CONFIG_SYS_CACHE_ACR2 0
162 #ifndef CONFIG_SYS_CACHE_ACR3
163 #define CONFIG_SYS_CACHE_ACR3 0
166 #ifndef CONFIG_SYS_CACHE_ACR4
167 #define CONFIG_SYS_CACHE_ACR4 0
170 #ifndef CONFIG_SYS_CACHE_ACR5
171 #define CONFIG_SYS_CACHE_ACR5 0
174 #ifndef CONFIG_SYS_CACHE_ACR6
175 #define CONFIG_SYS_CACHE_ACR6 0
178 #ifndef CONFIG_SYS_CACHE_ACR7
179 #define CONFIG_SYS_CACHE_ACR7 0
182 #define CF_ADDRMASK(x) (((x > 0x10) ? ((x >> 4) - 1) : (x)) << 16)
184 #ifndef __ASSEMBLY__ /* put C only stuff in this section */
186 void icache_invalid(void);
187 void dcache_invalid(void);
192 * m68k uses 16 byte L1 data cache line sizes. Use this for DMA buffer
193 * alignment unless the board configuration has specified a new value.
195 #ifdef CONFIG_SYS_CACHELINE_SIZE
196 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
198 #define ARCH_DMA_MINALIGN 16
201 #endif /* __CACHE_H */