2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
5 * Copyright 2010-2012 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm-offsets.h>
14 #include <timestamp.h>
16 #include <asm/cache.h>
18 #ifndef CONFIG_IDENT_STRING
19 #define CONFIG_IDENT_STRING ""
26 move.w #0x2700,%sr; /* disable intrs */ \
27 subl #60,%sp; /* space for 15 regs */ \
28 moveml %d0-%d7/%a0-%a6,%sp@;
31 moveml %sp@,%d0-%d7/%a0-%a6; \
32 addl #60,%sp; /* space for 15 regs */ \
35 #if defined(CONFIG_SERIAL_BOOT)
36 #define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + \
37 CONFIG_SYS_INIT_RAM_ADDR)
38 #define ASM_DRAMINIT_N (asm_dram_init - CONFIG_SYS_TEXT_BASE)
39 #define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + \
40 CONFIG_SYS_INIT_RAM_ADDR)
46 * Vector table. This is used for initial platform startup.
47 * These vectors are to catch any un-intended traps.
50 #if defined(CONFIG_SERIAL_BOOT)
52 INITSP: .long 0 /* Initial SP */
54 INITPC: .long ASM_DRAMINIT /* Initial PC */
56 #ifdef CONFIG_SYS_NAND_BOOT
57 INITPC: .long ASM_DRAMINIT_N /* Initial PC */
62 INITSP: .long 0 /* Initial SP */
63 INITPC: .long _START /* Initial PC */
68 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
69 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
73 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
76 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
78 #if !defined(CONFIG_SERIAL_BOOT)
82 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
83 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
87 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
88 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
91 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
92 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
93 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
94 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
95 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
96 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
97 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
98 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
101 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
102 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
103 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
104 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
105 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
106 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
107 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
108 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
111 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
112 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
113 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
114 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
115 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
116 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
117 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
118 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
121 #if defined(CONFIG_SERIAL_BOOT)
122 /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
124 .long 0x00000000 /* checksum, not yet implemented */
125 .long 0x00040000 /* image length */
126 .long CONFIG_SYS_TEXT_BASE /* image to be relocated at */
129 move.w #0x2700,%sr /* Mask off Interrupt */
131 #ifdef CONFIG_SYS_NAND_BOOT
132 /* for assembly stack */
133 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
136 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
141 move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0
144 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
147 /* initialize general use internal ram */
149 move.l #(ICACHE_STATUS), %a1 /* icache */
150 move.l #(DCACHE_STATUS), %a2 /* dcache */
154 /* invalidate and disable cache */
155 move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
156 movec %d0, %CACR /* Invalidate cache */
163 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
166 /* Must disable global address */
167 move.l #0xFC008000, %a1
168 move.l #(CONFIG_SYS_CS0_BASE), (%a1)
169 move.l #0xFC008008, %a1
170 move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
171 move.l #0xFC008004, %a1
172 move.l #(CONFIG_SYS_CS0_MASK), (%a1)
173 #endif /* CONFIG_CF_SBF */
175 #ifdef CONFIG_MCF5441x
176 /* TC: enable all peripherals,
177 in the future only enable certain peripherals */
178 move.l #0xFC04002D, %a1
180 #if defined(CONFIG_CF_SBF)
181 move.b #23, (%a1) /* dspi */
183 move.b #46, (%a1) /* DDR */
186 move.l #0xEC094060, %a1
189 /* use vco instead of cpu*2 clock for ddr clock */
190 move.l #0xEC09001A, %a1
191 move.w #0xE01D, (%a1)
194 move.l #0xFC0B8180, %a1
195 move.l #0x00000000, (%a1)
196 move.l #0x40000000, (%a1)
198 move.l #0xFC0B81AC, %a1
199 move.l #0x01030203, (%a1)
201 move.l #0xFC0B8000, %a1
202 move.l #0x01010101, (%a1)+ /* 0x00 */
203 move.l #0x00000101, (%a1)+ /* 0x04 */
204 move.l #0x01010100, (%a1)+ /* 0x08 */
205 move.l #0x01010000, (%a1)+ /* 0x0C */
206 move.l #0x00010101, (%a1)+ /* 0x10 */
207 move.l #0xFC0B8018, %a1
208 move.l #0x00010100, (%a1)+ /* 0x18 */
209 move.l #0x00000001, (%a1)+ /* 0x1C */
210 move.l #0x01000001, (%a1)+ /* 0x20 */
211 move.l #0x00000100, (%a1)+ /* 0x24 */
212 move.l #0x00010001, (%a1)+ /* 0x28 */
213 move.l #0x00000200, (%a1)+ /* 0x2C */
214 move.l #0x01000002, (%a1)+ /* 0x30 */
215 move.l #0x00000000, (%a1)+ /* 0x34 */
216 move.l #0x00000100, (%a1)+ /* 0x38 */
217 move.l #0x02000100, (%a1)+ /* 0x3C */
218 move.l #0x02000407, (%a1)+ /* 0x40 */
219 move.l #0x02030007, (%a1)+ /* 0x44 */
220 move.l #0x02000100, (%a1)+ /* 0x48 */
221 move.l #0x0A030203, (%a1)+ /* 0x4C */
222 move.l #0x00020708, (%a1)+ /* 0x50 */
223 move.l #0x00050008, (%a1)+ /* 0x54 */
224 move.l #0x04030002, (%a1)+ /* 0x58 */
225 move.l #0x00000004, (%a1)+ /* 0x5C */
226 move.l #0x020A0000, (%a1)+ /* 0x60 */
227 move.l #0x0C00000E, (%a1)+ /* 0x64 */
228 move.l #0x00002004, (%a1)+ /* 0x68 */
229 move.l #0x00000000, (%a1)+ /* 0x6C */
230 move.l #0x00100010, (%a1)+ /* 0x70 */
231 move.l #0x00100010, (%a1)+ /* 0x74 */
232 move.l #0x00000000, (%a1)+ /* 0x78 */
233 move.l #0x07990000, (%a1)+ /* 0x7C */
234 move.l #0xFC0B80A0, %a1
235 move.l #0x00000000, (%a1)+ /* 0xA0 */
236 move.l #0x00C80064, (%a1)+ /* 0xA4 */
237 move.l #0x44520002, (%a1)+ /* 0xA8 */
238 move.l #0x00C80023, (%a1)+ /* 0xAC */
239 move.l #0xFC0B80B4, %a1
240 move.l #0x0000C350, (%a1) /* 0xB4 */
241 move.l #0xFC0B80E0, %a1
242 move.l #0x04000000, (%a1)+ /* 0xE0 */
243 move.l #0x03000304, (%a1)+ /* 0xE4 */
244 move.l #0x40040000, (%a1)+ /* 0xE8 */
245 move.l #0xC0004004, (%a1)+ /* 0xEC */
246 move.l #0x0642C000, (%a1)+ /* 0xF0 */
247 move.l #0x00000642, (%a1)+ /* 0xF4 */
248 move.l #0xFC0B8024, %a1
250 move.l #0x01000100, (%a1) /* 0x24 */
254 #endif /* CONFIG_MCF5441x */
256 #ifdef CONFIG_MCF5445x
257 /* Dram Initialization a1, a2, and d0 */
259 move.l #0xFC0A4074, %a1
260 move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
263 /* SDRAM Chip 0 and 1 */
264 move.l #0xFC0B8110, %a1
265 move.l #0xFC0B8114, %a2
267 /* calculate the size */
269 move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
270 #ifdef CONFIG_SYS_SDRAM_BASE1
279 #ifdef CONFIG_SYS_NAND_BOOT
280 beq asm_nand_chk_status
282 /* SDRAM Chip 0 and 1 */
283 move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
285 #ifdef CONFIG_SYS_SDRAM_BASE1
286 move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
291 /* dram cfg1 and cfg2 */
292 move.l #0xFC0B8008, %a1
293 move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
295 move.l #0xFC0B800C, %a2
296 move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
299 move.l #0xFC0B8000, %a1 /* Mode */
300 move.l #0xFC0B8004, %a2 /* Ctrl */
303 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
306 #ifdef CONFIG_M54455EVB
308 move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
310 move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
318 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
321 /* Perform two refresh cycles */
322 move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
328 #ifdef CONFIG_M54455EVB
329 move.l #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1)
331 #elif defined(CONFIG_M54451EVB)
333 move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
335 move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
341 move.l #(CONFIG_SYS_SDRAM_CTRL), %d1
342 and.l #0x7FFFFFFF, %d1
343 #ifdef CONFIG_M54455EVB
344 or.l #0x10000C00, %d1
345 #elif defined(CONFIG_M54451EVB)
346 or.l #0x10000C00, %d1
353 #endif /* CONFIG_MCF5445x */
357 * DSPI Initialization
358 * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
364 /* Enable pins for DSPI mode - chip-selects are enabled later */
366 #ifdef CONFIG_MCF5441x
367 move.l #0xEC09404E, %a1
368 move.l #0xEC09404F, %a2
373 #ifdef CONFIG_MCF5445x
374 move.l #0xFC0A4063, %a0
377 /* Configure DSPI module */
378 move.l #0xFC05C000, %a0
379 move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
381 move.l #0xFC05C00C, %a0
382 #ifdef CONFIG_MCF5441x
383 move.l #0x3E000016, (%a0)
385 #ifdef CONFIG_MCF5445x
386 move.l #0x3E000011, (%a0)
389 move.l #0xFC05C034, %a2 /* dtfr */
390 move.l #0xFC05C03B, %a3 /* drfr */
392 move.l #(ASM_SBF_IMG_HDR + 4), %a1
396 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
397 move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
399 move.l #0xFC05C02C, %a1 /* dspi status */
401 /* Issue commands and address */
402 move.l #0x8002000B, %d2 /* Fast Read Cmd */
403 jsr asm_dspi_wr_status
404 jsr asm_dspi_rd_status
406 move.l #0x80020000, %d2 /* Address byte 2 */
407 jsr asm_dspi_wr_status
408 jsr asm_dspi_rd_status
410 move.l #0x80020000, %d2 /* Address byte 1 */
411 jsr asm_dspi_wr_status
412 jsr asm_dspi_rd_status
414 move.l #0x80020000, %d2 /* Address byte 0 */
415 jsr asm_dspi_wr_status
416 jsr asm_dspi_rd_status
418 move.l #0x80020000, %d2 /* Dummy Wr and Rd */
419 jsr asm_dspi_wr_status
420 jsr asm_dspi_rd_status
422 /* Transfer serial boot header to sram */
424 move.l #0x80020000, %d2
425 jsr asm_dspi_wr_status
426 jsr asm_dspi_rd_status
428 move.b %d1, (%a0) /* read, copy to dst */
430 add.l #1, %a0 /* inc dst by 1 */
431 sub.l #1, %d4 /* dec cnt by 1 */
432 bne asm_dspi_rd_loop1
434 /* Transfer u-boot from serial flash to memory */
436 move.l #0x80020000, %d2
437 jsr asm_dspi_wr_status
438 jsr asm_dspi_rd_status
440 move.b %d1, (%a4) /* read, copy to dst */
442 add.l #1, %a4 /* inc dst by 1 */
443 sub.l #1, %d5 /* dec cnt by 1 */
444 bne asm_dspi_rd_loop2
446 move.l #0x00020000, %d2 /* Terminate */
447 jsr asm_dspi_wr_status
448 jsr asm_dspi_rd_status
450 /* jump to memory and execute */
451 move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0
455 move.l (%a1), %d0 /* status */
456 and.l #0x0000F000, %d0
457 cmp.l #0x00003000, %d0
458 bgt asm_dspi_wr_status
464 move.l (%a1), %d0 /* status */
465 and.l #0x000000F0, %d0
468 beq asm_dspi_rd_status
472 #endif /* CONFIG_CF_SBF */
474 #ifdef CONFIG_SYS_NAND_BOOT
475 /* copy 4 boot pages to dram as soon as possible */
476 /* each page is 996 bytes (1056 total with 60 ECC bytes */
477 move.l #0x00000000, %a1 /* src */
478 move.l #CONFIG_SYS_TEXT_BASE, %a2 /* dst */
479 move.l #0x3E0, %d0 /* sz in long */
482 move.l (%a1)+, (%a2)+
484 bne asm_boot_nand_copy
486 /* jump to memory and execute */
487 move.l #(asm_nand_init), %a0
491 /* exit nand boot-mode */
492 move.l #0xFC0FFF30, %a1
493 or.l #0x00000040, %d1
496 /* initialize general use internal ram */
498 move.l #(CACR_STATUS), %a1 /* CACR */
499 move.l #(ICACHE_STATUS), %a2 /* icache */
500 move.l #(DCACHE_STATUS), %a3 /* dcache */
505 /* invalidate and disable cache */
506 move.l #0x01004100, %d0 /* Invalidate cache cmd */
507 movec %d0, %CACR /* Invalidate cache */
514 /* Must disable global address */
515 move.l #0xFC008000, %a1
516 move.l #(CONFIG_SYS_CS0_BASE), (%a1)
517 move.l #0xFC008008, %a1
518 move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
519 move.l #0xFC008004, %a1
520 move.l #(CONFIG_SYS_CS0_MASK), (%a1)
522 /* NAND port configuration */
523 move.l #0xEC094048, %a1
529 move.l #0xFC0FFF38, %a1 /* isr */
530 move.l #0x000e0000, (%a1)
531 move.l #0xFC0FFF08, %a2
532 move.l #0x00000000, (%a2)+ /* car */
533 move.l #0x11000000, (%a2)+ /* rar */
534 move.l #0x00000000, (%a2)+ /* rpt */
535 move.l #0x00000000, (%a2)+ /* rai */
536 move.l #0xFC0FFF2c, %a2 /* cfg */
537 move.l #0x00000000, (%a2)+ /* secsz */
538 move.l #0x000e0681, (%a2)+
539 move.l #0xFC0FFF04, %a2 /* cmd2 */
540 move.l #0xFF404001, (%a2)
541 move.l #0x000e0000, (%a1)
547 move.l #0xFC0FFF00, %a1
548 move.l #0x30700000, (%a1)+ /* cmd1 */
549 move.l #0x007EF000, (%a1)+ /* cmd2 */
551 move.l #0xFC0FFF2C, %a1
552 move.l #0x00000841, (%a1)+ /* secsz */
553 move.l #0x000e0681, (%a1)+ /* cfg */
555 move.l #100, %d4 /* 100 pages ~200KB */
556 move.l #4, %d2 /* start at 4 */
557 move.l #0xFC0FFF04, %a0 /* cmd2 */
558 move.l #0xFC0FFF0C, %a1 /* rar */
559 move.l #(CONFIG_SYS_TEXT_BASE + 0xF80), %a2
562 move.l #0x11000000, %d0 /* rar */
567 move.l (%a0), %d0 /* cmd2 */
575 move.l #0xFC0FFF38, %a4 /* isr */
577 and.l #0x40000000, %d0
579 beq asm_nand_chk_status
581 move.l #0xFC0FFF38, %a4 /* isr */
583 or.l #0x000E0000, %d0
587 move.l #0xFC0FC000, %a3 /* buf 1 */
589 move.l (%a3)+, (%a2)+
596 /* jump to memory and execute */
597 move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0
600 #endif /* CONFIG_SYS_NAND_BOOT */
607 #endif /* CONFIG_CF_SBF || CONFIG_NAND_U_BOOT */
613 #if !defined(CONFIG_SERIAL_BOOT)
616 move.w #0x2700,%sr /* Mask off Interrupt */
618 /* Set vector base register at the beginning of the Flash */
619 move.l #CONFIG_SYS_FLASH_BASE, %d0
622 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
625 /* initialize general use internal ram */
627 move.l #(ICACHE_STATUS), %a1 /* icache */
628 move.l #(DCACHE_STATUS), %a2 /* dcache */
632 /* invalidate and disable cache */
633 move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
634 movec %d0, %CACR /* Invalidate cache */
641 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
645 /* put relocation table address to a5 */
646 move.l #__got_start, %a5
648 /* setup stack initially on top of internal static ram */
649 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
652 * if configured, malloc_f arena will be reserved first,
653 * then (and always) gd struct space will be reserved
656 move.l #board_init_f_alloc_reserve, %a1
659 /* update stack and frame-pointers */
663 /* initialize reserved area */
665 move.l #board_init_f_init_reserve, %a1
668 /* run low-level CPU init code (from flash) */
669 move.l #cpu_init_f, %a1
672 /* run low-level board init code (from flash) */
674 move.l #board_init_f, %a1
677 /* board_init_f() does not return */
679 /******************************************************************************/
682 * void relocate_code (addr_sp, gd, addr_moni)
684 * This "function" does not return, instead it continues in RAM
685 * after relocating the monitor code.
689 * r5 = length in bytes
695 move.l 8(%a6), %sp /* set new stack pointer */
697 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
698 move.l 16(%a6), %a0 /* Save copy of Destination Address */
700 move.l #CONFIG_SYS_MONITOR_BASE, %a1
701 move.l #__init_end, %a2
704 /* copy the code to RAM */
706 move.l (%a1)+, (%a3)+
711 * We are done. Do not return, instead branch to second part of board
712 * initialization, now running from RAM.
715 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
722 * Now clear BSS segment
725 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
727 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
734 * fix got table in RAM
737 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
738 move.l %a1,%a5 /* fix got pointer register a5 */
741 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
751 /* calculate relative jump to board_init_r in ram */
753 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
755 /* set parameters for board_init_r */
756 move.l %a0,-(%sp) /* dest_addr */
757 move.l %d0,-(%sp) /* gd */
760 /******************************************************************************/
783 /******************************************************************************/
785 .globl version_string
787 .ascii U_BOOT_VERSION_STRING, "\0"