3 * Josef Baumgartner <josef.baumgartner@telex.de>
7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
9 * Arcturus Networks Inc. <www.arcturusnetworks.com>
11 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
12 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
13 * Hayden Fraser (Hayden.Fraser@freescale.com)
16 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
18 * See file CREDITS for list of people who contributed to this
21 * This program is free software; you can redistribute it and/or
22 * modify it under the terms of the GNU General Public License as
23 * published by the Free Software Foundation; either version 2 of
24 * the License, or (at your option) any later version.
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
31 * You should have received a copy of the GNU General Public License
32 * along with this program; if not, write to the Free Software
33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
39 #include <asm/immap.h>
42 #if defined(CONFIG_CMD_NET)
49 /* Only 5272 Flexbus chipselect is different from the rest */
52 fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
54 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
55 && defined(CONFIG_SYS_CS0_CTRL))
56 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
57 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
58 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
60 #warning "Chip Select 0 are not initialized/used"
62 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
63 && defined(CONFIG_SYS_CS1_CTRL))
64 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
65 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
66 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
68 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
69 && defined(CONFIG_SYS_CS2_CTRL))
70 out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
71 out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
72 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
74 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
75 && defined(CONFIG_SYS_CS3_CTRL))
76 out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
77 out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
78 out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
80 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
81 && defined(CONFIG_SYS_CS4_CTRL))
82 out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
83 out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
84 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
86 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
87 && defined(CONFIG_SYS_CS5_CTRL))
88 out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
89 out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
90 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
92 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
93 && defined(CONFIG_SYS_CS6_CTRL))
94 out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
95 out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
96 out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
98 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
99 && defined(CONFIG_SYS_CS7_CTRL))
100 out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
101 out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
102 out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
107 #if defined(CONFIG_M5208)
108 void cpu_init_f(void)
110 scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
112 #ifndef CONFIG_WATCHDOG
113 wdog_t *wdg = (wdog_t *) MMAP_WDOG;
115 /* Disable the watchdog if we aren't using it */
116 out_be16(&wdg->cr, 0);
119 out_be32(&scm1->mpr, 0x77777777);
120 out_be32(&scm1->pacra, 0);
121 out_be32(&scm1->pacrb, 0);
122 out_be32(&scm1->pacrc, 0);
123 out_be32(&scm1->pacrd, 0);
124 out_be32(&scm1->pacre, 0);
125 out_be32(&scm1->pacrf, 0);
127 /* FlexBus Chipselect */
133 /* initialize higher level parts of CPU like timers */
139 void uart_port_conf(int port)
141 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
146 clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
147 setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
150 clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
151 setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
154 #ifdef CONFIG_SYS_UART2_PRI_GPIO
155 clrbits_8(&gpio->par_timer,
156 ~(GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK));
157 setbits_8(&gpio->par_timer,
158 GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
160 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
161 clrbits_8(&gpio->par_feci2c,
162 ~(GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK));
163 setbits_8(&gpio->par_feci2c,
164 GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
166 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
167 clrbits_8(&gpio->par_feci2c,
168 ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK));
169 setbits_8(&gpio->par_feci2c,
170 GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
176 #if defined(CONFIG_CMD_NET)
177 int fecpin_setclear(struct eth_device *dev, int setclear)
179 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
182 setbits_8(&gpio->par_fec,
183 GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
184 setbits_8(&gpio->par_feci2c,
185 GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO);
187 clrbits_8(&gpio->par_fec,
188 ~(GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK));
189 clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII_UNMASK);
193 #endif /* CONFIG_CMD_NET */
194 #endif /* CONFIG_M5208 */
196 #if defined(CONFIG_M5253)
198 * Breath some life into the CPU...
200 * Set up the memory map,
201 * initialize a bunch of registers,
202 * initialize the UPM's
204 void cpu_init_f(void)
206 mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */
207 mbar_writeByte(MCFSIM_SYPCR, 0x00);
208 mbar_writeByte(MCFSIM_SWIVR, 0x0f);
209 mbar_writeByte(MCFSIM_SWSR, 0x00);
210 mbar_writeByte(MCFSIM_SWDICR, 0x00);
211 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
212 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
213 mbar_writeByte(MCFSIM_I2CICR, 0x00);
214 mbar_writeByte(MCFSIM_UART1ICR, 0x00);
215 mbar_writeByte(MCFSIM_UART2ICR, 0x00);
216 mbar_writeByte(MCFSIM_ICR6, 0x00);
217 mbar_writeByte(MCFSIM_ICR7, 0x00);
218 mbar_writeByte(MCFSIM_ICR8, 0x00);
219 mbar_writeByte(MCFSIM_ICR9, 0x00);
220 mbar_writeByte(MCFSIM_QSPIICR, 0x00);
222 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
223 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
224 mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
226 /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
228 /* FlexBus Chipselect */
231 #ifdef CONFIG_FSL_I2C
232 CONFIG_SYS_I2C_PINMUX_REG =
233 CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
234 CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
235 #ifdef CONFIG_SYS_I2C2_OFFSET
236 CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
237 CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
241 /* enable instruction cache now */
245 /*initialize higher level parts of CPU like timers */
251 void uart_port_conf(int port)
253 u32 *par = (u32 *) MMAP_PAR;
258 clrbits_be32(par, 0x00180000);
259 setbits_be32(par, 0x00180000);
262 clrbits_be32(par, 0x00000003);
263 clrbits_be32(par, 0xFFFFFFFC);
267 #endif /* #if defined(CONFIG_M5253) */
269 #if defined(CONFIG_M5271)
270 void cpu_init_f(void)
272 #ifndef CONFIG_WATCHDOG
273 /* Disable the watchdog if we aren't using it */
274 mbar_writeShort(MCF_WTM_WCR, 0);
277 /* FlexBus Chipselect */
280 #ifdef CONFIG_SYS_MCF_SYNCR
281 /* Set clockspeed according to board header file */
282 mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR);
284 /* Set clockspeed to 100MHz */
285 mbar_writeLong(MCF_FMPLL_SYNCR,
286 MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
288 while (!(mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK)) ;
292 * initialize higher level parts of CPU like timers
299 void uart_port_conf(int port)
306 temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xFFF3;
307 temp |= (MCF_GPIO_PAR_UART_U0TXD | MCF_GPIO_PAR_UART_U0RXD);
308 mbar_writeShort(MCF_GPIO_PAR_UART, temp);
311 temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xF0FF;
312 temp |= (MCF_GPIO_PAR_UART_U1RXD_UART1 | MCF_GPIO_PAR_UART_U1TXD_UART1);
313 mbar_writeShort(MCF_GPIO_PAR_UART, temp);
316 temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xCFFF;
318 mbar_writeShort(MCF_GPIO_PAR_UART, temp);
323 #if defined(CONFIG_CMD_NET)
324 int fecpin_setclear(struct eth_device *dev, int setclear)
327 /* Enable Ethernet pins */
328 mbar_writeByte(MCF_GPIO_PAR_FECI2C,
329 (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0));
335 #endif /* CONFIG_CMD_NET */
338 #if defined(CONFIG_M5272)
340 * Breath some life into the CPU...
342 * Set up the memory map,
343 * initialize a bunch of registers,
344 * initialize the UPM's
346 void cpu_init_f(void)
348 /* if we come from RAM we assume the CPU is
349 * already initialized.
351 #ifndef CONFIG_MONITOR_IS_IN_RAM
352 sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
353 gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
354 csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
356 out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR);
357 out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR);
360 out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT);
361 out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR);
362 out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT);
363 out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT);
364 out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR);
365 out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT);
366 out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT);
368 /* Memory Controller: */
369 out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM);
370 out_be32(&csctrl->cs_or0, CONFIG_SYS_OR0_PRELIM);
372 #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
373 out_be32(&csctrl->cs_br1, CONFIG_SYS_BR1_PRELIM);
374 out_be32(&csctrl->cs_or1, CONFIG_SYS_OR1_PRELIM);
377 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
378 out_be32(&csctrl->cs_br2, CONFIG_SYS_BR2_PRELIM);
379 out_be32(&csctrl->cs_or2, CONFIG_SYS_OR2_PRELIM);
382 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
383 out_be32(&csctrl->cs_br3, CONFIG_SYS_BR3_PRELIM);
384 out_be32(&csctrl->cs_or3, CONFIG_SYS_OR3_PRELIM);
387 #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
388 out_be32(&csctrl->cs_br4, CONFIG_SYS_BR4_PRELIM);
389 out_be32(&csctrl->cs_or4, CONFIG_SYS_OR4_PRELIM);
392 #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
393 out_be32(&csctrl->cs_br5, CONFIG_SYS_BR5_PRELIM);
394 out_be32(&csctrl->cs_or5, CONFIG_SYS_OR5_PRELIM);
397 #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
398 out_be32(&csctrl->cs_br6, CONFIG_SYS_BR6_PRELIM);
399 out_be32(&csctrl->cs_or6, CONFIG_SYS_OR6_PRELIM);
402 #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
403 out_be32(&csctrl->cs_br7, CONFIG_SYS_BR7_PRELIM);
404 out_be32(&csctrl->cs_or7, CONFIG_SYS_OR7_PRELIM);
407 #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
409 /* enable instruction cache now */
415 * initialize higher level parts of CPU like timers
422 void uart_port_conf(int port)
424 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
429 clrbits_be32(&gpio->gpio_pbcnt,
430 GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
431 setbits_be32(&gpio->gpio_pbcnt,
432 GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
435 clrbits_be32(&gpio->gpio_pdcnt,
436 GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
437 setbits_be32(&gpio->gpio_pdcnt,
438 GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
443 #if defined(CONFIG_CMD_NET)
444 int fecpin_setclear(struct eth_device *dev, int setclear)
446 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
449 setbits_be32(&gpio->gpio_pbcnt,
450 GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
451 GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
452 GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
453 GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3);
458 #endif /* CONFIG_CMD_NET */
459 #endif /* #if defined(CONFIG_M5272) */
461 #if defined(CONFIG_M5275)
464 * Breathe some life into the CPU...
466 * Set up the memory map,
467 * initialize a bunch of registers,
468 * initialize the UPM's
470 void cpu_init_f(void)
473 * if we come from RAM we assume the CPU is
474 * already initialized.
477 #ifndef CONFIG_MONITOR_IS_IN_RAM
478 wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
479 gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
481 /* Kill watchdog so we can initialize the PLL */
482 out_be16(&wdog_reg->wcr, 0);
484 /* FlexBus Chipselect */
486 #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
488 #ifdef CONFIG_FSL_I2C
489 CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
490 CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
493 /* enable instruction cache now */
498 * initialize higher level parts of CPU like timers
505 void uart_port_conf(int port)
507 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
512 clrbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
513 setbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
516 clrbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
517 setbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
520 clrbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
521 setbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
526 #if defined(CONFIG_CMD_NET)
527 int fecpin_setclear(struct eth_device *dev, int setclear)
529 struct fec_info_s *info = (struct fec_info_s *) dev->priv;
530 gpio_t *gpio = (gpio_t *)MMAP_GPIO;
533 /* Enable Ethernet pins */
534 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
535 setbits_be16(&gpio->par_feci2c, 0x0f00);
536 setbits_8(&gpio->par_fec0hl, 0xc0);
538 setbits_be16(&gpio->par_feci2c, 0x00a0);
539 setbits_8(&gpio->par_fec1hl, 0xc0);
542 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
543 clrbits_be16(&gpio->par_feci2c, 0x0f00);
544 clrbits_8(&gpio->par_fec0hl, 0xc0);
546 clrbits_be16(&gpio->par_feci2c, 0x00a0);
547 clrbits_8(&gpio->par_fec1hl, 0xc0);
553 #endif /* CONFIG_CMD_NET */
554 #endif /* #if defined(CONFIG_M5275) */
556 #if defined(CONFIG_M5282)
558 * Breath some life into the CPU...
560 * Set up the memory map,
561 * initialize a bunch of registers,
562 * initialize the UPM's
564 void cpu_init_f(void)
566 #ifndef CONFIG_WATCHDOG
567 /* disable watchdog if we aren't using it */
571 #ifndef CONFIG_MONITOR_IS_IN_RAM
574 MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
575 MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
576 while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
578 MCFGPIO_PBCDPAR = 0xc0;
580 /* Set up the GPIO ports */
581 #ifdef CONFIG_SYS_PEPAR
582 MCFGPIO_PEPAR = CONFIG_SYS_PEPAR;
584 #ifdef CONFIG_SYS_PFPAR
585 MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
587 #ifdef CONFIG_SYS_PJPAR
588 MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
590 #ifdef CONFIG_SYS_PSDPAR
591 MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
593 #ifdef CONFIG_SYS_PASPAR
594 MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
596 #ifdef CONFIG_SYS_PEHLPAR
597 MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
599 #ifdef CONFIG_SYS_PQSPAR
600 MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
602 #ifdef CONFIG_SYS_PTCPAR
603 MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR;
605 #if defined(CONFIG_SYS_PORTTC)
606 MCFGPIO_PORTTC = CONFIG_SYS_PORTTC;
608 #if defined(CONFIG_SYS_DDRTC)
609 MCFGPIO_DDRTC = CONFIG_SYS_DDRTC;
611 #ifdef CONFIG_SYS_PTDPAR
612 MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
614 #ifdef CONFIG_SYS_PUAPAR
615 MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
618 #if defined(CONFIG_SYS_DDRD)
619 MCFGPIO_DDRD = CONFIG_SYS_DDRD;
621 #ifdef CONFIG_SYS_DDRUA
622 MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
625 /* FlexBus Chipselect */
628 #endif /* CONFIG_MONITOR_IS_IN_RAM */
630 /* defer enabling cache until boot (see do_go) */
631 /* icache_enable(); */
635 * initialize higher level parts of CPU like timers
642 void uart_port_conf(int port)
647 MCFGPIO_PUAPAR &= 0xFc;
648 MCFGPIO_PUAPAR |= 0x03;
651 MCFGPIO_PUAPAR &= 0xF3;
652 MCFGPIO_PUAPAR |= 0x0C;
655 MCFGPIO_PASPAR &= 0xFF0F;
656 MCFGPIO_PASPAR |= 0x00A0;
661 #if defined(CONFIG_CMD_NET)
662 int fecpin_setclear(struct eth_device *dev, int setclear)
665 MCFGPIO_PASPAR |= 0x0F00;
666 MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
668 MCFGPIO_PASPAR &= 0xF0FF;
669 MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
673 #endif /* CONFIG_CMD_NET */
676 #if defined(CONFIG_M5249)
678 * Breath some life into the CPU...
680 * Set up the memory map,
681 * initialize a bunch of registers,
682 * initialize the UPM's
684 void cpu_init_f(void)
687 * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
688 * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
689 * which is their primary function.
692 mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
693 mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
694 mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
695 mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
696 mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
697 mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
701 * You can verify these values by using dBug's 'ird'
702 * (Internal Register Display) command
706 mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
707 mbar_writeByte(MCFSIM_SYPCR, 0x00);
708 mbar_writeByte(MCFSIM_SWIVR, 0x0f);
709 mbar_writeByte(MCFSIM_SWSR, 0x00);
710 mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
711 mbar_writeByte(MCFSIM_SWDICR, 0x00);
712 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
713 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
714 mbar_writeByte(MCFSIM_I2CICR, 0x00);
715 mbar_writeByte(MCFSIM_UART1ICR, 0x00);
716 mbar_writeByte(MCFSIM_UART2ICR, 0x00);
717 mbar_writeByte(MCFSIM_ICR6, 0x00);
718 mbar_writeByte(MCFSIM_ICR7, 0x00);
719 mbar_writeByte(MCFSIM_ICR8, 0x00);
720 mbar_writeByte(MCFSIM_ICR9, 0x00);
721 mbar_writeByte(MCFSIM_QSPIICR, 0x00);
723 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
724 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
725 mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
726 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
728 /* Setup interrupt priorities for gpio7 */
729 /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
731 /* IDE Config registers */
732 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
733 mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
735 /* FlexBus Chipselect */
738 /* enable instruction cache now */
743 * initialize higher level parts of CPU like timers
750 void uart_port_conf(int port)
753 #endif /* #if defined(CONFIG_M5249) */