3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/immap.h>
33 #if defined(CONFIG_CMD_NET)
40 * Breath some life into the CPU...
42 * Set up the memory map,
43 * initialize a bunch of registers,
44 * initialize the UPM's
48 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
49 fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
50 wdog_t *wdog = (wdog_t *) MMAP_WDOG;
51 scm_t *scm = (scm_t *) MMAP_SCM;
53 /* watchdog is enabled by default - disable the watchdog */
54 #ifndef CONFIG_WATCHDOG
55 out_be16(&wdog->cr, 0);
58 out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
60 /* Port configuration */
61 out_8(&gpio->par_cs, 0);
63 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
64 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
65 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
66 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
69 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
70 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1);
71 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
72 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
73 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
76 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
77 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2);
78 out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
79 out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
80 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
83 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
84 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3);
85 out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
86 out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
87 out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
90 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
91 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4);
92 out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
93 out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
94 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
97 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
98 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5);
99 out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
100 out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
101 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
104 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL))
105 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6);
106 out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
107 out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
108 out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
111 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL))
112 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7);
113 out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
114 out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
115 out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
118 #ifdef CONFIG_FSL_I2C
119 CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
120 CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
127 * initialize higher level parts of CPU like timers
134 void uart_port_conf(int port)
136 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
141 clrbits_be16(&gpio->par_uart,
142 GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
143 setbits_be16(&gpio->par_uart,
144 GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
147 clrbits_be16(&gpio->par_uart,
148 GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK);
149 setbits_be16(&gpio->par_uart,
150 GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
153 #ifdef CONFIG_SYS_UART2_PRI_GPIO
154 clrbits_be16(&gpio->par_uart,
155 GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
156 setbits_be16(&gpio->par_uart,
157 GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
158 #elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
159 clrbits_8(&gpio->par_feci2c,
160 GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
161 setbits_8(&gpio->par_feci2c,
162 GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD);
168 #if defined(CONFIG_CMD_NET)
169 int fecpin_setclear(struct eth_device *dev, int setclear)
171 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
174 setbits_8(&gpio->par_feci2c,
175 GPIO_PAR_FECI2C_EMDC_FECEMDC |
176 GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
178 clrbits_8(&gpio->par_feci2c,
179 GPIO_PAR_FECI2C_EMDC_MASK |
180 GPIO_PAR_FECI2C_EMDIO_MASK);