arch/loongarch/kernel/head.S

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
   4  */
   5 #include <linux/init.h>
   6 #include <linux/threads.h>
   7
   8 #include <asm/addrspace.h>
   9 #include <asm/asm.h>
  10 #include <asm/asmmacro.h>
  11 #include <asm/regdef.h>
  12 #include <asm/loongarch.h>
  13 #include <asm/stackframe.h>
  14
  15 #ifdef CONFIG_EFI_STUB
  16
  17 #include "efi-header.S"
  18
  19         __HEAD
  20
  21 _head:
  22         .word   MZ_MAGIC                /* "MZ", MS-DOS header */
  23         .org    0x3c                    /* 0x04 ~ 0x3b reserved */
  24         .long   pe_header - _head       /* Offset to the PE header */
  25
  26 pe_header:
  27         __EFI_PE_HEADER
  28
  29 SYM_DATA(kernel_asize, .long _end - _text);
  30 SYM_DATA(kernel_fsize, .long _edata - _text);
  31 SYM_DATA(kernel_offset, .long kernel_offset - _text);
  32
  33 #endif
  34
  35         __REF
  36
  37         .align 12
  38
  39 SYM_CODE_START(kernel_entry)                    # kernel entry point
  40
  41         /* Config direct window and set PG */
  42         li.d            t0, CSR_DMW0_INIT       # UC, PLV0, 0x8000 xxxx xxxx xxxx
  43         csrwr           t0, LOONGARCH_CSR_DMWIN0
  44         li.d            t0, CSR_DMW1_INIT       # CA, PLV0, 0x9000 xxxx xxxx xxxx
  45         csrwr           t0, LOONGARCH_CSR_DMWIN1
  46
  47         /* We might not get launched at the address the kernel is linked to,
  48            so we jump there.  */
  49         la.abs          t0, 0f
  50         jr              t0
  51 0:
  52         /* Enable PG */
  53         li.w            t0, 0xb0                # PLV=0, IE=0, PG=1
  54         csrwr           t0, LOONGARCH_CSR_CRMD
  55         li.w            t0, 0x04                # PLV=0, PIE=1, PWE=0
  56         csrwr           t0, LOONGARCH_CSR_PRMD
  57         li.w            t0, 0x00                # FPE=0, SXE=0, ASXE=0, BTE=0
  58         csrwr           t0, LOONGARCH_CSR_EUEN
  59
  60         la              t0, __bss_start         # clear .bss
  61         st.d            zero, t0, 0
  62         la              t1, __bss_stop - LONGSIZE
  63 1:
  64         addi.d          t0, t0, LONGSIZE
  65         st.d            zero, t0, 0
  66         bne             t0, t1, 1b
  67
  68         la              t0, fw_arg0
  69         st.d            a0, t0, 0               # firmware arguments
  70         la              t0, fw_arg1
  71         st.d            a1, t0, 0
  72         la              t0, fw_arg2
  73         st.d            a2, t0, 0
  74
  75         /* KSave3 used for percpu base, initialized as 0 */
  76         csrwr           zero, PERCPU_BASE_KS
  77         /* GPR21 used for percpu base (runtime), initialized as 0 */
  78         move            u0, zero
  79
  80         la              tp, init_thread_union
  81         /* Set the SP after an empty pt_regs.  */
  82         PTR_LI          sp, (_THREAD_SIZE - 32 - PT_SIZE)
  83         PTR_ADD         sp, sp, tp
  84         set_saved_sp    sp, t0, t1
  85         PTR_ADDI        sp, sp, -4 * SZREG      # init stack pointer
  86
  87         bl              start_kernel
  88
  89 SYM_CODE_END(kernel_entry)
  90
  91 #ifdef CONFIG_SMP
  92
  93 /*
  94  * SMP slave cpus entry point.  Board specific code for bootstrap calls this
  95  * function after setting up the stack and tp registers.
  96  */
  97 SYM_CODE_START(smpboot_entry)
  98         li.d            t0, CSR_DMW0_INIT       # UC, PLV0
  99         csrwr           t0, LOONGARCH_CSR_DMWIN0
 100         li.d            t0, CSR_DMW1_INIT       # CA, PLV0
 101         csrwr           t0, LOONGARCH_CSR_DMWIN1
 102
 103         la.abs          t0, 0f
 104         jr              t0
 105 0:
 106         /* Enable PG */
 107         li.w            t0, 0xb0                # PLV=0, IE=0, PG=1
 108         csrwr           t0, LOONGARCH_CSR_CRMD
 109         li.w            t0, 0x04                # PLV=0, PIE=1, PWE=0
 110         csrwr           t0, LOONGARCH_CSR_PRMD
 111         li.w            t0, 0x00                # FPE=0, SXE=0, ASXE=0, BTE=0
 112         csrwr           t0, LOONGARCH_CSR_EUEN
 113
 114         la.abs          t0, cpuboot_data
 115         ld.d            sp, t0, CPU_BOOT_STACK
 116         ld.d            tp, t0, CPU_BOOT_TINFO
 117
 118         bl              start_secondary
 119 SYM_CODE_END(smpboot_entry)
 120
 121 #endif /* CONFIG_SMP */
 122
 123 SYM_ENTRY(kernel_entry_end, SYM_L_GLOBAL, SYM_A_NONE)