arch/loongarch/include/asm/loongarch.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
   4  */
   5 #ifndef _ASM_LOONGARCH_H
   6 #define _ASM_LOONGARCH_H
   7
   8 #include <linux/bits.h>
   9 #include <linux/linkage.h>
  10 #include <linux/types.h>
  11
  12 #ifndef __ASSEMBLY__
  13 #include <larchintrin.h>
  14
  15 /*
  16  * parse_r var, r - Helper assembler macro for parsing register names.
  17  *
  18  * This converts the register name in $n form provided in \r to the
  19  * corresponding register number, which is assigned to the variable \var. It is
  20  * needed to allow explicit encoding of instructions in inline assembly where
  21  * registers are chosen by the compiler in $n form, allowing us to avoid using
  22  * fixed register numbers.
  23  *
  24  * It also allows newer instructions (not implemented by the assembler) to be
  25  * transparently implemented using assembler macros, instead of needing separate
  26  * cases depending on toolchain support.
  27  *
  28  * Simple usage example:
  29  * __asm__ __volatile__("parse_r addr, %0\n\t"
  30  *                      "#invtlb op, 0, %0\n\t"
  31  *                      ".word ((0x6498000) | (addr << 10) | (0 << 5) | op)"
  32  *                      : "=r" (status);
  33  */
  34
  35 /* Match an individual register number and assign to \var */
  36 #define _IFC_REG(n)                             \
  37         ".ifc   \\r, $r" #n "\n\t"              \
  38         "\\var  = " #n "\n\t"                   \
  39         ".endif\n\t"
  40
  41 __asm__(".macro parse_r var r\n\t"
  42         "\\var  = -1\n\t"
  43         _IFC_REG(0)  _IFC_REG(1)  _IFC_REG(2)  _IFC_REG(3)
  44         _IFC_REG(4)  _IFC_REG(5)  _IFC_REG(6)  _IFC_REG(7)
  45         _IFC_REG(8)  _IFC_REG(9)  _IFC_REG(10) _IFC_REG(11)
  46         _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15)
  47         _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19)
  48         _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23)
  49         _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27)
  50         _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31)
  51         ".iflt  \\var\n\t"
  52         ".error \"Unable to parse register name \\r\"\n\t"
  53         ".endif\n\t"
  54         ".endm");
  55
  56 #undef _IFC_REG
  57
  58 /* CPUCFG */
  59 static inline u32 read_cpucfg(u32 reg)
  60 {
  61         return __cpucfg(reg);
  62 }
  63
  64 #endif /* !__ASSEMBLY__ */
  65
  66 #ifdef __ASSEMBLY__
  67
  68 /* LoongArch Registers */
  69 #define REG_ZERO        0x0
  70 #define REG_RA          0x1
  71 #define REG_TP          0x2
  72 #define REG_SP          0x3
  73 #define REG_A0          0x4 /* Reused as V0 for return value */
  74 #define REG_A1          0x5 /* Reused as V1 for return value */
  75 #define REG_A2          0x6
  76 #define REG_A3          0x7
  77 #define REG_A4          0x8
  78 #define REG_A5          0x9
  79 #define REG_A6          0xa
  80 #define REG_A7          0xb
  81 #define REG_T0          0xc
  82 #define REG_T1          0xd
  83 #define REG_T2          0xe
  84 #define REG_T3          0xf
  85 #define REG_T4          0x10
  86 #define REG_T5          0x11
  87 #define REG_T6          0x12
  88 #define REG_T7          0x13
  89 #define REG_T8          0x14
  90 #define REG_U0          0x15 /* Kernel uses it as percpu base */
  91 #define REG_FP          0x16
  92 #define REG_S0          0x17
  93 #define REG_S1          0x18
  94 #define REG_S2          0x19
  95 #define REG_S3          0x1a
  96 #define REG_S4          0x1b
  97 #define REG_S5          0x1c
  98 #define REG_S6          0x1d
  99 #define REG_S7          0x1e
 100 #define REG_S8          0x1f
 101
 102 #endif /* __ASSEMBLY__ */
 103
 104 /* Bit fields for CPUCFG registers */
 105 #define LOONGARCH_CPUCFG0               0x0
 106 #define  CPUCFG0_PRID                   GENMASK(31, 0)
 107
 108 #define LOONGARCH_CPUCFG1               0x1
 109 #define  CPUCFG1_ISGR32                 BIT(0)
 110 #define  CPUCFG1_ISGR64                 BIT(1)
 111 #define  CPUCFG1_PAGING                 BIT(2)
 112 #define  CPUCFG1_IOCSR                  BIT(3)
 113 #define  CPUCFG1_PABITS                 GENMASK(11, 4)
 114 #define  CPUCFG1_VABITS                 GENMASK(19, 12)
 115 #define  CPUCFG1_UAL                    BIT(20)
 116 #define  CPUCFG1_RI                     BIT(21)
 117 #define  CPUCFG1_EP                     BIT(22)
 118 #define  CPUCFG1_RPLV                   BIT(23)
 119 #define  CPUCFG1_HUGEPG                 BIT(24)
 120 #define  CPUCFG1_IOCSRBRD               BIT(25)
 121 #define  CPUCFG1_MSGINT                 BIT(26)
 122
 123 #define LOONGARCH_CPUCFG2               0x2
 124 #define  CPUCFG2_FP                     BIT(0)
 125 #define  CPUCFG2_FPSP                   BIT(1)
 126 #define  CPUCFG2_FPDP                   BIT(2)
 127 #define  CPUCFG2_FPVERS                 GENMASK(5, 3)
 128 #define  CPUCFG2_LSX                    BIT(6)
 129 #define  CPUCFG2_LASX                   BIT(7)
 130 #define  CPUCFG2_COMPLEX                BIT(8)
 131 #define  CPUCFG2_CRYPTO                 BIT(9)
 132 #define  CPUCFG2_LVZP                   BIT(10)
 133 #define  CPUCFG2_LVZVER                 GENMASK(13, 11)
 134 #define  CPUCFG2_LLFTP                  BIT(14)
 135 #define  CPUCFG2_LLFTPREV               GENMASK(17, 15)
 136 #define  CPUCFG2_X86BT                  BIT(18)
 137 #define  CPUCFG2_ARMBT                  BIT(19)
 138 #define  CPUCFG2_MIPSBT                 BIT(20)
 139 #define  CPUCFG2_LSPW                   BIT(21)
 140 #define  CPUCFG2_LAM                    BIT(22)
 141
 142 #define LOONGARCH_CPUCFG3               0x3
 143 #define  CPUCFG3_CCDMA                  BIT(0)
 144 #define  CPUCFG3_SFB                    BIT(1)
 145 #define  CPUCFG3_UCACC                  BIT(2)
 146 #define  CPUCFG3_LLEXC                  BIT(3)
 147 #define  CPUCFG3_SCDLY                  BIT(4)
 148 #define  CPUCFG3_LLDBAR                 BIT(5)
 149 #define  CPUCFG3_ITLBT                  BIT(6)
 150 #define  CPUCFG3_ICACHET                BIT(7)
 151 #define  CPUCFG3_SPW_LVL                GENMASK(10, 8)
 152 #define  CPUCFG3_SPW_HG_HF              BIT(11)
 153 #define  CPUCFG3_RVA                    BIT(12)
 154 #define  CPUCFG3_RVAMAX                 GENMASK(16, 13)
 155
 156 #define LOONGARCH_CPUCFG4               0x4
 157 #define  CPUCFG4_CCFREQ                 GENMASK(31, 0)
 158
 159 #define LOONGARCH_CPUCFG5               0x5
 160 #define  CPUCFG5_CCMUL                  GENMASK(15, 0)
 161 #define  CPUCFG5_CCDIV                  GENMASK(31, 16)
 162
 163 #define LOONGARCH_CPUCFG6               0x6
 164 #define  CPUCFG6_PMP                    BIT(0)
 165 #define  CPUCFG6_PAMVER                 GENMASK(3, 1)
 166 #define  CPUCFG6_PMNUM                  GENMASK(7, 4)
 167 #define  CPUCFG6_PMBITS                 GENMASK(13, 8)
 168 #define  CPUCFG6_UPM                    BIT(14)
 169
 170 #define LOONGARCH_CPUCFG16              0x10
 171 #define  CPUCFG16_L1_IUPRE              BIT(0)
 172 #define  CPUCFG16_L1_IUUNIFY            BIT(1)
 173 #define  CPUCFG16_L1_DPRE               BIT(2)
 174 #define  CPUCFG16_L2_IUPRE              BIT(3)
 175 #define  CPUCFG16_L2_IUUNIFY            BIT(4)
 176 #define  CPUCFG16_L2_IUPRIV             BIT(5)
 177 #define  CPUCFG16_L2_IUINCL             BIT(6)
 178 #define  CPUCFG16_L2_DPRE               BIT(7)
 179 #define  CPUCFG16_L2_DPRIV              BIT(8)
 180 #define  CPUCFG16_L2_DINCL              BIT(9)
 181 #define  CPUCFG16_L3_IUPRE              BIT(10)
 182 #define  CPUCFG16_L3_IUUNIFY            BIT(11)
 183 #define  CPUCFG16_L3_IUPRIV             BIT(12)
 184 #define  CPUCFG16_L3_IUINCL             BIT(13)
 185 #define  CPUCFG16_L3_DPRE               BIT(14)
 186 #define  CPUCFG16_L3_DPRIV              BIT(15)
 187 #define  CPUCFG16_L3_DINCL              BIT(16)
 188
 189 #define LOONGARCH_CPUCFG17              0x11
 190 #define  CPUCFG17_L1I_WAYS_M            GENMASK(15, 0)
 191 #define  CPUCFG17_L1I_SETS_M            GENMASK(23, 16)
 192 #define  CPUCFG17_L1I_SIZE_M            GENMASK(30, 24)
 193 #define  CPUCFG17_L1I_WAYS              0
 194 #define  CPUCFG17_L1I_SETS              16
 195 #define  CPUCFG17_L1I_SIZE              24
 196
 197 #define LOONGARCH_CPUCFG18              0x12
 198 #define  CPUCFG18_L1D_WAYS_M            GENMASK(15, 0)
 199 #define  CPUCFG18_L1D_SETS_M            GENMASK(23, 16)
 200 #define  CPUCFG18_L1D_SIZE_M            GENMASK(30, 24)
 201 #define  CPUCFG18_L1D_WAYS              0
 202 #define  CPUCFG18_L1D_SETS              16
 203 #define  CPUCFG18_L1D_SIZE              24
 204
 205 #define LOONGARCH_CPUCFG19              0x13
 206 #define  CPUCFG19_L2_WAYS_M             GENMASK(15, 0)
 207 #define  CPUCFG19_L2_SETS_M             GENMASK(23, 16)
 208 #define  CPUCFG19_L2_SIZE_M             GENMASK(30, 24)
 209 #define  CPUCFG19_L2_WAYS               0
 210 #define  CPUCFG19_L2_SETS               16
 211 #define  CPUCFG19_L2_SIZE               24
 212
 213 #define LOONGARCH_CPUCFG20              0x14
 214 #define  CPUCFG20_L3_WAYS_M             GENMASK(15, 0)
 215 #define  CPUCFG20_L3_SETS_M             GENMASK(23, 16)
 216 #define  CPUCFG20_L3_SIZE_M             GENMASK(30, 24)
 217 #define  CPUCFG20_L3_WAYS               0
 218 #define  CPUCFG20_L3_SETS               16
 219 #define  CPUCFG20_L3_SIZE               24
 220
 221 #define LOONGARCH_CPUCFG48              0x30
 222 #define  CPUCFG48_MCSR_LCK              BIT(0)
 223 #define  CPUCFG48_NAP_EN                BIT(1)
 224 #define  CPUCFG48_VFPU_CG               BIT(2)
 225 #define  CPUCFG48_RAM_CG                BIT(3)
 226
 227 #ifndef __ASSEMBLY__
 228
 229 /* CSR */
 230 static __always_inline u32 csr_read32(u32 reg)
 231 {
 232         return __csrrd_w(reg);
 233 }
 234
 235 static __always_inline u64 csr_read64(u32 reg)
 236 {
 237         return __csrrd_d(reg);
 238 }
 239
 240 static __always_inline void csr_write32(u32 val, u32 reg)
 241 {
 242         __csrwr_w(val, reg);
 243 }
 244
 245 static __always_inline void csr_write64(u64 val, u32 reg)
 246 {
 247         __csrwr_d(val, reg);
 248 }
 249
 250 static __always_inline u32 csr_xchg32(u32 val, u32 mask, u32 reg)
 251 {
 252         return __csrxchg_w(val, mask, reg);
 253 }
 254
 255 static __always_inline u64 csr_xchg64(u64 val, u64 mask, u32 reg)
 256 {
 257         return __csrxchg_d(val, mask, reg);
 258 }
 259
 260 /* IOCSR */
 261 static __always_inline u32 iocsr_read32(u32 reg)
 262 {
 263         return __iocsrrd_w(reg);
 264 }
 265
 266 static __always_inline u64 iocsr_read64(u32 reg)
 267 {
 268         return __iocsrrd_d(reg);
 269 }
 270
 271 static __always_inline void iocsr_write32(u32 val, u32 reg)
 272 {
 273         __iocsrwr_w(val, reg);
 274 }
 275
 276 static __always_inline void iocsr_write64(u64 val, u32 reg)
 277 {
 278         __iocsrwr_d(val, reg);
 279 }
 280
 281 #endif /* !__ASSEMBLY__ */
 282
 283 /* CSR register number */
 284
 285 /* Basic CSR registers */
 286 #define LOONGARCH_CSR_CRMD              0x0     /* Current mode info */
 287 #define  CSR_CRMD_WE_SHIFT              9
 288 #define  CSR_CRMD_WE                    (_ULCAST_(0x1) << CSR_CRMD_WE_SHIFT)
 289 #define  CSR_CRMD_DACM_SHIFT            7
 290 #define  CSR_CRMD_DACM_WIDTH            2
 291 #define  CSR_CRMD_DACM                  (_ULCAST_(0x3) << CSR_CRMD_DACM_SHIFT)
 292 #define  CSR_CRMD_DACF_SHIFT            5
 293 #define  CSR_CRMD_DACF_WIDTH            2
 294 #define  CSR_CRMD_DACF                  (_ULCAST_(0x3) << CSR_CRMD_DACF_SHIFT)
 295 #define  CSR_CRMD_PG_SHIFT              4
 296 #define  CSR_CRMD_PG                    (_ULCAST_(0x1) << CSR_CRMD_PG_SHIFT)
 297 #define  CSR_CRMD_DA_SHIFT              3
 298 #define  CSR_CRMD_DA                    (_ULCAST_(0x1) << CSR_CRMD_DA_SHIFT)
 299 #define  CSR_CRMD_IE_SHIFT              2
 300 #define  CSR_CRMD_IE                    (_ULCAST_(0x1) << CSR_CRMD_IE_SHIFT)
 301 #define  CSR_CRMD_PLV_SHIFT             0
 302 #define  CSR_CRMD_PLV_WIDTH             2
 303 #define  CSR_CRMD_PLV                   (_ULCAST_(0x3) << CSR_CRMD_PLV_SHIFT)
 304
 305 #define PLV_KERN                        0
 306 #define PLV_USER                        3
 307 #define PLV_MASK                        0x3
 308
 309 #define LOONGARCH_CSR_PRMD              0x1     /* Prev-exception mode info */
 310 #define  CSR_PRMD_PWE_SHIFT             3
 311 #define  CSR_PRMD_PWE                   (_ULCAST_(0x1) << CSR_PRMD_PWE_SHIFT)
 312 #define  CSR_PRMD_PIE_SHIFT             2
 313 #define  CSR_PRMD_PIE                   (_ULCAST_(0x1) << CSR_PRMD_PIE_SHIFT)
 314 #define  CSR_PRMD_PPLV_SHIFT            0
 315 #define  CSR_PRMD_PPLV_WIDTH            2
 316 #define  CSR_PRMD_PPLV                  (_ULCAST_(0x3) << CSR_PRMD_PPLV_SHIFT)
 317
 318 #define LOONGARCH_CSR_EUEN              0x2     /* Extended unit enable */
 319 #define  CSR_EUEN_LBTEN_SHIFT           3
 320 #define  CSR_EUEN_LBTEN                 (_ULCAST_(0x1) << CSR_EUEN_LBTEN_SHIFT)
 321 #define  CSR_EUEN_LASXEN_SHIFT          2
 322 #define  CSR_EUEN_LASXEN                (_ULCAST_(0x1) << CSR_EUEN_LASXEN_SHIFT)
 323 #define  CSR_EUEN_LSXEN_SHIFT           1
 324 #define  CSR_EUEN_LSXEN                 (_ULCAST_(0x1) << CSR_EUEN_LSXEN_SHIFT)
 325 #define  CSR_EUEN_FPEN_SHIFT            0
 326 #define  CSR_EUEN_FPEN                  (_ULCAST_(0x1) << CSR_EUEN_FPEN_SHIFT)
 327
 328 #define LOONGARCH_CSR_MISC              0x3     /* Misc config */
 329
 330 #define LOONGARCH_CSR_ECFG              0x4     /* Exception config */
 331 #define  CSR_ECFG_VS_SHIFT              16
 332 #define  CSR_ECFG_VS_WIDTH              3
 333 #define  CSR_ECFG_VS                    (_ULCAST_(0x7) << CSR_ECFG_VS_SHIFT)
 334 #define  CSR_ECFG_IM_SHIFT              0
 335 #define  CSR_ECFG_IM_WIDTH              13
 336 #define  CSR_ECFG_IM                    (_ULCAST_(0x1fff) << CSR_ECFG_IM_SHIFT)
 337
 338 #define LOONGARCH_CSR_ESTAT             0x5     /* Exception status */
 339 #define  CSR_ESTAT_ESUBCODE_SHIFT       22
 340 #define  CSR_ESTAT_ESUBCODE_WIDTH       9
 341 #define  CSR_ESTAT_ESUBCODE             (_ULCAST_(0x1ff) << CSR_ESTAT_ESUBCODE_SHIFT)
 342 #define  CSR_ESTAT_EXC_SHIFT            16
 343 #define  CSR_ESTAT_EXC_WIDTH            6
 344 #define  CSR_ESTAT_EXC                  (_ULCAST_(0x3f) << CSR_ESTAT_EXC_SHIFT)
 345 #define  CSR_ESTAT_IS_SHIFT             0
 346 #define  CSR_ESTAT_IS_WIDTH             15
 347 #define  CSR_ESTAT_IS                   (_ULCAST_(0x7fff) << CSR_ESTAT_IS_SHIFT)
 348
 349 #define LOONGARCH_CSR_ERA               0x6     /* ERA */
 350
 351 #define LOONGARCH_CSR_BADV              0x7     /* Bad virtual address */
 352
 353 #define LOONGARCH_CSR_BADI              0x8     /* Bad instruction */
 354
 355 #define LOONGARCH_CSR_EENTRY            0xc     /* Exception entry */
 356
 357 /* TLB related CSR registers */
 358 #define LOONGARCH_CSR_TLBIDX            0x10    /* TLB Index, EHINV, PageSize, NP */
 359 #define  CSR_TLBIDX_EHINV_SHIFT         31
 360 #define  CSR_TLBIDX_EHINV               (_ULCAST_(1) << CSR_TLBIDX_EHINV_SHIFT)
 361 #define  CSR_TLBIDX_PS_SHIFT            24
 362 #define  CSR_TLBIDX_PS_WIDTH            6
 363 #define  CSR_TLBIDX_PS                  (_ULCAST_(0x3f) << CSR_TLBIDX_PS_SHIFT)
 364 #define  CSR_TLBIDX_IDX_SHIFT           0
 365 #define  CSR_TLBIDX_IDX_WIDTH           12
 366 #define  CSR_TLBIDX_IDX                 (_ULCAST_(0xfff) << CSR_TLBIDX_IDX_SHIFT)
 367 #define  CSR_TLBIDX_SIZEM               0x3f000000
 368 #define  CSR_TLBIDX_SIZE                CSR_TLBIDX_PS_SHIFT
 369 #define  CSR_TLBIDX_IDXM                0xfff
 370 #define  CSR_INVALID_ENTRY(e)           (CSR_TLBIDX_EHINV | e)
 371
 372 #define LOONGARCH_CSR_TLBEHI            0x11    /* TLB EntryHi */
 373
 374 #define LOONGARCH_CSR_TLBELO0           0x12    /* TLB EntryLo0 */
 375 #define  CSR_TLBLO0_RPLV_SHIFT          63
 376 #define  CSR_TLBLO0_RPLV                (_ULCAST_(0x1) << CSR_TLBLO0_RPLV_SHIFT)
 377 #define  CSR_TLBLO0_NX_SHIFT            62
 378 #define  CSR_TLBLO0_NX                  (_ULCAST_(0x1) << CSR_TLBLO0_NX_SHIFT)
 379 #define  CSR_TLBLO0_NR_SHIFT            61
 380 #define  CSR_TLBLO0_NR                  (_ULCAST_(0x1) << CSR_TLBLO0_NR_SHIFT)
 381 #define  CSR_TLBLO0_PFN_SHIFT           12
 382 #define  CSR_TLBLO0_PFN_WIDTH           36
 383 #define  CSR_TLBLO0_PFN                 (_ULCAST_(0xfffffffff) << CSR_TLBLO0_PFN_SHIFT)
 384 #define  CSR_TLBLO0_GLOBAL_SHIFT        6
 385 #define  CSR_TLBLO0_GLOBAL              (_ULCAST_(0x1) << CSR_TLBLO0_GLOBAL_SHIFT)
 386 #define  CSR_TLBLO0_CCA_SHIFT           4
 387 #define  CSR_TLBLO0_CCA_WIDTH           2
 388 #define  CSR_TLBLO0_CCA                 (_ULCAST_(0x3) << CSR_TLBLO0_CCA_SHIFT)
 389 #define  CSR_TLBLO0_PLV_SHIFT           2
 390 #define  CSR_TLBLO0_PLV_WIDTH           2
 391 #define  CSR_TLBLO0_PLV                 (_ULCAST_(0x3) << CSR_TLBLO0_PLV_SHIFT)
 392 #define  CSR_TLBLO0_WE_SHIFT            1
 393 #define  CSR_TLBLO0_WE                  (_ULCAST_(0x1) << CSR_TLBLO0_WE_SHIFT)
 394 #define  CSR_TLBLO0_V_SHIFT             0
 395 #define  CSR_TLBLO0_V                   (_ULCAST_(0x1) << CSR_TLBLO0_V_SHIFT)
 396
 397 #define LOONGARCH_CSR_TLBELO1           0x13    /* TLB EntryLo1 */
 398 #define  CSR_TLBLO1_RPLV_SHIFT          63
 399 #define  CSR_TLBLO1_RPLV                (_ULCAST_(0x1) << CSR_TLBLO1_RPLV_SHIFT)
 400 #define  CSR_TLBLO1_NX_SHIFT            62
 401 #define  CSR_TLBLO1_NX                  (_ULCAST_(0x1) << CSR_TLBLO1_NX_SHIFT)
 402 #define  CSR_TLBLO1_NR_SHIFT            61
 403 #define  CSR_TLBLO1_NR                  (_ULCAST_(0x1) << CSR_TLBLO1_NR_SHIFT)
 404 #define  CSR_TLBLO1_PFN_SHIFT           12
 405 #define  CSR_TLBLO1_PFN_WIDTH           36
 406 #define  CSR_TLBLO1_PFN                 (_ULCAST_(0xfffffffff) << CSR_TLBLO1_PFN_SHIFT)
 407 #define  CSR_TLBLO1_GLOBAL_SHIFT        6
 408 #define  CSR_TLBLO1_GLOBAL              (_ULCAST_(0x1) << CSR_TLBLO1_GLOBAL_SHIFT)
 409 #define  CSR_TLBLO1_CCA_SHIFT           4
 410 #define  CSR_TLBLO1_CCA_WIDTH           2
 411 #define  CSR_TLBLO1_CCA                 (_ULCAST_(0x3) << CSR_TLBLO1_CCA_SHIFT)
 412 #define  CSR_TLBLO1_PLV_SHIFT           2
 413 #define  CSR_TLBLO1_PLV_WIDTH           2
 414 #define  CSR_TLBLO1_PLV                 (_ULCAST_(0x3) << CSR_TLBLO1_PLV_SHIFT)
 415 #define  CSR_TLBLO1_WE_SHIFT            1
 416 #define  CSR_TLBLO1_WE                  (_ULCAST_(0x1) << CSR_TLBLO1_WE_SHIFT)
 417 #define  CSR_TLBLO1_V_SHIFT             0
 418 #define  CSR_TLBLO1_V                   (_ULCAST_(0x1) << CSR_TLBLO1_V_SHIFT)
 419
 420 #define LOONGARCH_CSR_GTLBC             0x15    /* Guest TLB control */
 421 #define  CSR_GTLBC_RID_SHIFT            16
 422 #define  CSR_GTLBC_RID_WIDTH            8
 423 #define  CSR_GTLBC_RID                  (_ULCAST_(0xff) << CSR_GTLBC_RID_SHIFT)
 424 #define  CSR_GTLBC_TOTI_SHIFT           13
 425 #define  CSR_GTLBC_TOTI                 (_ULCAST_(0x1) << CSR_GTLBC_TOTI_SHIFT)
 426 #define  CSR_GTLBC_USERID_SHIFT         12
 427 #define  CSR_GTLBC_USERID               (_ULCAST_(0x1) << CSR_GTLBC_USERID_SHIFT)
 428 #define  CSR_GTLBC_GMTLBSZ_SHIFT        0
 429 #define  CSR_GTLBC_GMTLBSZ_WIDTH        6
 430 #define  CSR_GTLBC_GMTLBSZ              (_ULCAST_(0x3f) << CSR_GTLBC_GMTLBSZ_SHIFT)
 431
 432 #define LOONGARCH_CSR_TRGP              0x16    /* TLBR read guest info */
 433 #define  CSR_TRGP_RID_SHIFT             16
 434 #define  CSR_TRGP_RID_WIDTH             8
 435 #define  CSR_TRGP_RID                   (_ULCAST_(0xff) << CSR_TRGP_RID_SHIFT)
 436 #define  CSR_TRGP_GTLB_SHIFT            0
 437 #define  CSR_TRGP_GTLB                  (1 << CSR_TRGP_GTLB_SHIFT)
 438
 439 #define LOONGARCH_CSR_ASID              0x18    /* ASID */
 440 #define  CSR_ASID_BIT_SHIFT             16      /* ASIDBits */
 441 #define  CSR_ASID_BIT_WIDTH             8
 442 #define  CSR_ASID_BIT                   (_ULCAST_(0xff) << CSR_ASID_BIT_SHIFT)
 443 #define  CSR_ASID_ASID_SHIFT            0
 444 #define  CSR_ASID_ASID_WIDTH            10
 445 #define  CSR_ASID_ASID                  (_ULCAST_(0x3ff) << CSR_ASID_ASID_SHIFT)
 446
 447 #define LOONGARCH_CSR_PGDL              0x19    /* Page table base address when VA[47] = 0 */
 448
 449 #define LOONGARCH_CSR_PGDH              0x1a    /* Page table base address when VA[47] = 1 */
 450
 451 #define LOONGARCH_CSR_PGD               0x1b    /* Page table base */
 452
 453 #define LOONGARCH_CSR_PWCTL0            0x1c    /* PWCtl0 */
 454 #define  CSR_PWCTL0_PTEW_SHIFT          30
 455 #define  CSR_PWCTL0_PTEW_WIDTH          2
 456 #define  CSR_PWCTL0_PTEW                (_ULCAST_(0x3) << CSR_PWCTL0_PTEW_SHIFT)
 457 #define  CSR_PWCTL0_DIR1WIDTH_SHIFT     25
 458 #define  CSR_PWCTL0_DIR1WIDTH_WIDTH     5
 459 #define  CSR_PWCTL0_DIR1WIDTH           (_ULCAST_(0x1f) << CSR_PWCTL0_DIR1WIDTH_SHIFT)
 460 #define  CSR_PWCTL0_DIR1BASE_SHIFT      20
 461 #define  CSR_PWCTL0_DIR1BASE_WIDTH      5
 462 #define  CSR_PWCTL0_DIR1BASE            (_ULCAST_(0x1f) << CSR_PWCTL0_DIR1BASE_SHIFT)
 463 #define  CSR_PWCTL0_DIR0WIDTH_SHIFT     15
 464 #define  CSR_PWCTL0_DIR0WIDTH_WIDTH     5
 465 #define  CSR_PWCTL0_DIR0WIDTH           (_ULCAST_(0x1f) << CSR_PWCTL0_DIR0WIDTH_SHIFT)
 466 #define  CSR_PWCTL0_DIR0BASE_SHIFT      10
 467 #define  CSR_PWCTL0_DIR0BASE_WIDTH      5
 468 #define  CSR_PWCTL0_DIR0BASE            (_ULCAST_(0x1f) << CSR_PWCTL0_DIR0BASE_SHIFT)
 469 #define  CSR_PWCTL0_PTWIDTH_SHIFT       5
 470 #define  CSR_PWCTL0_PTWIDTH_WIDTH       5
 471 #define  CSR_PWCTL0_PTWIDTH             (_ULCAST_(0x1f) << CSR_PWCTL0_PTWIDTH_SHIFT)
 472 #define  CSR_PWCTL0_PTBASE_SHIFT        0
 473 #define  CSR_PWCTL0_PTBASE_WIDTH        5
 474 #define  CSR_PWCTL0_PTBASE              (_ULCAST_(0x1f) << CSR_PWCTL0_PTBASE_SHIFT)
 475
 476 #define LOONGARCH_CSR_PWCTL1            0x1d    /* PWCtl1 */
 477 #define  CSR_PWCTL1_DIR3WIDTH_SHIFT     18
 478 #define  CSR_PWCTL1_DIR3WIDTH_WIDTH     5
 479 #define  CSR_PWCTL1_DIR3WIDTH           (_ULCAST_(0x1f) << CSR_PWCTL1_DIR3WIDTH_SHIFT)
 480 #define  CSR_PWCTL1_DIR3BASE_SHIFT      12
 481 #define  CSR_PWCTL1_DIR3BASE_WIDTH      5
 482 #define  CSR_PWCTL1_DIR3BASE            (_ULCAST_(0x1f) << CSR_PWCTL0_DIR3BASE_SHIFT)
 483 #define  CSR_PWCTL1_DIR2WIDTH_SHIFT     6
 484 #define  CSR_PWCTL1_DIR2WIDTH_WIDTH     5
 485 #define  CSR_PWCTL1_DIR2WIDTH           (_ULCAST_(0x1f) << CSR_PWCTL1_DIR2WIDTH_SHIFT)
 486 #define  CSR_PWCTL1_DIR2BASE_SHIFT      0
 487 #define  CSR_PWCTL1_DIR2BASE_WIDTH      5
 488 #define  CSR_PWCTL1_DIR2BASE            (_ULCAST_(0x1f) << CSR_PWCTL0_DIR2BASE_SHIFT)
 489
 490 #define LOONGARCH_CSR_STLBPGSIZE        0x1e
 491 #define  CSR_STLBPGSIZE_PS_WIDTH        6
 492 #define  CSR_STLBPGSIZE_PS              (_ULCAST_(0x3f))
 493
 494 #define LOONGARCH_CSR_RVACFG            0x1f
 495 #define  CSR_RVACFG_RDVA_WIDTH          4
 496 #define  CSR_RVACFG_RDVA                (_ULCAST_(0xf))
 497
 498 /* Config CSR registers */
 499 #define LOONGARCH_CSR_CPUID             0x20    /* CPU core id */
 500 #define  CSR_CPUID_COREID_WIDTH         9
 501 #define  CSR_CPUID_COREID               _ULCAST_(0x1ff)
 502
 503 #define LOONGARCH_CSR_PRCFG1            0x21    /* Config1 */
 504 #define  CSR_CONF1_VSMAX_SHIFT          12
 505 #define  CSR_CONF1_VSMAX_WIDTH          3
 506 #define  CSR_CONF1_VSMAX                (_ULCAST_(7) << CSR_CONF1_VSMAX_SHIFT)
 507 #define  CSR_CONF1_TMRBITS_SHIFT        4
 508 #define  CSR_CONF1_TMRBITS_WIDTH        8
 509 #define  CSR_CONF1_TMRBITS              (_ULCAST_(0xff) << CSR_CONF1_TMRBITS_SHIFT)
 510 #define  CSR_CONF1_KSNUM_WIDTH          4
 511 #define  CSR_CONF1_KSNUM                _ULCAST_(0xf)
 512
 513 #define LOONGARCH_CSR_PRCFG2            0x22    /* Config2 */
 514 #define  CSR_CONF2_PGMASK_SUPP          0x3ffff000
 515
 516 #define LOONGARCH_CSR_PRCFG3            0x23    /* Config3 */
 517 #define  CSR_CONF3_STLBIDX_SHIFT        20
 518 #define  CSR_CONF3_STLBIDX_WIDTH        6
 519 #define  CSR_CONF3_STLBIDX              (_ULCAST_(0x3f) << CSR_CONF3_STLBIDX_SHIFT)
 520 #define  CSR_CONF3_STLBWAYS_SHIFT       12
 521 #define  CSR_CONF3_STLBWAYS_WIDTH       8
 522 #define  CSR_CONF3_STLBWAYS             (_ULCAST_(0xff) << CSR_CONF3_STLBWAYS_SHIFT)
 523 #define  CSR_CONF3_MTLBSIZE_SHIFT       4
 524 #define  CSR_CONF3_MTLBSIZE_WIDTH       8
 525 #define  CSR_CONF3_MTLBSIZE             (_ULCAST_(0xff) << CSR_CONF3_MTLBSIZE_SHIFT)
 526 #define  CSR_CONF3_TLBTYPE_SHIFT        0
 527 #define  CSR_CONF3_TLBTYPE_WIDTH        4
 528 #define  CSR_CONF3_TLBTYPE              (_ULCAST_(0xf) << CSR_CONF3_TLBTYPE_SHIFT)
 529
 530 /* KSave registers */
 531 #define LOONGARCH_CSR_KS0               0x30
 532 #define LOONGARCH_CSR_KS1               0x31
 533 #define LOONGARCH_CSR_KS2               0x32
 534 #define LOONGARCH_CSR_KS3               0x33
 535 #define LOONGARCH_CSR_KS4               0x34
 536 #define LOONGARCH_CSR_KS5               0x35
 537 #define LOONGARCH_CSR_KS6               0x36
 538 #define LOONGARCH_CSR_KS7               0x37
 539 #define LOONGARCH_CSR_KS8               0x38
 540
 541 /* Exception allocated KS0, KS1 and KS2 statically */
 542 #define EXCEPTION_KS0                   LOONGARCH_CSR_KS0
 543 #define EXCEPTION_KS1                   LOONGARCH_CSR_KS1
 544 #define EXCEPTION_KS2                   LOONGARCH_CSR_KS2
 545 #define EXC_KSAVE_MASK                  (1 << 0 | 1 << 1 | 1 << 2)
 546
 547 /* Percpu-data base allocated KS3 statically */
 548 #define PERCPU_BASE_KS                  LOONGARCH_CSR_KS3
 549 #define PERCPU_KSAVE_MASK               (1 << 3)
 550
 551 /* KVM allocated KS4 and KS5 statically */
 552 #define KVM_VCPU_KS                     LOONGARCH_CSR_KS4
 553 #define KVM_TEMP_KS                     LOONGARCH_CSR_KS5
 554 #define KVM_KSAVE_MASK                  (1 << 4 | 1 << 5)
 555
 556 /* Timer registers */
 557 #define LOONGARCH_CSR_TMID              0x40    /* Timer ID */
 558
 559 #define LOONGARCH_CSR_TCFG              0x41    /* Timer config */
 560 #define  CSR_TCFG_VAL_SHIFT             2
 561 #define  CSR_TCFG_VAL_WIDTH             48
 562 #define  CSR_TCFG_VAL                   (_ULCAST_(0x3fffffffffff) << CSR_TCFG_VAL_SHIFT)
 563 #define  CSR_TCFG_PERIOD_SHIFT          1
 564 #define  CSR_TCFG_PERIOD                (_ULCAST_(0x1) << CSR_TCFG_PERIOD_SHIFT)
 565 #define  CSR_TCFG_EN                    (_ULCAST_(0x1))
 566
 567 #define LOONGARCH_CSR_TVAL              0x42    /* Timer value */
 568
 569 #define LOONGARCH_CSR_CNTC              0x43    /* Timer offset */
 570
 571 #define LOONGARCH_CSR_TINTCLR           0x44    /* Timer interrupt clear */
 572 #define  CSR_TINTCLR_TI_SHIFT           0
 573 #define  CSR_TINTCLR_TI                 (1 << CSR_TINTCLR_TI_SHIFT)
 574
 575 /* Guest registers */
 576 #define LOONGARCH_CSR_GSTAT             0x50    /* Guest status */
 577 #define  CSR_GSTAT_GID_SHIFT            16
 578 #define  CSR_GSTAT_GID_WIDTH            8
 579 #define  CSR_GSTAT_GID                  (_ULCAST_(0xff) << CSR_GSTAT_GID_SHIFT)
 580 #define  CSR_GSTAT_GIDBIT_SHIFT         4
 581 #define  CSR_GSTAT_GIDBIT_WIDTH         6
 582 #define  CSR_GSTAT_GIDBIT               (_ULCAST_(0x3f) << CSR_GSTAT_GIDBIT_SHIFT)
 583 #define  CSR_GSTAT_PVM_SHIFT            1
 584 #define  CSR_GSTAT_PVM                  (_ULCAST_(0x1) << CSR_GSTAT_PVM_SHIFT)
 585 #define  CSR_GSTAT_VM_SHIFT             0
 586 #define  CSR_GSTAT_VM                   (_ULCAST_(0x1) << CSR_GSTAT_VM_SHIFT)
 587
 588 #define LOONGARCH_CSR_GCFG              0x51    /* Guest config */
 589 #define  CSR_GCFG_GPERF_SHIFT           24
 590 #define  CSR_GCFG_GPERF_WIDTH           3
 591 #define  CSR_GCFG_GPERF                 (_ULCAST_(0x7) << CSR_GCFG_GPERF_SHIFT)
 592 #define  CSR_GCFG_GCI_SHIFT             20
 593 #define  CSR_GCFG_GCI_WIDTH             2
 594 #define  CSR_GCFG_GCI                   (_ULCAST_(0x3) << CSR_GCFG_GCI_SHIFT)
 595 #define  CSR_GCFG_GCI_ALL               (_ULCAST_(0x0) << CSR_GCFG_GCI_SHIFT)
 596 #define  CSR_GCFG_GCI_HIT               (_ULCAST_(0x1) << CSR_GCFG_GCI_SHIFT)
 597 #define  CSR_GCFG_GCI_SECURE            (_ULCAST_(0x2) << CSR_GCFG_GCI_SHIFT)
 598 #define  CSR_GCFG_GCIP_SHIFT            16
 599 #define  CSR_GCFG_GCIP                  (_ULCAST_(0xf) << CSR_GCFG_GCIP_SHIFT)
 600 #define  CSR_GCFG_GCIP_ALL              (_ULCAST_(0x1) << CSR_GCFG_GCIP_SHIFT)
 601 #define  CSR_GCFG_GCIP_HIT              (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 1))
 602 #define  CSR_GCFG_GCIP_SECURE           (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 2))
 603 #define  CSR_GCFG_TORU_SHIFT            15
 604 #define  CSR_GCFG_TORU                  (_ULCAST_(0x1) << CSR_GCFG_TORU_SHIFT)
 605 #define  CSR_GCFG_TORUP_SHIFT           14
 606 #define  CSR_GCFG_TORUP                 (_ULCAST_(0x1) << CSR_GCFG_TORUP_SHIFT)
 607 #define  CSR_GCFG_TOP_SHIFT             13
 608 #define  CSR_GCFG_TOP                   (_ULCAST_(0x1) << CSR_GCFG_TOP_SHIFT)
 609 #define  CSR_GCFG_TOPP_SHIFT            12
 610 #define  CSR_GCFG_TOPP                  (_ULCAST_(0x1) << CSR_GCFG_TOPP_SHIFT)
 611 #define  CSR_GCFG_TOE_SHIFT             11
 612 #define  CSR_GCFG_TOE                   (_ULCAST_(0x1) << CSR_GCFG_TOE_SHIFT)
 613 #define  CSR_GCFG_TOEP_SHIFT            10
 614 #define  CSR_GCFG_TOEP                  (_ULCAST_(0x1) << CSR_GCFG_TOEP_SHIFT)
 615 #define  CSR_GCFG_TIT_SHIFT             9
 616 #define  CSR_GCFG_TIT                   (_ULCAST_(0x1) << CSR_GCFG_TIT_SHIFT)
 617 #define  CSR_GCFG_TITP_SHIFT            8
 618 #define  CSR_GCFG_TITP                  (_ULCAST_(0x1) << CSR_GCFG_TITP_SHIFT)
 619 #define  CSR_GCFG_SIT_SHIFT             7
 620 #define  CSR_GCFG_SIT                   (_ULCAST_(0x1) << CSR_GCFG_SIT_SHIFT)
 621 #define  CSR_GCFG_SITP_SHIFT            6
 622 #define  CSR_GCFG_SITP                  (_ULCAST_(0x1) << CSR_GCFG_SITP_SHIFT)
 623 #define  CSR_GCFG_MATC_SHITF            4
 624 #define  CSR_GCFG_MATC_WIDTH            2
 625 #define  CSR_GCFG_MATC_MASK             (_ULCAST_(0x3) << CSR_GCFG_MATC_SHITF)
 626 #define  CSR_GCFG_MATC_GUEST            (_ULCAST_(0x0) << CSR_GCFG_MATC_SHITF)
 627 #define  CSR_GCFG_MATC_ROOT             (_ULCAST_(0x1) << CSR_GCFG_MATC_SHITF)
 628 #define  CSR_GCFG_MATC_NEST             (_ULCAST_(0x2) << CSR_GCFG_MATC_SHITF)
 629
 630 #define LOONGARCH_CSR_GINTC             0x52    /* Guest interrupt control */
 631 #define  CSR_GINTC_HC_SHIFT             16
 632 #define  CSR_GINTC_HC_WIDTH             8
 633 #define  CSR_GINTC_HC                   (_ULCAST_(0xff) << CSR_GINTC_HC_SHIFT)
 634 #define  CSR_GINTC_PIP_SHIFT            8
 635 #define  CSR_GINTC_PIP_WIDTH            8
 636 #define  CSR_GINTC_PIP                  (_ULCAST_(0xff) << CSR_GINTC_PIP_SHIFT)
 637 #define  CSR_GINTC_VIP_SHIFT            0
 638 #define  CSR_GINTC_VIP_WIDTH            8
 639 #define  CSR_GINTC_VIP                  (_ULCAST_(0xff))
 640
 641 #define LOONGARCH_CSR_GCNTC             0x53    /* Guest timer offset */
 642
 643 /* LLBCTL register */
 644 #define LOONGARCH_CSR_LLBCTL            0x60    /* LLBit control */
 645 #define  CSR_LLBCTL_ROLLB_SHIFT         0
 646 #define  CSR_LLBCTL_ROLLB               (_ULCAST_(1) << CSR_LLBCTL_ROLLB_SHIFT)
 647 #define  CSR_LLBCTL_WCLLB_SHIFT         1
 648 #define  CSR_LLBCTL_WCLLB               (_ULCAST_(1) << CSR_LLBCTL_WCLLB_SHIFT)
 649 #define  CSR_LLBCTL_KLO_SHIFT           2
 650 #define  CSR_LLBCTL_KLO                 (_ULCAST_(1) << CSR_LLBCTL_KLO_SHIFT)
 651
 652 /* Implement dependent */
 653 #define LOONGARCH_CSR_IMPCTL1           0x80    /* Loongson config1 */
 654 #define  CSR_MISPEC_SHIFT               20
 655 #define  CSR_MISPEC_WIDTH               8
 656 #define  CSR_MISPEC                     (_ULCAST_(0xff) << CSR_MISPEC_SHIFT)
 657 #define  CSR_SSEN_SHIFT                 18
 658 #define  CSR_SSEN                       (_ULCAST_(1) << CSR_SSEN_SHIFT)
 659 #define  CSR_SCRAND_SHIFT               17
 660 #define  CSR_SCRAND                     (_ULCAST_(1) << CSR_SCRAND_SHIFT)
 661 #define  CSR_LLEXCL_SHIFT               16
 662 #define  CSR_LLEXCL                     (_ULCAST_(1) << CSR_LLEXCL_SHIFT)
 663 #define  CSR_DISVC_SHIFT                15
 664 #define  CSR_DISVC                      (_ULCAST_(1) << CSR_DISVC_SHIFT)
 665 #define  CSR_VCLRU_SHIFT                14
 666 #define  CSR_VCLRU                      (_ULCAST_(1) << CSR_VCLRU_SHIFT)
 667 #define  CSR_DCLRU_SHIFT                13
 668 #define  CSR_DCLRU                      (_ULCAST_(1) << CSR_DCLRU_SHIFT)
 669 #define  CSR_FASTLDQ_SHIFT              12
 670 #define  CSR_FASTLDQ                    (_ULCAST_(1) << CSR_FASTLDQ_SHIFT)
 671 #define  CSR_USERCAC_SHIFT              11
 672 #define  CSR_USERCAC                    (_ULCAST_(1) << CSR_USERCAC_SHIFT)
 673 #define  CSR_ANTI_MISPEC_SHIFT          10
 674 #define  CSR_ANTI_MISPEC                (_ULCAST_(1) << CSR_ANTI_MISPEC_SHIFT)
 675 #define  CSR_AUTO_FLUSHSFB_SHIFT        9
 676 #define  CSR_AUTO_FLUSHSFB              (_ULCAST_(1) << CSR_AUTO_FLUSHSFB_SHIFT)
 677 #define  CSR_STFILL_SHIFT               8
 678 #define  CSR_STFILL                     (_ULCAST_(1) << CSR_STFILL_SHIFT)
 679 #define  CSR_LIFEP_SHIFT                7
 680 #define  CSR_LIFEP                      (_ULCAST_(1) << CSR_LIFEP_SHIFT)
 681 #define  CSR_LLSYNC_SHIFT               6
 682 #define  CSR_LLSYNC                     (_ULCAST_(1) << CSR_LLSYNC_SHIFT)
 683 #define  CSR_BRBTDIS_SHIFT              5
 684 #define  CSR_BRBTDIS                    (_ULCAST_(1) << CSR_BRBTDIS_SHIFT)
 685 #define  CSR_RASDIS_SHIFT               4
 686 #define  CSR_RASDIS                     (_ULCAST_(1) << CSR_RASDIS_SHIFT)
 687 #define  CSR_STPRE_SHIFT                2
 688 #define  CSR_STPRE_WIDTH                2
 689 #define  CSR_STPRE                      (_ULCAST_(3) << CSR_STPRE_SHIFT)
 690 #define  CSR_INSTPRE_SHIFT              1
 691 #define  CSR_INSTPRE                    (_ULCAST_(1) << CSR_INSTPRE_SHIFT)
 692 #define  CSR_DATAPRE_SHIFT              0
 693 #define  CSR_DATAPRE                    (_ULCAST_(1) << CSR_DATAPRE_SHIFT)
 694
 695 #define LOONGARCH_CSR_IMPCTL2           0x81    /* Loongson config2 */
 696 #define  CSR_FLUSH_MTLB_SHIFT           0
 697 #define  CSR_FLUSH_MTLB                 (_ULCAST_(1) << CSR_FLUSH_MTLB_SHIFT)
 698 #define  CSR_FLUSH_STLB_SHIFT           1
 699 #define  CSR_FLUSH_STLB                 (_ULCAST_(1) << CSR_FLUSH_STLB_SHIFT)
 700 #define  CSR_FLUSH_DTLB_SHIFT           2
 701 #define  CSR_FLUSH_DTLB                 (_ULCAST_(1) << CSR_FLUSH_DTLB_SHIFT)
 702 #define  CSR_FLUSH_ITLB_SHIFT           3
 703 #define  CSR_FLUSH_ITLB                 (_ULCAST_(1) << CSR_FLUSH_ITLB_SHIFT)
 704 #define  CSR_FLUSH_BTAC_SHIFT           4
 705 #define  CSR_FLUSH_BTAC                 (_ULCAST_(1) << CSR_FLUSH_BTAC_SHIFT)
 706
 707 #define LOONGARCH_CSR_GNMI              0x82
 708
 709 /* TLB Refill registers */
 710 #define LOONGARCH_CSR_TLBRENTRY         0x88    /* TLB refill exception entry */
 711 #define LOONGARCH_CSR_TLBRBADV          0x89    /* TLB refill badvaddr */
 712 #define LOONGARCH_CSR_TLBRERA           0x8a    /* TLB refill ERA */
 713 #define LOONGARCH_CSR_TLBRSAVE          0x8b    /* KSave for TLB refill exception */
 714 #define LOONGARCH_CSR_TLBRELO0          0x8c    /* TLB refill entrylo0 */
 715 #define LOONGARCH_CSR_TLBRELO1          0x8d    /* TLB refill entrylo1 */
 716 #define LOONGARCH_CSR_TLBREHI           0x8e    /* TLB refill entryhi */
 717 #define  CSR_TLBREHI_PS_SHIFT           0
 718 #define  CSR_TLBREHI_PS                 (_ULCAST_(0x3f) << CSR_TLBREHI_PS_SHIFT)
 719 #define LOONGARCH_CSR_TLBRPRMD          0x8f    /* TLB refill mode info */
 720
 721 /* Machine Error registers */
 722 #define LOONGARCH_CSR_MERRCTL           0x90    /* MERRCTL */
 723 #define LOONGARCH_CSR_MERRINFO1         0x91    /* MError info1 */
 724 #define LOONGARCH_CSR_MERRINFO2         0x92    /* MError info2 */
 725 #define LOONGARCH_CSR_MERRENTRY         0x93    /* MError exception entry */
 726 #define LOONGARCH_CSR_MERRERA           0x94    /* MError exception ERA */
 727 #define LOONGARCH_CSR_MERRSAVE          0x95    /* KSave for machine error exception */
 728
 729 #define LOONGARCH_CSR_CTAG              0x98    /* TagLo + TagHi */
 730
 731 #define LOONGARCH_CSR_PRID              0xc0
 732
 733 /* Shadow MCSR : 0xc0 ~ 0xff */
 734 #define LOONGARCH_CSR_MCSR0             0xc0    /* CPUCFG0 and CPUCFG1 */
 735 #define  MCSR0_INT_IMPL_SHIFT           58
 736 #define  MCSR0_INT_IMPL                 0
 737 #define  MCSR0_IOCSR_BRD_SHIFT          57
 738 #define  MCSR0_IOCSR_BRD                (_ULCAST_(1) << MCSR0_IOCSR_BRD_SHIFT)
 739 #define  MCSR0_HUGEPG_SHIFT             56
 740 #define  MCSR0_HUGEPG                   (_ULCAST_(1) << MCSR0_HUGEPG_SHIFT)
 741 #define  MCSR0_RPLMTLB_SHIFT            55
 742 #define  MCSR0_RPLMTLB                  (_ULCAST_(1) << MCSR0_RPLMTLB_SHIFT)
 743 #define  MCSR0_EP_SHIFT                 54
 744 #define  MCSR0_EP                       (_ULCAST_(1) << MCSR0_EP_SHIFT)
 745 #define  MCSR0_RI_SHIFT                 53
 746 #define  MCSR0_RI                       (_ULCAST_(1) << MCSR0_RI_SHIFT)
 747 #define  MCSR0_UAL_SHIFT                52
 748 #define  MCSR0_UAL                      (_ULCAST_(1) << MCSR0_UAL_SHIFT)
 749 #define  MCSR0_VABIT_SHIFT              44
 750 #define  MCSR0_VABIT_WIDTH              8
 751 #define  MCSR0_VABIT                    (_ULCAST_(0xff) << MCSR0_VABIT_SHIFT)
 752 #define  VABIT_DEFAULT                  0x2f
 753 #define  MCSR0_PABIT_SHIFT              36
 754 #define  MCSR0_PABIT_WIDTH              8
 755 #define  MCSR0_PABIT                    (_ULCAST_(0xff) << MCSR0_PABIT_SHIFT)
 756 #define  PABIT_DEFAULT                  0x2f
 757 #define  MCSR0_IOCSR_SHIFT              35
 758 #define  MCSR0_IOCSR                    (_ULCAST_(1) << MCSR0_IOCSR_SHIFT)
 759 #define  MCSR0_PAGING_SHIFT             34
 760 #define  MCSR0_PAGING                   (_ULCAST_(1) << MCSR0_PAGING_SHIFT)
 761 #define  MCSR0_GR64_SHIFT               33
 762 #define  MCSR0_GR64                     (_ULCAST_(1) << MCSR0_GR64_SHIFT)
 763 #define  GR64_DEFAULT                   1
 764 #define  MCSR0_GR32_SHIFT               32
 765 #define  MCSR0_GR32                     (_ULCAST_(1) << MCSR0_GR32_SHIFT)
 766 #define  GR32_DEFAULT                   0
 767 #define  MCSR0_PRID_WIDTH               32
 768 #define  MCSR0_PRID                     0x14C010
 769
 770 #define LOONGARCH_CSR_MCSR1             0xc1    /* CPUCFG2 and CPUCFG3 */
 771 #define  MCSR1_HPFOLD_SHIFT             43
 772 #define  MCSR1_HPFOLD                   (_ULCAST_(1) << MCSR1_HPFOLD_SHIFT)
 773 #define  MCSR1_SPW_LVL_SHIFT            40
 774 #define  MCSR1_SPW_LVL_WIDTH            3
 775 #define  MCSR1_SPW_LVL                  (_ULCAST_(7) << MCSR1_SPW_LVL_SHIFT)
 776 #define  MCSR1_ICACHET_SHIFT            39
 777 #define  MCSR1_ICACHET                  (_ULCAST_(1) << MCSR1_ICACHET_SHIFT)
 778 #define  MCSR1_ITLBT_SHIFT              38
 779 #define  MCSR1_ITLBT                    (_ULCAST_(1) << MCSR1_ITLBT_SHIFT)
 780 #define  MCSR1_LLDBAR_SHIFT             37
 781 #define  MCSR1_LLDBAR                   (_ULCAST_(1) << MCSR1_LLDBAR_SHIFT)
 782 #define  MCSR1_SCDLY_SHIFT              36
 783 #define  MCSR1_SCDLY                    (_ULCAST_(1) << MCSR1_SCDLY_SHIFT)
 784 #define  MCSR1_LLEXC_SHIFT              35
 785 #define  MCSR1_LLEXC                    (_ULCAST_(1) << MCSR1_LLEXC_SHIFT)
 786 #define  MCSR1_UCACC_SHIFT              34
 787 #define  MCSR1_UCACC                    (_ULCAST_(1) << MCSR1_UCACC_SHIFT)
 788 #define  MCSR1_SFB_SHIFT                33
 789 #define  MCSR1_SFB                      (_ULCAST_(1) << MCSR1_SFB_SHIFT)
 790 #define  MCSR1_CCDMA_SHIFT              32
 791 #define  MCSR1_CCDMA                    (_ULCAST_(1) << MCSR1_CCDMA_SHIFT)
 792 #define  MCSR1_LAMO_SHIFT               22
 793 #define  MCSR1_LAMO                     (_ULCAST_(1) << MCSR1_LAMO_SHIFT)
 794 #define  MCSR1_LSPW_SHIFT               21
 795 #define  MCSR1_LSPW                     (_ULCAST_(1) << MCSR1_LSPW_SHIFT)
 796 #define  MCSR1_MIPSBT_SHIFT             20
 797 #define  MCSR1_MIPSBT                   (_ULCAST_(1) << MCSR1_MIPSBT_SHIFT)
 798 #define  MCSR1_ARMBT_SHIFT              19
 799 #define  MCSR1_ARMBT                    (_ULCAST_(1) << MCSR1_ARMBT_SHIFT)
 800 #define  MCSR1_X86BT_SHIFT              18
 801 #define  MCSR1_X86BT                    (_ULCAST_(1) << MCSR1_X86BT_SHIFT)
 802 #define  MCSR1_LLFTPVERS_SHIFT          15
 803 #define  MCSR1_LLFTPVERS_WIDTH          3
 804 #define  MCSR1_LLFTPVERS                (_ULCAST_(7) << MCSR1_LLFTPVERS_SHIFT)
 805 #define  MCSR1_LLFTP_SHIFT              14
 806 #define  MCSR1_LLFTP                    (_ULCAST_(1) << MCSR1_LLFTP_SHIFT)
 807 #define  MCSR1_VZVERS_SHIFT             11
 808 #define  MCSR1_VZVERS_WIDTH             3
 809 #define  MCSR1_VZVERS                   (_ULCAST_(7) << MCSR1_VZVERS_SHIFT)
 810 #define  MCSR1_VZ_SHIFT                 10
 811 #define  MCSR1_VZ                       (_ULCAST_(1) << MCSR1_VZ_SHIFT)
 812 #define  MCSR1_CRYPTO_SHIFT             9
 813 #define  MCSR1_CRYPTO                   (_ULCAST_(1) << MCSR1_CRYPTO_SHIFT)
 814 #define  MCSR1_COMPLEX_SHIFT            8
 815 #define  MCSR1_COMPLEX                  (_ULCAST_(1) << MCSR1_COMPLEX_SHIFT)
 816 #define  MCSR1_LASX_SHIFT               7
 817 #define  MCSR1_LASX                     (_ULCAST_(1) << MCSR1_LASX_SHIFT)
 818 #define  MCSR1_LSX_SHIFT                6
 819 #define  MCSR1_LSX                      (_ULCAST_(1) << MCSR1_LSX_SHIFT)
 820 #define  MCSR1_FPVERS_SHIFT             3
 821 #define  MCSR1_FPVERS_WIDTH             3
 822 #define  MCSR1_FPVERS                   (_ULCAST_(7) << MCSR1_FPVERS_SHIFT)
 823 #define  MCSR1_FPDP_SHIFT               2
 824 #define  MCSR1_FPDP                     (_ULCAST_(1) << MCSR1_FPDP_SHIFT)
 825 #define  MCSR1_FPSP_SHIFT               1
 826 #define  MCSR1_FPSP                     (_ULCAST_(1) << MCSR1_FPSP_SHIFT)
 827 #define  MCSR1_FP_SHIFT                 0
 828 #define  MCSR1_FP                       (_ULCAST_(1) << MCSR1_FP_SHIFT)
 829
 830 #define LOONGARCH_CSR_MCSR2             0xc2    /* CPUCFG4 and CPUCFG5 */
 831 #define  MCSR2_CCDIV_SHIFT              48
 832 #define  MCSR2_CCDIV_WIDTH              16
 833 #define  MCSR2_CCDIV                    (_ULCAST_(0xffff) << MCSR2_CCDIV_SHIFT)
 834 #define  MCSR2_CCMUL_SHIFT              32
 835 #define  MCSR2_CCMUL_WIDTH              16
 836 #define  MCSR2_CCMUL                    (_ULCAST_(0xffff) << MCSR2_CCMUL_SHIFT)
 837 #define  MCSR2_CCFREQ_WIDTH             32
 838 #define  MCSR2_CCFREQ                   (_ULCAST_(0xffffffff))
 839 #define  CCFREQ_DEFAULT                 0x5f5e100       /* 100MHz */
 840
 841 #define LOONGARCH_CSR_MCSR3             0xc3    /* CPUCFG6 */
 842 #define  MCSR3_UPM_SHIFT                14
 843 #define  MCSR3_UPM                      (_ULCAST_(1) << MCSR3_UPM_SHIFT)
 844 #define  MCSR3_PMBITS_SHIFT             8
 845 #define  MCSR3_PMBITS_WIDTH             6
 846 #define  MCSR3_PMBITS                   (_ULCAST_(0x3f) << MCSR3_PMBITS_SHIFT)
 847 #define  PMBITS_DEFAULT                 0x40
 848 #define  MCSR3_PMNUM_SHIFT              4
 849 #define  MCSR3_PMNUM_WIDTH              4
 850 #define  MCSR3_PMNUM                    (_ULCAST_(0xf) << MCSR3_PMNUM_SHIFT)
 851 #define  MCSR3_PAMVER_SHIFT             1
 852 #define  MCSR3_PAMVER_WIDTH             3
 853 #define  MCSR3_PAMVER                   (_ULCAST_(0x7) << MCSR3_PAMVER_SHIFT)
 854 #define  MCSR3_PMP_SHIFT                0
 855 #define  MCSR3_PMP                      (_ULCAST_(1) << MCSR3_PMP_SHIFT)
 856
 857 #define LOONGARCH_CSR_MCSR8             0xc8    /* CPUCFG16 and CPUCFG17 */
 858 #define  MCSR8_L1I_SIZE_SHIFT           56
 859 #define  MCSR8_L1I_SIZE_WIDTH           7
 860 #define  MCSR8_L1I_SIZE                 (_ULCAST_(0x7f) << MCSR8_L1I_SIZE_SHIFT)
 861 #define  MCSR8_L1I_IDX_SHIFT            48
 862 #define  MCSR8_L1I_IDX_WIDTH            8
 863 #define  MCSR8_L1I_IDX                  (_ULCAST_(0xff) << MCSR8_L1I_IDX_SHIFT)
 864 #define  MCSR8_L1I_WAY_SHIFT            32
 865 #define  MCSR8_L1I_WAY_WIDTH            16
 866 #define  MCSR8_L1I_WAY                  (_ULCAST_(0xffff) << MCSR8_L1I_WAY_SHIFT)
 867 #define  MCSR8_L3DINCL_SHIFT            16
 868 #define  MCSR8_L3DINCL                  (_ULCAST_(1) << MCSR8_L3DINCL_SHIFT)
 869 #define  MCSR8_L3DPRIV_SHIFT            15
 870 #define  MCSR8_L3DPRIV                  (_ULCAST_(1) << MCSR8_L3DPRIV_SHIFT)
 871 #define  MCSR8_L3DPRE_SHIFT             14
 872 #define  MCSR8_L3DPRE                   (_ULCAST_(1) << MCSR8_L3DPRE_SHIFT)
 873 #define  MCSR8_L3IUINCL_SHIFT           13
 874 #define  MCSR8_L3IUINCL                 (_ULCAST_(1) << MCSR8_L3IUINCL_SHIFT)
 875 #define  MCSR8_L3IUPRIV_SHIFT           12
 876 #define  MCSR8_L3IUPRIV                 (_ULCAST_(1) << MCSR8_L3IUPRIV_SHIFT)
 877 #define  MCSR8_L3IUUNIFY_SHIFT          11
 878 #define  MCSR8_L3IUUNIFY                (_ULCAST_(1) << MCSR8_L3IUUNIFY_SHIFT)
 879 #define  MCSR8_L3IUPRE_SHIFT            10
 880 #define  MCSR8_L3IUPRE                  (_ULCAST_(1) << MCSR8_L3IUPRE_SHIFT)
 881 #define  MCSR8_L2DINCL_SHIFT            9
 882 #define  MCSR8_L2DINCL                  (_ULCAST_(1) << MCSR8_L2DINCL_SHIFT)
 883 #define  MCSR8_L2DPRIV_SHIFT            8
 884 #define  MCSR8_L2DPRIV                  (_ULCAST_(1) << MCSR8_L2DPRIV_SHIFT)
 885 #define  MCSR8_L2DPRE_SHIFT             7
 886 #define  MCSR8_L2DPRE                   (_ULCAST_(1) << MCSR8_L2DPRE_SHIFT)
 887 #define  MCSR8_L2IUINCL_SHIFT           6
 888 #define  MCSR8_L2IUINCL                 (_ULCAST_(1) << MCSR8_L2IUINCL_SHIFT)
 889 #define  MCSR8_L2IUPRIV_SHIFT           5
 890 #define  MCSR8_L2IUPRIV                 (_ULCAST_(1) << MCSR8_L2IUPRIV_SHIFT)
 891 #define  MCSR8_L2IUUNIFY_SHIFT          4
 892 #define  MCSR8_L2IUUNIFY                (_ULCAST_(1) << MCSR8_L2IUUNIFY_SHIFT)
 893 #define  MCSR8_L2IUPRE_SHIFT            3
 894 #define  MCSR8_L2IUPRE                  (_ULCAST_(1) << MCSR8_L2IUPRE_SHIFT)
 895 #define  MCSR8_L1DPRE_SHIFT             2
 896 #define  MCSR8_L1DPRE                   (_ULCAST_(1) << MCSR8_L1DPRE_SHIFT)
 897 #define  MCSR8_L1IUUNIFY_SHIFT          1
 898 #define  MCSR8_L1IUUNIFY                (_ULCAST_(1) << MCSR8_L1IUUNIFY_SHIFT)
 899 #define  MCSR8_L1IUPRE_SHIFT            0
 900 #define  MCSR8_L1IUPRE                  (_ULCAST_(1) << MCSR8_L1IUPRE_SHIFT)
 901
 902 #define LOONGARCH_CSR_MCSR9             0xc9    /* CPUCFG18 and CPUCFG19 */
 903 #define  MCSR9_L2U_SIZE_SHIFT           56
 904 #define  MCSR9_L2U_SIZE_WIDTH           7
 905 #define  MCSR9_L2U_SIZE                 (_ULCAST_(0x7f) << MCSR9_L2U_SIZE_SHIFT)
 906 #define  MCSR9_L2U_IDX_SHIFT            48
 907 #define  MCSR9_L2U_IDX_WIDTH            8
 908 #define  MCSR9_L2U_IDX                  (_ULCAST_(0xff) << MCSR9_IDX_LOG_SHIFT)
 909 #define  MCSR9_L2U_WAY_SHIFT            32
 910 #define  MCSR9_L2U_WAY_WIDTH            16
 911 #define  MCSR9_L2U_WAY                  (_ULCAST_(0xffff) << MCSR9_L2U_WAY_SHIFT)
 912 #define  MCSR9_L1D_SIZE_SHIFT           24
 913 #define  MCSR9_L1D_SIZE_WIDTH           7
 914 #define  MCSR9_L1D_SIZE                 (_ULCAST_(0x7f) << MCSR9_L1D_SIZE_SHIFT)
 915 #define  MCSR9_L1D_IDX_SHIFT            16
 916 #define  MCSR9_L1D_IDX_WIDTH            8
 917 #define  MCSR9_L1D_IDX                  (_ULCAST_(0xff) << MCSR9_L1D_IDX_SHIFT)
 918 #define  MCSR9_L1D_WAY_SHIFT            0
 919 #define  MCSR9_L1D_WAY_WIDTH            16
 920 #define  MCSR9_L1D_WAY                  (_ULCAST_(0xffff) << MCSR9_L1D_WAY_SHIFT)
 921
 922 #define LOONGARCH_CSR_MCSR10            0xca    /* CPUCFG20 */
 923 #define  MCSR10_L3U_SIZE_SHIFT          24
 924 #define  MCSR10_L3U_SIZE_WIDTH          7
 925 #define  MCSR10_L3U_SIZE                (_ULCAST_(0x7f) << MCSR10_L3U_SIZE_SHIFT)
 926 #define  MCSR10_L3U_IDX_SHIFT           16
 927 #define  MCSR10_L3U_IDX_WIDTH           8
 928 #define  MCSR10_L3U_IDX                 (_ULCAST_(0xff) << MCSR10_L3U_IDX_SHIFT)
 929 #define  MCSR10_L3U_WAY_SHIFT           0
 930 #define  MCSR10_L3U_WAY_WIDTH           16
 931 #define  MCSR10_L3U_WAY                 (_ULCAST_(0xffff) << MCSR10_L3U_WAY_SHIFT)
 932
 933 #define LOONGARCH_CSR_MCSR24            0xf0    /* cpucfg48 */
 934 #define  MCSR24_RAMCG_SHIFT             3
 935 #define  MCSR24_RAMCG                   (_ULCAST_(1) << MCSR24_RAMCG_SHIFT)
 936 #define  MCSR24_VFPUCG_SHIFT            2
 937 #define  MCSR24_VFPUCG                  (_ULCAST_(1) << MCSR24_VFPUCG_SHIFT)
 938 #define  MCSR24_NAPEN_SHIFT             1
 939 #define  MCSR24_NAPEN                   (_ULCAST_(1) << MCSR24_NAPEN_SHIFT)
 940 #define  MCSR24_MCSRLOCK_SHIFT          0
 941 #define  MCSR24_MCSRLOCK                (_ULCAST_(1) << MCSR24_MCSRLOCK_SHIFT)
 942
 943 /* Uncached accelerate windows registers */
 944 #define LOONGARCH_CSR_UCAWIN            0x100
 945 #define LOONGARCH_CSR_UCAWIN0_LO        0x102
 946 #define LOONGARCH_CSR_UCAWIN0_HI        0x103
 947 #define LOONGARCH_CSR_UCAWIN1_LO        0x104
 948 #define LOONGARCH_CSR_UCAWIN1_HI        0x105
 949 #define LOONGARCH_CSR_UCAWIN2_LO        0x106
 950 #define LOONGARCH_CSR_UCAWIN2_HI        0x107
 951 #define LOONGARCH_CSR_UCAWIN3_LO        0x108
 952 #define LOONGARCH_CSR_UCAWIN3_HI        0x109
 953
 954 /* Direct Map windows registers */
 955 #define LOONGARCH_CSR_DMWIN0            0x180   /* 64 direct map win0: MEM & IF */
 956 #define LOONGARCH_CSR_DMWIN1            0x181   /* 64 direct map win1: MEM & IF */
 957 #define LOONGARCH_CSR_DMWIN2            0x182   /* 64 direct map win2: MEM */
 958 #define LOONGARCH_CSR_DMWIN3            0x183   /* 64 direct map win3: MEM */
 959
 960 /* Direct Map window 0/1 */
 961 #define CSR_DMW0_PLV0           _CONST64_(1 << 0)
 962 #define CSR_DMW0_VSEG           _CONST64_(0x8000)
 963 #define CSR_DMW0_BASE           (CSR_DMW0_VSEG << DMW_PABITS)
 964 #define CSR_DMW0_INIT           (CSR_DMW0_BASE | CSR_DMW0_PLV0)
 965
 966 #define CSR_DMW1_PLV0           _CONST64_(1 << 0)
 967 #define CSR_DMW1_MAT            _CONST64_(1 << 4)
 968 #define CSR_DMW1_VSEG           _CONST64_(0x9000)
 969 #define CSR_DMW1_BASE           (CSR_DMW1_VSEG << DMW_PABITS)
 970 #define CSR_DMW1_INIT           (CSR_DMW1_BASE | CSR_DMW1_MAT | CSR_DMW1_PLV0)
 971
 972 /* Performance Counter registers */
 973 #define LOONGARCH_CSR_PERFCTRL0         0x200   /* 32 perf event 0 config */
 974 #define LOONGARCH_CSR_PERFCNTR0         0x201   /* 64 perf event 0 count value */
 975 #define LOONGARCH_CSR_PERFCTRL1         0x202   /* 32 perf event 1 config */
 976 #define LOONGARCH_CSR_PERFCNTR1         0x203   /* 64 perf event 1 count value */
 977 #define LOONGARCH_CSR_PERFCTRL2         0x204   /* 32 perf event 2 config */
 978 #define LOONGARCH_CSR_PERFCNTR2         0x205   /* 64 perf event 2 count value */
 979 #define LOONGARCH_CSR_PERFCTRL3         0x206   /* 32 perf event 3 config */
 980 #define LOONGARCH_CSR_PERFCNTR3         0x207   /* 64 perf event 3 count value */
 981 #define  CSR_PERFCTRL_PLV0              (_ULCAST_(1) << 16)
 982 #define  CSR_PERFCTRL_PLV1              (_ULCAST_(1) << 17)
 983 #define  CSR_PERFCTRL_PLV2              (_ULCAST_(1) << 18)
 984 #define  CSR_PERFCTRL_PLV3              (_ULCAST_(1) << 19)
 985 #define  CSR_PERFCTRL_IE                (_ULCAST_(1) << 20)
 986 #define  CSR_PERFCTRL_EVENT             0x3ff
 987
 988 /* Debug registers */
 989 #define LOONGARCH_CSR_MWPC              0x300   /* data breakpoint config */
 990 #define LOONGARCH_CSR_MWPS              0x301   /* data breakpoint status */
 991
 992 #define LOONGARCH_CSR_DB0ADDR           0x310   /* data breakpoint 0 address */
 993 #define LOONGARCH_CSR_DB0MASK           0x311   /* data breakpoint 0 mask */
 994 #define LOONGARCH_CSR_DB0CTL            0x312   /* data breakpoint 0 control */
 995 #define LOONGARCH_CSR_DB0ASID           0x313   /* data breakpoint 0 asid */
 996
 997 #define LOONGARCH_CSR_DB1ADDR           0x318   /* data breakpoint 1 address */
 998 #define LOONGARCH_CSR_DB1MASK           0x319   /* data breakpoint 1 mask */
 999 #define LOONGARCH_CSR_DB1CTL            0x31a   /* data breakpoint 1 control */
1000 #define LOONGARCH_CSR_DB1ASID           0x31b   /* data breakpoint 1 asid */
1001
1002 #define LOONGARCH_CSR_DB2ADDR           0x320   /* data breakpoint 2 address */
1003 #define LOONGARCH_CSR_DB2MASK           0x321   /* data breakpoint 2 mask */
1004 #define LOONGARCH_CSR_DB2CTL            0x322   /* data breakpoint 2 control */
1005 #define LOONGARCH_CSR_DB2ASID           0x323   /* data breakpoint 2 asid */
1006
1007 #define LOONGARCH_CSR_DB3ADDR           0x328   /* data breakpoint 3 address */
1008 #define LOONGARCH_CSR_DB3MASK           0x329   /* data breakpoint 3 mask */
1009 #define LOONGARCH_CSR_DB3CTL            0x32a   /* data breakpoint 3 control */
1010 #define LOONGARCH_CSR_DB3ASID           0x32b   /* data breakpoint 3 asid */
1011
1012 #define LOONGARCH_CSR_DB4ADDR           0x330   /* data breakpoint 4 address */
1013 #define LOONGARCH_CSR_DB4MASK           0x331   /* data breakpoint 4 maks */
1014 #define LOONGARCH_CSR_DB4CTL            0x332   /* data breakpoint 4 control */
1015 #define LOONGARCH_CSR_DB4ASID           0x333   /* data breakpoint 4 asid */
1016
1017 #define LOONGARCH_CSR_DB5ADDR           0x338   /* data breakpoint 5 address */
1018 #define LOONGARCH_CSR_DB5MASK           0x339   /* data breakpoint 5 mask */
1019 #define LOONGARCH_CSR_DB5CTL            0x33a   /* data breakpoint 5 control */
1020 #define LOONGARCH_CSR_DB5ASID           0x33b   /* data breakpoint 5 asid */
1021
1022 #define LOONGARCH_CSR_DB6ADDR           0x340   /* data breakpoint 6 address */
1023 #define LOONGARCH_CSR_DB6MASK           0x341   /* data breakpoint 6 mask */
1024 #define LOONGARCH_CSR_DB6CTL            0x342   /* data breakpoint 6 control */
1025 #define LOONGARCH_CSR_DB6ASID           0x343   /* data breakpoint 6 asid */
1026
1027 #define LOONGARCH_CSR_DB7ADDR           0x348   /* data breakpoint 7 address */
1028 #define LOONGARCH_CSR_DB7MASK           0x349   /* data breakpoint 7 mask */
1029 #define LOONGARCH_CSR_DB7CTL            0x34a   /* data breakpoint 7 control */
1030 #define LOONGARCH_CSR_DB7ASID           0x34b   /* data breakpoint 7 asid */
1031
1032 #define LOONGARCH_CSR_FWPC              0x380   /* instruction breakpoint config */
1033 #define LOONGARCH_CSR_FWPS              0x381   /* instruction breakpoint status */
1034
1035 #define LOONGARCH_CSR_IB0ADDR           0x390   /* inst breakpoint 0 address */
1036 #define LOONGARCH_CSR_IB0MASK           0x391   /* inst breakpoint 0 mask */
1037 #define LOONGARCH_CSR_IB0CTL            0x392   /* inst breakpoint 0 control */
1038 #define LOONGARCH_CSR_IB0ASID           0x393   /* inst breakpoint 0 asid */
1039
1040 #define LOONGARCH_CSR_IB1ADDR           0x398   /* inst breakpoint 1 address */
1041 #define LOONGARCH_CSR_IB1MASK           0x399   /* inst breakpoint 1 mask */
1042 #define LOONGARCH_CSR_IB1CTL            0x39a   /* inst breakpoint 1 control */
1043 #define LOONGARCH_CSR_IB1ASID           0x39b   /* inst breakpoint 1 asid */
1044
1045 #define LOONGARCH_CSR_IB2ADDR           0x3a0   /* inst breakpoint 2 address */
1046 #define LOONGARCH_CSR_IB2MASK           0x3a1   /* inst breakpoint 2 mask */
1047 #define LOONGARCH_CSR_IB2CTL            0x3a2   /* inst breakpoint 2 control */
1048 #define LOONGARCH_CSR_IB2ASID           0x3a3   /* inst breakpoint 2 asid */
1049
1050 #define LOONGARCH_CSR_IB3ADDR           0x3a8   /* inst breakpoint 3 address */
1051 #define LOONGARCH_CSR_IB3MASK           0x3a9   /* breakpoint 3 mask */
1052 #define LOONGARCH_CSR_IB3CTL            0x3aa   /* inst breakpoint 3 control */
1053 #define LOONGARCH_CSR_IB3ASID           0x3ab   /* inst breakpoint 3 asid */
1054
1055 #define LOONGARCH_CSR_IB4ADDR           0x3b0   /* inst breakpoint 4 address */
1056 #define LOONGARCH_CSR_IB4MASK           0x3b1   /* inst breakpoint 4 mask */
1057 #define LOONGARCH_CSR_IB4CTL            0x3b2   /* inst breakpoint 4 control */
1058 #define LOONGARCH_CSR_IB4ASID           0x3b3   /* inst breakpoint 4 asid */
1059
1060 #define LOONGARCH_CSR_IB5ADDR           0x3b8   /* inst breakpoint 5 address */
1061 #define LOONGARCH_CSR_IB5MASK           0x3b9   /* inst breakpoint 5 mask */
1062 #define LOONGARCH_CSR_IB5CTL            0x3ba   /* inst breakpoint 5 control */
1063 #define LOONGARCH_CSR_IB5ASID           0x3bb   /* inst breakpoint 5 asid */
1064
1065 #define LOONGARCH_CSR_IB6ADDR           0x3c0   /* inst breakpoint 6 address */
1066 #define LOONGARCH_CSR_IB6MASK           0x3c1   /* inst breakpoint 6 mask */
1067 #define LOONGARCH_CSR_IB6CTL            0x3c2   /* inst breakpoint 6 control */
1068 #define LOONGARCH_CSR_IB6ASID           0x3c3   /* inst breakpoint 6 asid */
1069
1070 #define LOONGARCH_CSR_IB7ADDR           0x3c8   /* inst breakpoint 7 address */
1071 #define LOONGARCH_CSR_IB7MASK           0x3c9   /* inst breakpoint 7 mask */
1072 #define LOONGARCH_CSR_IB7CTL            0x3ca   /* inst breakpoint 7 control */
1073 #define LOONGARCH_CSR_IB7ASID           0x3cb   /* inst breakpoint 7 asid */
1074
1075 #define LOONGARCH_CSR_DEBUG             0x500   /* debug config */
1076 #define LOONGARCH_CSR_DERA              0x501   /* debug era */
1077 #define LOONGARCH_CSR_DESAVE            0x502   /* debug save */
1078
1079 /*
1080  * CSR_ECFG IM
1081  */
1082 #define ECFG0_IM                0x00001fff
1083 #define ECFGB_SIP0              0
1084 #define ECFGF_SIP0              (_ULCAST_(1) << ECFGB_SIP0)
1085 #define ECFGB_SIP1              1
1086 #define ECFGF_SIP1              (_ULCAST_(1) << ECFGB_SIP1)
1087 #define ECFGB_IP0               2
1088 #define ECFGF_IP0               (_ULCAST_(1) << ECFGB_IP0)
1089 #define ECFGB_IP1               3
1090 #define ECFGF_IP1               (_ULCAST_(1) << ECFGB_IP1)
1091 #define ECFGB_IP2               4
1092 #define ECFGF_IP2               (_ULCAST_(1) << ECFGB_IP2)
1093 #define ECFGB_IP3               5
1094 #define ECFGF_IP3               (_ULCAST_(1) << ECFGB_IP3)
1095 #define ECFGB_IP4               6
1096 #define ECFGF_IP4               (_ULCAST_(1) << ECFGB_IP4)
1097 #define ECFGB_IP5               7
1098 #define ECFGF_IP5               (_ULCAST_(1) << ECFGB_IP5)
1099 #define ECFGB_IP6               8
1100 #define ECFGF_IP6               (_ULCAST_(1) << ECFGB_IP6)
1101 #define ECFGB_IP7               9
1102 #define ECFGF_IP7               (_ULCAST_(1) << ECFGB_IP7)
1103 #define ECFGB_PMC               10
1104 #define ECFGF_PMC               (_ULCAST_(1) << ECFGB_PMC)
1105 #define ECFGB_TIMER             11
1106 #define ECFGF_TIMER             (_ULCAST_(1) << ECFGB_TIMER)
1107 #define ECFGB_IPI               12
1108 #define ECFGF_IPI               (_ULCAST_(1) << ECFGB_IPI)
1109 #define ECFGF(hwirq)            (_ULCAST_(1) << hwirq)
1110
1111 #define ESTATF_IP               0x00001fff
1112
1113 #define LOONGARCH_IOCSR_FEATURES        0x8
1114 #define  IOCSRF_TEMP                    BIT_ULL(0)
1115 #define  IOCSRF_NODECNT                 BIT_ULL(1)
1116 #define  IOCSRF_MSI                     BIT_ULL(2)
1117 #define  IOCSRF_EXTIOI                  BIT_ULL(3)
1118 #define  IOCSRF_CSRIPI                  BIT_ULL(4)
1119 #define  IOCSRF_FREQCSR                 BIT_ULL(5)
1120 #define  IOCSRF_FREQSCALE               BIT_ULL(6)
1121 #define  IOCSRF_DVFSV1                  BIT_ULL(7)
1122 #define  IOCSRF_EIODECODE               BIT_ULL(9)
1123 #define  IOCSRF_FLATMODE                BIT_ULL(10)
1124 #define  IOCSRF_VM                      BIT_ULL(11)
1125
1126 #define LOONGARCH_IOCSR_VENDOR          0x10
1127
1128 #define LOONGARCH_IOCSR_CPUNAME         0x20
1129
1130 #define LOONGARCH_IOCSR_NODECNT         0x408
1131
1132 #define LOONGARCH_IOCSR_MISC_FUNC       0x420
1133 #define  IOCSR_MISC_FUNC_TIMER_RESET    BIT_ULL(21)
1134 #define  IOCSR_MISC_FUNC_EXT_IOI_EN     BIT_ULL(48)
1135
1136 #define LOONGARCH_IOCSR_CPUTEMP         0x428
1137
1138 /* PerCore CSR, only accessible by local cores */
1139 #define LOONGARCH_IOCSR_IPI_STATUS      0x1000
1140 #define LOONGARCH_IOCSR_IPI_EN          0x1004
1141 #define LOONGARCH_IOCSR_IPI_SET         0x1008
1142 #define LOONGARCH_IOCSR_IPI_CLEAR       0x100c
1143 #define LOONGARCH_IOCSR_MBUF0           0x1020
1144 #define LOONGARCH_IOCSR_MBUF1           0x1028
1145 #define LOONGARCH_IOCSR_MBUF2           0x1030
1146 #define LOONGARCH_IOCSR_MBUF3           0x1038
1147
1148 #define LOONGARCH_IOCSR_IPI_SEND        0x1040
1149 #define  IOCSR_IPI_SEND_IP_SHIFT        0
1150 #define  IOCSR_IPI_SEND_CPU_SHIFT       16
1151 #define  IOCSR_IPI_SEND_BLOCKING        BIT(31)
1152
1153 #define LOONGARCH_IOCSR_MBUF_SEND       0x1048
1154 #define  IOCSR_MBUF_SEND_BLOCKING       BIT_ULL(31)
1155 #define  IOCSR_MBUF_SEND_BOX_SHIFT      2
1156 #define  IOCSR_MBUF_SEND_BOX_LO(box)    (box << 1)
1157 #define  IOCSR_MBUF_SEND_BOX_HI(box)    ((box << 1) + 1)
1158 #define  IOCSR_MBUF_SEND_CPU_SHIFT      16
1159 #define  IOCSR_MBUF_SEND_BUF_SHIFT      32
1160 #define  IOCSR_MBUF_SEND_H32_MASK       0xFFFFFFFF00000000ULL
1161
1162 #define LOONGARCH_IOCSR_ANY_SEND        0x1158
1163 #define  IOCSR_ANY_SEND_BLOCKING        BIT_ULL(31)
1164 #define  IOCSR_ANY_SEND_CPU_SHIFT       16
1165 #define  IOCSR_ANY_SEND_MASK_SHIFT      27
1166 #define  IOCSR_ANY_SEND_BUF_SHIFT       32
1167 #define  IOCSR_ANY_SEND_H32_MASK        0xFFFFFFFF00000000ULL
1168
1169 /* Register offset and bit definition for CSR access */
1170 #define LOONGARCH_IOCSR_TIMER_CFG       0x1060
1171 #define LOONGARCH_IOCSR_TIMER_TICK      0x1070
1172 #define  IOCSR_TIMER_CFG_RESERVED       (_ULCAST_(1) << 63)
1173 #define  IOCSR_TIMER_CFG_PERIODIC       (_ULCAST_(1) << 62)
1174 #define  IOCSR_TIMER_CFG_EN             (_ULCAST_(1) << 61)
1175 #define  IOCSR_TIMER_MASK               0x0ffffffffffffULL
1176 #define  IOCSR_TIMER_INITVAL_RST        (_ULCAST_(0xffff) << 48)
1177
1178 #define LOONGARCH_IOCSR_EXTIOI_NODEMAP_BASE     0x14a0
1179 #define LOONGARCH_IOCSR_EXTIOI_IPMAP_BASE       0x14c0
1180 #define LOONGARCH_IOCSR_EXTIOI_EN_BASE          0x1600
1181 #define LOONGARCH_IOCSR_EXTIOI_BOUNCE_BASE      0x1680
1182 #define LOONGARCH_IOCSR_EXTIOI_ISR_BASE         0x1800
1183 #define LOONGARCH_IOCSR_EXTIOI_ROUTE_BASE       0x1c00
1184 #define IOCSR_EXTIOI_VECTOR_NUM                 256
1185
1186 #ifndef __ASSEMBLY__
1187
1188 static inline u64 drdtime(void)
1189 {
1190         int rID = 0;
1191         u64 val = 0;
1192
1193         __asm__ __volatile__(
1194                 "rdtime.d %0, %1 \n\t"
1195                 : "=r"(val), "=r"(rID)
1196                 :
1197                 );
1198         return val;
1199 }
1200
1201 static inline unsigned int get_csr_cpuid(void)
1202 {
1203         return csr_read32(LOONGARCH_CSR_CPUID);
1204 }
1205
1206 static inline void csr_any_send(unsigned int addr, unsigned int data,
1207                                 unsigned int data_mask, unsigned int cpu)
1208 {
1209         uint64_t val = 0;
1210
1211         val = IOCSR_ANY_SEND_BLOCKING | addr;
1212         val |= (cpu << IOCSR_ANY_SEND_CPU_SHIFT);
1213         val |= (data_mask << IOCSR_ANY_SEND_MASK_SHIFT);
1214         val |= ((uint64_t)data << IOCSR_ANY_SEND_BUF_SHIFT);
1215         iocsr_write64(val, LOONGARCH_IOCSR_ANY_SEND);
1216 }
1217
1218 static inline unsigned int read_csr_excode(void)
1219 {
1220         return (csr_read32(LOONGARCH_CSR_ESTAT) & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT;
1221 }
1222
1223 static inline void write_csr_index(unsigned int idx)
1224 {
1225         csr_xchg32(idx, CSR_TLBIDX_IDXM, LOONGARCH_CSR_TLBIDX);
1226 }
1227
1228 static inline unsigned int read_csr_pagesize(void)
1229 {
1230         return (csr_read32(LOONGARCH_CSR_TLBIDX) & CSR_TLBIDX_SIZEM) >> CSR_TLBIDX_SIZE;
1231 }
1232
1233 static inline void write_csr_pagesize(unsigned int size)
1234 {
1235         csr_xchg32(size << CSR_TLBIDX_SIZE, CSR_TLBIDX_SIZEM, LOONGARCH_CSR_TLBIDX);
1236 }
1237
1238 static inline unsigned int read_csr_tlbrefill_pagesize(void)
1239 {
1240         return (csr_read64(LOONGARCH_CSR_TLBREHI) & CSR_TLBREHI_PS) >> CSR_TLBREHI_PS_SHIFT;
1241 }
1242
1243 static inline void write_csr_tlbrefill_pagesize(unsigned int size)
1244 {
1245         csr_xchg64(size << CSR_TLBREHI_PS_SHIFT, CSR_TLBREHI_PS, LOONGARCH_CSR_TLBREHI);
1246 }
1247
1248 #define read_csr_asid()                 csr_read32(LOONGARCH_CSR_ASID)
1249 #define write_csr_asid(val)             csr_write32(val, LOONGARCH_CSR_ASID)
1250 #define read_csr_entryhi()              csr_read64(LOONGARCH_CSR_TLBEHI)
1251 #define write_csr_entryhi(val)          csr_write64(val, LOONGARCH_CSR_TLBEHI)
1252 #define read_csr_entrylo0()             csr_read64(LOONGARCH_CSR_TLBELO0)
1253 #define write_csr_entrylo0(val)         csr_write64(val, LOONGARCH_CSR_TLBELO0)
1254 #define read_csr_entrylo1()             csr_read64(LOONGARCH_CSR_TLBELO1)
1255 #define write_csr_entrylo1(val)         csr_write64(val, LOONGARCH_CSR_TLBELO1)
1256 #define read_csr_ecfg()                 csr_read32(LOONGARCH_CSR_ECFG)
1257 #define write_csr_ecfg(val)             csr_write32(val, LOONGARCH_CSR_ECFG)
1258 #define read_csr_estat()                csr_read32(LOONGARCH_CSR_ESTAT)
1259 #define write_csr_estat(val)            csr_write32(val, LOONGARCH_CSR_ESTAT)
1260 #define read_csr_tlbidx()               csr_read32(LOONGARCH_CSR_TLBIDX)
1261 #define write_csr_tlbidx(val)           csr_write32(val, LOONGARCH_CSR_TLBIDX)
1262 #define read_csr_euen()                 csr_read32(LOONGARCH_CSR_EUEN)
1263 #define write_csr_euen(val)             csr_write32(val, LOONGARCH_CSR_EUEN)
1264 #define read_csr_cpuid()                csr_read32(LOONGARCH_CSR_CPUID)
1265 #define read_csr_prcfg1()               csr_read64(LOONGARCH_CSR_PRCFG1)
1266 #define write_csr_prcfg1(val)           csr_write64(val, LOONGARCH_CSR_PRCFG1)
1267 #define read_csr_prcfg2()               csr_read64(LOONGARCH_CSR_PRCFG2)
1268 #define write_csr_prcfg2(val)           csr_write64(val, LOONGARCH_CSR_PRCFG2)
1269 #define read_csr_prcfg3()               csr_read64(LOONGARCH_CSR_PRCFG3)
1270 #define write_csr_prcfg3(val)           csr_write64(val, LOONGARCH_CSR_PRCFG3)
1271 #define read_csr_stlbpgsize()           csr_read32(LOONGARCH_CSR_STLBPGSIZE)
1272 #define write_csr_stlbpgsize(val)       csr_write32(val, LOONGARCH_CSR_STLBPGSIZE)
1273 #define read_csr_rvacfg()               csr_read32(LOONGARCH_CSR_RVACFG)
1274 #define write_csr_rvacfg(val)           csr_write32(val, LOONGARCH_CSR_RVACFG)
1275 #define write_csr_tintclear(val)        csr_write32(val, LOONGARCH_CSR_TINTCLR)
1276 #define read_csr_impctl1()              csr_read64(LOONGARCH_CSR_IMPCTL1)
1277 #define write_csr_impctl1(val)          csr_write64(val, LOONGARCH_CSR_IMPCTL1)
1278 #define write_csr_impctl2(val)          csr_write64(val, LOONGARCH_CSR_IMPCTL2)
1279
1280 #define read_csr_perfctrl0()            csr_read64(LOONGARCH_CSR_PERFCTRL0)
1281 #define read_csr_perfcntr0()            csr_read64(LOONGARCH_CSR_PERFCNTR0)
1282 #define read_csr_perfctrl1()            csr_read64(LOONGARCH_CSR_PERFCTRL1)
1283 #define read_csr_perfcntr1()            csr_read64(LOONGARCH_CSR_PERFCNTR1)
1284 #define read_csr_perfctrl2()            csr_read64(LOONGARCH_CSR_PERFCTRL2)
1285 #define read_csr_perfcntr2()            csr_read64(LOONGARCH_CSR_PERFCNTR2)
1286 #define read_csr_perfctrl3()            csr_read64(LOONGARCH_CSR_PERFCTRL3)
1287 #define read_csr_perfcntr3()            csr_read64(LOONGARCH_CSR_PERFCNTR3)
1288 #define write_csr_perfctrl0(val)        csr_write64(val, LOONGARCH_CSR_PERFCTRL0)
1289 #define write_csr_perfcntr0(val)        csr_write64(val, LOONGARCH_CSR_PERFCNTR0)
1290 #define write_csr_perfctrl1(val)        csr_write64(val, LOONGARCH_CSR_PERFCTRL1)
1291 #define write_csr_perfcntr1(val)        csr_write64(val, LOONGARCH_CSR_PERFCNTR1)
1292 #define write_csr_perfctrl2(val)        csr_write64(val, LOONGARCH_CSR_PERFCTRL2)
1293 #define write_csr_perfcntr2(val)        csr_write64(val, LOONGARCH_CSR_PERFCNTR2)
1294 #define write_csr_perfctrl3(val)        csr_write64(val, LOONGARCH_CSR_PERFCTRL3)
1295 #define write_csr_perfcntr3(val)        csr_write64(val, LOONGARCH_CSR_PERFCNTR3)
1296
1297 /*
1298  * Manipulate bits in a register.
1299  */
1300 #define __BUILD_CSR_COMMON(name)                                \
1301 static inline unsigned long                                     \
1302 set_##name(unsigned long set)                                   \
1303 {                                                               \
1304         unsigned long res, new;                                 \
1305                                                                 \
1306         res = read_##name();                                    \
1307         new = res | set;                                        \
1308         write_##name(new);                                      \
1309                                                                 \
1310         return res;                                             \
1311 }                                                               \
1312                                                                 \
1313 static inline unsigned long                                     \
1314 clear_##name(unsigned long clear)                               \
1315 {                                                               \
1316         unsigned long res, new;                                 \
1317                                                                 \
1318         res = read_##name();                                    \
1319         new = res & ~clear;                                     \
1320         write_##name(new);                                      \
1321                                                                 \
1322         return res;                                             \
1323 }                                                               \
1324                                                                 \
1325 static inline unsigned long                                     \
1326 change_##name(unsigned long change, unsigned long val)          \
1327 {                                                               \
1328         unsigned long res, new;                                 \
1329                                                                 \
1330         res = read_##name();                                    \
1331         new = res & ~change;                                    \
1332         new |= (val & change);                                  \
1333         write_##name(new);                                      \
1334                                                                 \
1335         return res;                                             \
1336 }
1337
1338 #define __BUILD_CSR_OP(name)    __BUILD_CSR_COMMON(csr_##name)
1339
1340 __BUILD_CSR_OP(euen)
1341 __BUILD_CSR_OP(ecfg)
1342 __BUILD_CSR_OP(tlbidx)
1343
1344 #define set_csr_estat(val)      \
1345         csr_xchg32(val, val, LOONGARCH_CSR_ESTAT)
1346 #define clear_csr_estat(val)    \
1347         csr_xchg32(~(val), val, LOONGARCH_CSR_ESTAT)
1348
1349 #endif /* __ASSEMBLY__ */
1350
1351 /* Generic EntryLo bit definitions */
1352 #define ENTRYLO_V               (_ULCAST_(1) << 0)
1353 #define ENTRYLO_D               (_ULCAST_(1) << 1)
1354 #define ENTRYLO_PLV_SHIFT       2
1355 #define ENTRYLO_PLV             (_ULCAST_(3) << ENTRYLO_PLV_SHIFT)
1356 #define ENTRYLO_C_SHIFT         4
1357 #define ENTRYLO_C               (_ULCAST_(3) << ENTRYLO_C_SHIFT)
1358 #define ENTRYLO_G               (_ULCAST_(1) << 6)
1359 #define ENTRYLO_NR              (_ULCAST_(1) << 61)
1360 #define ENTRYLO_NX              (_ULCAST_(1) << 62)
1361
1362 /* Values for PageSize register */
1363 #define PS_4K           0x0000000c
1364 #define PS_8K           0x0000000d
1365 #define PS_16K          0x0000000e
1366 #define PS_32K          0x0000000f
1367 #define PS_64K          0x00000010
1368 #define PS_128K         0x00000011
1369 #define PS_256K         0x00000012
1370 #define PS_512K         0x00000013
1371 #define PS_1M           0x00000014
1372 #define PS_2M           0x00000015
1373 #define PS_4M           0x00000016
1374 #define PS_8M           0x00000017
1375 #define PS_16M          0x00000018
1376 #define PS_32M          0x00000019
1377 #define PS_64M          0x0000001a
1378 #define PS_128M         0x0000001b
1379 #define PS_256M         0x0000001c
1380 #define PS_512M         0x0000001d
1381 #define PS_1G           0x0000001e
1382
1383 /* Default page size for a given kernel configuration */
1384 #ifdef CONFIG_PAGE_SIZE_4KB
1385 #define PS_DEFAULT_SIZE PS_4K
1386 #elif defined(CONFIG_PAGE_SIZE_16KB)
1387 #define PS_DEFAULT_SIZE PS_16K
1388 #elif defined(CONFIG_PAGE_SIZE_64KB)
1389 #define PS_DEFAULT_SIZE PS_64K
1390 #else
1391 #error Bad page size configuration!
1392 #endif
1393
1394 /* Default huge tlb size for a given kernel configuration */
1395 #ifdef CONFIG_PAGE_SIZE_4KB
1396 #define PS_HUGE_SIZE   PS_1M
1397 #elif defined(CONFIG_PAGE_SIZE_16KB)
1398 #define PS_HUGE_SIZE   PS_16M
1399 #elif defined(CONFIG_PAGE_SIZE_64KB)
1400 #define PS_HUGE_SIZE   PS_256M
1401 #else
1402 #error Bad page size configuration for hugetlbfs!
1403 #endif
1404
1405 /* ExStatus.ExcCode */
1406 #define EXCCODE_RSV             0       /* Reserved */
1407 #define EXCCODE_TLBL            1       /* TLB miss on a load */
1408 #define EXCCODE_TLBS            2       /* TLB miss on a store */
1409 #define EXCCODE_TLBI            3       /* TLB miss on a ifetch */
1410 #define EXCCODE_TLBM            4       /* TLB modified fault */
1411 #define EXCCODE_TLBNR           5       /* TLB Read-Inhibit exception */
1412 #define EXCCODE_TLBNX           6       /* TLB Execution-Inhibit exception */
1413 #define EXCCODE_TLBPE           7       /* TLB Privilege Error */
1414 #define EXCCODE_ADE             8       /* Address Error */
1415         #define EXSUBCODE_ADEF          0       /* Fetch Instruction */
1416         #define EXSUBCODE_ADEM          1       /* Access Memory*/
1417 #define EXCCODE_ALE             9       /* Unalign Access */
1418 #define EXCCODE_OOB             10      /* Out of bounds */
1419 #define EXCCODE_SYS             11      /* System call */
1420 #define EXCCODE_BP              12      /* Breakpoint */
1421 #define EXCCODE_INE             13      /* Inst. Not Exist */
1422 #define EXCCODE_IPE             14      /* Inst. Privileged Error */
1423 #define EXCCODE_FPDIS           15      /* FPU Disabled */
1424 #define EXCCODE_LSXDIS          16      /* LSX Disabled */
1425 #define EXCCODE_LASXDIS         17      /* LASX Disabled */
1426 #define EXCCODE_FPE             18      /* Floating Point Exception */
1427         #define EXCSUBCODE_FPE          0       /* Floating Point Exception */
1428         #define EXCSUBCODE_VFPE         1       /* Vector Exception */
1429 #define EXCCODE_WATCH           19      /* Watch address reference */
1430 #define EXCCODE_BTDIS           20      /* Binary Trans. Disabled */
1431 #define EXCCODE_BTE             21      /* Binary Trans. Exception */
1432 #define EXCCODE_PSI             22      /* Guest Privileged Error */
1433 #define EXCCODE_HYP             23      /* Hypercall */
1434 #define EXCCODE_GCM             24      /* Guest CSR modified */
1435         #define EXCSUBCODE_GCSC         0       /* Software caused */
1436         #define EXCSUBCODE_GCHC         1       /* Hardware caused */
1437 #define EXCCODE_SE              25      /* Security */
1438
1439 #define EXCCODE_INT_START   64
1440 #define EXCCODE_SIP0        64
1441 #define EXCCODE_SIP1        65
1442 #define EXCCODE_IP0         66
1443 #define EXCCODE_IP1         67
1444 #define EXCCODE_IP2         68
1445 #define EXCCODE_IP3         69
1446 #define EXCCODE_IP4         70
1447 #define EXCCODE_IP5         71
1448 #define EXCCODE_IP6         72
1449 #define EXCCODE_IP7         73
1450 #define EXCCODE_PMC         74 /* Performance Counter */
1451 #define EXCCODE_TIMER       75
1452 #define EXCCODE_IPI         76
1453 #define EXCCODE_NMI         77
1454 #define EXCCODE_INT_END     78
1455 #define EXCCODE_INT_NUM     (EXCCODE_INT_END - EXCCODE_INT_START)
1456
1457 /* FPU register names */
1458 #define LOONGARCH_FCSR0 $r0
1459 #define LOONGARCH_FCSR1 $r1
1460 #define LOONGARCH_FCSR2 $r2
1461 #define LOONGARCH_FCSR3 $r3
1462
1463 /* FPU Status Register Values */
1464 #define FPU_CSR_RSVD    0xe0e0fce0
1465
1466 /*
1467  * X the exception cause indicator
1468  * E the exception enable
1469  * S the sticky/flag bit
1470  */
1471 #define FPU_CSR_ALL_X   0x1f000000
1472 #define FPU_CSR_INV_X   0x10000000
1473 #define FPU_CSR_DIV_X   0x08000000
1474 #define FPU_CSR_OVF_X   0x04000000
1475 #define FPU_CSR_UDF_X   0x02000000
1476 #define FPU_CSR_INE_X   0x01000000
1477
1478 #define FPU_CSR_ALL_S   0x001f0000
1479 #define FPU_CSR_INV_S   0x00100000
1480 #define FPU_CSR_DIV_S   0x00080000
1481 #define FPU_CSR_OVF_S   0x00040000
1482 #define FPU_CSR_UDF_S   0x00020000
1483 #define FPU_CSR_INE_S   0x00010000
1484
1485 #define FPU_CSR_ALL_E   0x0000001f
1486 #define FPU_CSR_INV_E   0x00000010
1487 #define FPU_CSR_DIV_E   0x00000008
1488 #define FPU_CSR_OVF_E   0x00000004
1489 #define FPU_CSR_UDF_E   0x00000002
1490 #define FPU_CSR_INE_E   0x00000001
1491
1492 /* Bits 8 and 9 of FPU Status Register specify the rounding mode */
1493 #define FPU_CSR_RM      0x300
1494 #define FPU_CSR_RN      0x000   /* nearest */
1495 #define FPU_CSR_RZ      0x100   /* towards zero */
1496 #define FPU_CSR_RU      0x200   /* towards +Infinity */
1497 #define FPU_CSR_RD      0x300   /* towards -Infinity */
1498
1499 #define read_fcsr(source)       \
1500 ({      \
1501         unsigned int __res;     \
1502 \
1503         __asm__ __volatile__(   \
1504         "       movfcsr2gr      %0, "__stringify(source)" \n"   \
1505         : "=r" (__res));        \
1506         __res;  \
1507 })
1508
1509 #define write_fcsr(dest, val) \
1510 do {    \
1511         __asm__ __volatile__(   \
1512         "       movgr2fcsr      %0, "__stringify(dest)" \n"     \
1513         : : "r" (val)); \
1514 } while (0)
1515
1516 #endif /* _ASM_LOONGARCH_H */