2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/config.h>
29 #include <linux/smp_lock.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/compiler.h>
32 #include <linux/acpi.h>
33 #include <linux/module.h>
34 #include <linux/sysdev.h>
39 #include <asm/timer.h>
40 #include <asm/i8259.h>
42 #include <mach_apic.h>
46 int (*ioapic_renumber_irq)(int ioapic, int irq);
47 atomic_t irq_mis_count;
49 /* Where if anywhere is the i8259 connect in external int mode */
50 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
52 static DEFINE_SPINLOCK(ioapic_lock);
53 static DEFINE_SPINLOCK(vector_lock);
55 int timer_over_8254 __initdata = 1;
58 * Is the SiS APIC rmw bug present ?
59 * -1 = don't know, 0 = no, 1 = yes
61 int sis_apic_bug = -1;
64 * # of IRQ routing registers
66 int nr_ioapic_registers[MAX_IO_APICS];
68 int disable_timer_pin_1 __initdata;
71 * Rough estimation of how many shared IRQs there are, can
74 #define MAX_PLUS_SHARED_IRQS NR_IRQS
75 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
78 * This is performance-critical, we want to do it O(1)
80 * the indexing order of this array favors 1:1 mappings
81 * between pins and IRQs.
84 static struct irq_pin_list {
86 } irq_2_pin[PIN_MAP_SIZE];
88 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
90 #define vector_to_irq(vector) \
91 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
93 #define vector_to_irq(vector) (vector)
97 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
98 * shared ISA-space IRQs, so we have to support them. We are super
99 * fast in the common case, and fast for shared ISA-space IRQs.
101 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
103 static int first_free_entry = NR_IRQS;
104 struct irq_pin_list *entry = irq_2_pin + irq;
107 entry = irq_2_pin + entry->next;
109 if (entry->pin != -1) {
110 entry->next = first_free_entry;
111 entry = irq_2_pin + entry->next;
112 if (++first_free_entry >= PIN_MAP_SIZE)
113 panic("io_apic.c: whoops");
120 * Reroute an IRQ to a different pin.
122 static void __init replace_pin_at_irq(unsigned int irq,
123 int oldapic, int oldpin,
124 int newapic, int newpin)
126 struct irq_pin_list *entry = irq_2_pin + irq;
129 if (entry->apic == oldapic && entry->pin == oldpin) {
130 entry->apic = newapic;
135 entry = irq_2_pin + entry->next;
139 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
141 struct irq_pin_list *entry = irq_2_pin + irq;
142 unsigned int pin, reg;
148 reg = io_apic_read(entry->apic, 0x10 + pin*2);
151 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
154 entry = irq_2_pin + entry->next;
159 static void __mask_IO_APIC_irq (unsigned int irq)
161 __modify_IO_APIC_irq(irq, 0x00010000, 0);
165 static void __unmask_IO_APIC_irq (unsigned int irq)
167 __modify_IO_APIC_irq(irq, 0, 0x00010000);
170 /* mask = 1, trigger = 0 */
171 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
173 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
176 /* mask = 0, trigger = 1 */
177 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
179 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
182 static void mask_IO_APIC_irq (unsigned int irq)
186 spin_lock_irqsave(&ioapic_lock, flags);
187 __mask_IO_APIC_irq(irq);
188 spin_unlock_irqrestore(&ioapic_lock, flags);
191 static void unmask_IO_APIC_irq (unsigned int irq)
195 spin_lock_irqsave(&ioapic_lock, flags);
196 __unmask_IO_APIC_irq(irq);
197 spin_unlock_irqrestore(&ioapic_lock, flags);
200 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
202 struct IO_APIC_route_entry entry;
205 /* Check delivery_mode to be sure we're not clearing an SMI pin */
206 spin_lock_irqsave(&ioapic_lock, flags);
207 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
208 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
209 spin_unlock_irqrestore(&ioapic_lock, flags);
210 if (entry.delivery_mode == dest_SMI)
214 * Disable it in the IO-APIC irq-routing table:
216 memset(&entry, 0, sizeof(entry));
218 spin_lock_irqsave(&ioapic_lock, flags);
219 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
220 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
221 spin_unlock_irqrestore(&ioapic_lock, flags);
224 static void clear_IO_APIC (void)
228 for (apic = 0; apic < nr_ioapics; apic++)
229 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
230 clear_IO_APIC_pin(apic, pin);
234 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
238 struct irq_pin_list *entry = irq_2_pin + irq;
239 unsigned int apicid_value;
242 cpus_and(tmp, cpumask, cpu_online_map);
246 cpus_and(cpumask, tmp, CPU_MASK_ALL);
248 apicid_value = cpu_mask_to_apicid(cpumask);
249 /* Prepare to do the io_apic_write */
250 apicid_value = apicid_value << 24;
251 spin_lock_irqsave(&ioapic_lock, flags);
256 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
259 entry = irq_2_pin + entry->next;
261 set_irq_info(irq, cpumask);
262 spin_unlock_irqrestore(&ioapic_lock, flags);
265 #if defined(CONFIG_IRQBALANCE)
266 # include <asm/processor.h> /* kernel_thread() */
267 # include <linux/kernel_stat.h> /* kstat */
268 # include <linux/slab.h> /* kmalloc() */
269 # include <linux/timer.h> /* time_after() */
271 #ifdef CONFIG_BALANCED_IRQ_DEBUG
272 # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
273 # define Dprintk(x...) do { TDprintk(x); } while (0)
275 # define TDprintk(x...)
276 # define Dprintk(x...)
279 #define IRQBALANCE_CHECK_ARCH -999
280 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
281 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
282 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
283 #define BALANCED_IRQ_LESS_DELTA (HZ)
285 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
286 static int physical_balance __read_mostly;
287 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
289 static struct irq_cpu_info {
290 unsigned long * last_irq;
291 unsigned long * irq_delta;
293 } irq_cpu_data[NR_CPUS];
295 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
296 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
297 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
299 #define IDLE_ENOUGH(cpu,now) \
300 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
302 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
304 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
306 static cpumask_t balance_irq_affinity[NR_IRQS] = {
307 [0 ... NR_IRQS-1] = CPU_MASK_ALL
310 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
312 balance_irq_affinity[irq] = mask;
315 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
316 unsigned long now, int direction)
324 if (unlikely(cpu == curr_cpu))
327 if (direction == 1) {
336 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
337 (search_idle && !IDLE_ENOUGH(cpu,now)));
342 static inline void balance_irq(int cpu, int irq)
344 unsigned long now = jiffies;
345 cpumask_t allowed_mask;
346 unsigned int new_cpu;
348 if (irqbalance_disabled)
351 cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
352 new_cpu = move(cpu, allowed_mask, now, 1);
353 if (cpu != new_cpu) {
354 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
358 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
361 Dprintk("Rotating IRQs among CPUs.\n");
362 for_each_online_cpu(i) {
363 for (j = 0; j < NR_IRQS; j++) {
364 if (!irq_desc[j].action)
366 /* Is it a significant load ? */
367 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
368 useful_load_threshold)
373 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
374 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
378 static void do_irq_balance(void)
381 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
382 unsigned long move_this_load = 0;
383 int max_loaded = 0, min_loaded = 0;
385 unsigned long useful_load_threshold = balanced_irq_interval + 10;
387 int tmp_loaded, first_attempt = 1;
388 unsigned long tmp_cpu_irq;
389 unsigned long imbalance = 0;
390 cpumask_t allowed_mask, target_cpu_mask, tmp;
392 for_each_possible_cpu(i) {
397 package_index = CPU_TO_PACKAGEINDEX(i);
398 for (j = 0; j < NR_IRQS; j++) {
399 unsigned long value_now, delta;
400 /* Is this an active IRQ? */
401 if (!irq_desc[j].action)
403 if ( package_index == i )
404 IRQ_DELTA(package_index,j) = 0;
405 /* Determine the total count per processor per IRQ */
406 value_now = (unsigned long) kstat_cpu(i).irqs[j];
408 /* Determine the activity per processor per IRQ */
409 delta = value_now - LAST_CPU_IRQ(i,j);
411 /* Update last_cpu_irq[][] for the next time */
412 LAST_CPU_IRQ(i,j) = value_now;
414 /* Ignore IRQs whose rate is less than the clock */
415 if (delta < useful_load_threshold)
417 /* update the load for the processor or package total */
418 IRQ_DELTA(package_index,j) += delta;
420 /* Keep track of the higher numbered sibling as well */
421 if (i != package_index)
424 * We have sibling A and sibling B in the package
426 * cpu_irq[A] = load for cpu A + load for cpu B
427 * cpu_irq[B] = load for cpu B
429 CPU_IRQ(package_index) += delta;
432 /* Find the least loaded processor package */
433 for_each_online_cpu(i) {
434 if (i != CPU_TO_PACKAGEINDEX(i))
436 if (min_cpu_irq > CPU_IRQ(i)) {
437 min_cpu_irq = CPU_IRQ(i);
441 max_cpu_irq = ULONG_MAX;
444 /* Look for heaviest loaded processor.
445 * We may come back to get the next heaviest loaded processor.
446 * Skip processors with trivial loads.
450 for_each_online_cpu(i) {
451 if (i != CPU_TO_PACKAGEINDEX(i))
453 if (max_cpu_irq <= CPU_IRQ(i))
455 if (tmp_cpu_irq < CPU_IRQ(i)) {
456 tmp_cpu_irq = CPU_IRQ(i);
461 if (tmp_loaded == -1) {
462 /* In the case of small number of heavy interrupt sources,
463 * loading some of the cpus too much. We use Ingo's original
464 * approach to rotate them around.
466 if (!first_attempt && imbalance >= useful_load_threshold) {
467 rotate_irqs_among_cpus(useful_load_threshold);
470 goto not_worth_the_effort;
473 first_attempt = 0; /* heaviest search */
474 max_cpu_irq = tmp_cpu_irq; /* load */
475 max_loaded = tmp_loaded; /* processor */
476 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
478 Dprintk("max_loaded cpu = %d\n", max_loaded);
479 Dprintk("min_loaded cpu = %d\n", min_loaded);
480 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
481 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
482 Dprintk("load imbalance = %lu\n", imbalance);
484 /* if imbalance is less than approx 10% of max load, then
485 * observe diminishing returns action. - quit
487 if (imbalance < (max_cpu_irq >> 3)) {
488 Dprintk("Imbalance too trivial\n");
489 goto not_worth_the_effort;
493 /* if we select an IRQ to move that can't go where we want, then
494 * see if there is another one to try.
498 for (j = 0; j < NR_IRQS; j++) {
499 /* Is this an active IRQ? */
500 if (!irq_desc[j].action)
502 if (imbalance <= IRQ_DELTA(max_loaded,j))
504 /* Try to find the IRQ that is closest to the imbalance
505 * without going over.
507 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
508 move_this_load = IRQ_DELTA(max_loaded,j);
512 if (selected_irq == -1) {
516 imbalance = move_this_load;
518 /* For physical_balance case, we accumlated both load
519 * values in the one of the siblings cpu_irq[],
520 * to use the same code for physical and logical processors
521 * as much as possible.
523 * NOTE: the cpu_irq[] array holds the sum of the load for
524 * sibling A and sibling B in the slot for the lowest numbered
525 * sibling (A), _AND_ the load for sibling B in the slot for
526 * the higher numbered sibling.
528 * We seek the least loaded sibling by making the comparison
531 load = CPU_IRQ(min_loaded) >> 1;
532 for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
533 if (load > CPU_IRQ(j)) {
534 /* This won't change cpu_sibling_map[min_loaded] */
540 cpus_and(allowed_mask,
542 balance_irq_affinity[selected_irq]);
543 target_cpu_mask = cpumask_of_cpu(min_loaded);
544 cpus_and(tmp, target_cpu_mask, allowed_mask);
546 if (!cpus_empty(tmp)) {
548 Dprintk("irq = %d moved to cpu = %d\n",
549 selected_irq, min_loaded);
550 /* mark for change destination */
551 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
553 /* Since we made a change, come back sooner to
554 * check for more variation.
556 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
557 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
562 not_worth_the_effort:
564 * if we did not find an IRQ to move, then adjust the time interval
567 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
568 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
569 Dprintk("IRQ worth rotating not found\n");
573 static int balanced_irq(void *unused)
576 unsigned long prev_balance_time = jiffies;
577 long time_remaining = balanced_irq_interval;
581 /* push everything to CPU 0 to give us a starting point. */
582 for (i = 0 ; i < NR_IRQS ; i++) {
583 pending_irq_cpumask[i] = cpumask_of_cpu(0);
584 set_pending_irq(i, cpumask_of_cpu(0));
588 time_remaining = schedule_timeout_interruptible(time_remaining);
590 if (time_after(jiffies,
591 prev_balance_time+balanced_irq_interval)) {
594 prev_balance_time = jiffies;
595 time_remaining = balanced_irq_interval;
602 static int __init balanced_irq_init(void)
605 struct cpuinfo_x86 *c;
608 cpus_shift_right(tmp, cpu_online_map, 2);
610 /* When not overwritten by the command line ask subarchitecture. */
611 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
612 irqbalance_disabled = NO_BALANCE_IRQ;
613 if (irqbalance_disabled)
616 /* disable irqbalance completely if there is only one processor online */
617 if (num_online_cpus() < 2) {
618 irqbalance_disabled = 1;
622 * Enable physical balance only if more than 1 physical processor
625 if (smp_num_siblings > 1 && !cpus_empty(tmp))
626 physical_balance = 1;
628 for_each_online_cpu(i) {
629 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
630 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
631 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
632 printk(KERN_ERR "balanced_irq_init: out of memory");
635 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
636 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
639 printk(KERN_INFO "Starting balanced_irq\n");
640 if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
643 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
645 for_each_possible_cpu(i) {
646 kfree(irq_cpu_data[i].irq_delta);
647 irq_cpu_data[i].irq_delta = NULL;
648 kfree(irq_cpu_data[i].last_irq);
649 irq_cpu_data[i].last_irq = NULL;
654 int __init irqbalance_disable(char *str)
656 irqbalance_disabled = 1;
660 __setup("noirqbalance", irqbalance_disable);
662 late_initcall(balanced_irq_init);
663 #endif /* CONFIG_IRQBALANCE */
664 #endif /* CONFIG_SMP */
667 void fastcall send_IPI_self(int vector)
674 apic_wait_icr_idle();
675 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
677 * Send the IPI. The write to APIC_ICR fires this off.
679 apic_write_around(APIC_ICR, cfg);
681 #endif /* !CONFIG_SMP */
685 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
686 * specific CPU-side IRQs.
690 static int pirq_entries [MAX_PIRQS];
691 static int pirqs_enabled;
692 int skip_ioapic_setup;
694 static int __init ioapic_setup(char *str)
696 skip_ioapic_setup = 1;
700 __setup("noapic", ioapic_setup);
702 static int __init ioapic_pirq_setup(char *str)
705 int ints[MAX_PIRQS+1];
707 get_options(str, ARRAY_SIZE(ints), ints);
709 for (i = 0; i < MAX_PIRQS; i++)
710 pirq_entries[i] = -1;
713 apic_printk(APIC_VERBOSE, KERN_INFO
714 "PIRQ redirection, working around broken MP-BIOS.\n");
716 if (ints[0] < MAX_PIRQS)
719 for (i = 0; i < max; i++) {
720 apic_printk(APIC_VERBOSE, KERN_DEBUG
721 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
723 * PIRQs are mapped upside down, usually.
725 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
730 __setup("pirq=", ioapic_pirq_setup);
733 * Find the IRQ entry number of a certain pin.
735 static int find_irq_entry(int apic, int pin, int type)
739 for (i = 0; i < mp_irq_entries; i++)
740 if (mp_irqs[i].mpc_irqtype == type &&
741 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
742 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
743 mp_irqs[i].mpc_dstirq == pin)
750 * Find the pin to which IRQ[irq] (ISA) is connected
752 static int __init find_isa_irq_pin(int irq, int type)
756 for (i = 0; i < mp_irq_entries; i++) {
757 int lbus = mp_irqs[i].mpc_srcbus;
759 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
760 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
761 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
762 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
764 (mp_irqs[i].mpc_irqtype == type) &&
765 (mp_irqs[i].mpc_srcbusirq == irq))
767 return mp_irqs[i].mpc_dstirq;
772 static int __init find_isa_irq_apic(int irq, int type)
776 for (i = 0; i < mp_irq_entries; i++) {
777 int lbus = mp_irqs[i].mpc_srcbus;
779 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
780 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
781 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
782 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
784 (mp_irqs[i].mpc_irqtype == type) &&
785 (mp_irqs[i].mpc_srcbusirq == irq))
788 if (i < mp_irq_entries) {
790 for(apic = 0; apic < nr_ioapics; apic++) {
791 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
800 * Find a specific PCI IRQ entry.
801 * Not an __init, possibly needed by modules
803 static int pin_2_irq(int idx, int apic, int pin);
805 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
807 int apic, i, best_guess = -1;
809 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
810 "slot:%d, pin:%d.\n", bus, slot, pin);
811 if (mp_bus_id_to_pci_bus[bus] == -1) {
812 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
815 for (i = 0; i < mp_irq_entries; i++) {
816 int lbus = mp_irqs[i].mpc_srcbus;
818 for (apic = 0; apic < nr_ioapics; apic++)
819 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
820 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
823 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
824 !mp_irqs[i].mpc_irqtype &&
826 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
827 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
829 if (!(apic || IO_APIC_IRQ(irq)))
832 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
835 * Use the first all-but-pin matching entry as a
836 * best-guess fuzzy result for broken mptables.
844 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
847 * This function currently is only a helper for the i386 smp boot process where
848 * we need to reprogram the ioredtbls to cater for the cpus which have come online
849 * so mask in all cases should simply be TARGET_CPUS
852 void __init setup_ioapic_dest(void)
854 int pin, ioapic, irq, irq_entry;
856 if (skip_ioapic_setup == 1)
859 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
860 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
861 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
864 irq = pin_2_irq(irq_entry, ioapic, pin);
865 set_ioapic_affinity_irq(irq, TARGET_CPUS);
873 * EISA Edge/Level control register, ELCR
875 static int EISA_ELCR(unsigned int irq)
878 unsigned int port = 0x4d0 + (irq >> 3);
879 return (inb(port) >> (irq & 7)) & 1;
881 apic_printk(APIC_VERBOSE, KERN_INFO
882 "Broken MPtable reports ISA irq %d\n", irq);
886 /* EISA interrupts are always polarity zero and can be edge or level
887 * trigger depending on the ELCR value. If an interrupt is listed as
888 * EISA conforming in the MP table, that means its trigger type must
889 * be read in from the ELCR */
891 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
892 #define default_EISA_polarity(idx) (0)
894 /* ISA interrupts are always polarity zero edge triggered,
895 * when listed as conforming in the MP table. */
897 #define default_ISA_trigger(idx) (0)
898 #define default_ISA_polarity(idx) (0)
900 /* PCI interrupts are always polarity one level triggered,
901 * when listed as conforming in the MP table. */
903 #define default_PCI_trigger(idx) (1)
904 #define default_PCI_polarity(idx) (1)
906 /* MCA interrupts are always polarity zero level triggered,
907 * when listed as conforming in the MP table. */
909 #define default_MCA_trigger(idx) (1)
910 #define default_MCA_polarity(idx) (0)
912 /* NEC98 interrupts are always polarity zero edge triggered,
913 * when listed as conforming in the MP table. */
915 #define default_NEC98_trigger(idx) (0)
916 #define default_NEC98_polarity(idx) (0)
918 static int __init MPBIOS_polarity(int idx)
920 int bus = mp_irqs[idx].mpc_srcbus;
924 * Determine IRQ line polarity (high active or low active):
926 switch (mp_irqs[idx].mpc_irqflag & 3)
928 case 0: /* conforms, ie. bus-type dependent polarity */
930 switch (mp_bus_id_to_type[bus])
932 case MP_BUS_ISA: /* ISA pin */
934 polarity = default_ISA_polarity(idx);
937 case MP_BUS_EISA: /* EISA pin */
939 polarity = default_EISA_polarity(idx);
942 case MP_BUS_PCI: /* PCI pin */
944 polarity = default_PCI_polarity(idx);
947 case MP_BUS_MCA: /* MCA pin */
949 polarity = default_MCA_polarity(idx);
952 case MP_BUS_NEC98: /* NEC 98 pin */
954 polarity = default_NEC98_polarity(idx);
959 printk(KERN_WARNING "broken BIOS!!\n");
966 case 1: /* high active */
971 case 2: /* reserved */
973 printk(KERN_WARNING "broken BIOS!!\n");
977 case 3: /* low active */
982 default: /* invalid */
984 printk(KERN_WARNING "broken BIOS!!\n");
992 static int MPBIOS_trigger(int idx)
994 int bus = mp_irqs[idx].mpc_srcbus;
998 * Determine IRQ trigger mode (edge or level sensitive):
1000 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1002 case 0: /* conforms, ie. bus-type dependent */
1004 switch (mp_bus_id_to_type[bus])
1006 case MP_BUS_ISA: /* ISA pin */
1008 trigger = default_ISA_trigger(idx);
1011 case MP_BUS_EISA: /* EISA pin */
1013 trigger = default_EISA_trigger(idx);
1016 case MP_BUS_PCI: /* PCI pin */
1018 trigger = default_PCI_trigger(idx);
1021 case MP_BUS_MCA: /* MCA pin */
1023 trigger = default_MCA_trigger(idx);
1026 case MP_BUS_NEC98: /* NEC 98 pin */
1028 trigger = default_NEC98_trigger(idx);
1033 printk(KERN_WARNING "broken BIOS!!\n");
1045 case 2: /* reserved */
1047 printk(KERN_WARNING "broken BIOS!!\n");
1056 default: /* invalid */
1058 printk(KERN_WARNING "broken BIOS!!\n");
1066 static inline int irq_polarity(int idx)
1068 return MPBIOS_polarity(idx);
1071 static inline int irq_trigger(int idx)
1073 return MPBIOS_trigger(idx);
1076 static int pin_2_irq(int idx, int apic, int pin)
1079 int bus = mp_irqs[idx].mpc_srcbus;
1082 * Debugging check, we are in big trouble if this message pops up!
1084 if (mp_irqs[idx].mpc_dstirq != pin)
1085 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1087 switch (mp_bus_id_to_type[bus])
1089 case MP_BUS_ISA: /* ISA pin */
1094 irq = mp_irqs[idx].mpc_srcbusirq;
1097 case MP_BUS_PCI: /* PCI pin */
1100 * PCI IRQs are mapped in order
1104 irq += nr_ioapic_registers[i++];
1108 * For MPS mode, so far only needed by ES7000 platform
1110 if (ioapic_renumber_irq)
1111 irq = ioapic_renumber_irq(apic, irq);
1117 printk(KERN_ERR "unknown bus type %d.\n",bus);
1124 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1126 if ((pin >= 16) && (pin <= 23)) {
1127 if (pirq_entries[pin-16] != -1) {
1128 if (!pirq_entries[pin-16]) {
1129 apic_printk(APIC_VERBOSE, KERN_DEBUG
1130 "disabling PIRQ%d\n", pin-16);
1132 irq = pirq_entries[pin-16];
1133 apic_printk(APIC_VERBOSE, KERN_DEBUG
1134 "using PIRQ%d -> IRQ %d\n",
1142 static inline int IO_APIC_irq_trigger(int irq)
1146 for (apic = 0; apic < nr_ioapics; apic++) {
1147 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1148 idx = find_irq_entry(apic,pin,mp_INT);
1149 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1150 return irq_trigger(idx);
1154 * nonexistent IRQs are edge default
1159 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1160 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1162 int assign_irq_vector(int irq)
1164 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1167 BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
1169 spin_lock(&vector_lock);
1171 if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
1172 spin_unlock(&vector_lock);
1173 return IO_APIC_VECTOR(irq);
1176 current_vector += 8;
1177 if (current_vector == SYSCALL_VECTOR)
1180 if (current_vector >= FIRST_SYSTEM_VECTOR) {
1183 spin_unlock(&vector_lock);
1186 current_vector = FIRST_DEVICE_VECTOR + offset;
1189 vector = current_vector;
1190 vector_irq[vector] = irq;
1191 if (irq != AUTO_ASSIGN)
1192 IO_APIC_VECTOR(irq) = vector;
1194 spin_unlock(&vector_lock);
1199 static struct hw_interrupt_type ioapic_level_type;
1200 static struct hw_interrupt_type ioapic_edge_type;
1202 #define IOAPIC_AUTO -1
1203 #define IOAPIC_EDGE 0
1204 #define IOAPIC_LEVEL 1
1206 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1208 unsigned idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
1210 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1211 trigger == IOAPIC_LEVEL)
1212 irq_desc[idx].handler = &ioapic_level_type;
1214 irq_desc[idx].handler = &ioapic_edge_type;
1215 set_intr_gate(vector, interrupt[idx]);
1218 static void __init setup_IO_APIC_irqs(void)
1220 struct IO_APIC_route_entry entry;
1221 int apic, pin, idx, irq, first_notcon = 1, vector;
1222 unsigned long flags;
1224 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1226 for (apic = 0; apic < nr_ioapics; apic++) {
1227 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1230 * add it to the IO-APIC irq-routing table:
1232 memset(&entry,0,sizeof(entry));
1234 entry.delivery_mode = INT_DELIVERY_MODE;
1235 entry.dest_mode = INT_DEST_MODE;
1236 entry.mask = 0; /* enable IRQ */
1237 entry.dest.logical.logical_dest =
1238 cpu_mask_to_apicid(TARGET_CPUS);
1240 idx = find_irq_entry(apic,pin,mp_INT);
1243 apic_printk(APIC_VERBOSE, KERN_DEBUG
1244 " IO-APIC (apicid-pin) %d-%d",
1245 mp_ioapics[apic].mpc_apicid,
1249 apic_printk(APIC_VERBOSE, ", %d-%d",
1250 mp_ioapics[apic].mpc_apicid, pin);
1254 entry.trigger = irq_trigger(idx);
1255 entry.polarity = irq_polarity(idx);
1257 if (irq_trigger(idx)) {
1262 irq = pin_2_irq(idx, apic, pin);
1264 * skip adding the timer int on secondary nodes, which causes
1265 * a small but painful rift in the time-space continuum
1267 if (multi_timer_check(apic, irq))
1270 add_pin_to_irq(irq, apic, pin);
1272 if (!apic && !IO_APIC_IRQ(irq))
1275 if (IO_APIC_IRQ(irq)) {
1276 vector = assign_irq_vector(irq);
1277 entry.vector = vector;
1278 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1280 if (!apic && (irq < 16))
1281 disable_8259A_irq(irq);
1283 spin_lock_irqsave(&ioapic_lock, flags);
1284 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1285 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1286 set_native_irq_info(irq, TARGET_CPUS);
1287 spin_unlock_irqrestore(&ioapic_lock, flags);
1292 apic_printk(APIC_VERBOSE, " not connected.\n");
1296 * Set up the 8259A-master output pin:
1298 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1300 struct IO_APIC_route_entry entry;
1301 unsigned long flags;
1303 memset(&entry,0,sizeof(entry));
1305 disable_8259A_irq(0);
1308 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1311 * We use logical delivery to get the timer IRQ
1314 entry.dest_mode = INT_DEST_MODE;
1315 entry.mask = 0; /* unmask IRQ now */
1316 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1317 entry.delivery_mode = INT_DELIVERY_MODE;
1320 entry.vector = vector;
1323 * The timer IRQ doesn't have to know that behind the
1324 * scene we have a 8259A-master in AEOI mode ...
1326 irq_desc[0].handler = &ioapic_edge_type;
1329 * Add it to the IO-APIC irq-routing table:
1331 spin_lock_irqsave(&ioapic_lock, flags);
1332 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1333 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1334 spin_unlock_irqrestore(&ioapic_lock, flags);
1336 enable_8259A_irq(0);
1339 static inline void UNEXPECTED_IO_APIC(void)
1343 void __init print_IO_APIC(void)
1346 union IO_APIC_reg_00 reg_00;
1347 union IO_APIC_reg_01 reg_01;
1348 union IO_APIC_reg_02 reg_02;
1349 union IO_APIC_reg_03 reg_03;
1350 unsigned long flags;
1352 if (apic_verbosity == APIC_QUIET)
1355 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1356 for (i = 0; i < nr_ioapics; i++)
1357 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1358 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1361 * We are a bit conservative about what we expect. We have to
1362 * know about every hardware change ASAP.
1364 printk(KERN_INFO "testing the IO APIC.......................\n");
1366 for (apic = 0; apic < nr_ioapics; apic++) {
1368 spin_lock_irqsave(&ioapic_lock, flags);
1369 reg_00.raw = io_apic_read(apic, 0);
1370 reg_01.raw = io_apic_read(apic, 1);
1371 if (reg_01.bits.version >= 0x10)
1372 reg_02.raw = io_apic_read(apic, 2);
1373 if (reg_01.bits.version >= 0x20)
1374 reg_03.raw = io_apic_read(apic, 3);
1375 spin_unlock_irqrestore(&ioapic_lock, flags);
1377 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1378 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1379 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1380 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1381 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1382 if (reg_00.bits.ID >= get_physical_broadcast())
1383 UNEXPECTED_IO_APIC();
1384 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1385 UNEXPECTED_IO_APIC();
1387 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1388 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1389 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1390 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1391 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1392 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1393 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1394 (reg_01.bits.entries != 0x2E) &&
1395 (reg_01.bits.entries != 0x3F)
1397 UNEXPECTED_IO_APIC();
1399 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1400 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1401 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1402 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1403 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1404 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1405 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
1407 UNEXPECTED_IO_APIC();
1408 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1409 UNEXPECTED_IO_APIC();
1412 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1413 * but the value of reg_02 is read as the previous read register
1414 * value, so ignore it if reg_02 == reg_01.
1416 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1417 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1418 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1419 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1420 UNEXPECTED_IO_APIC();
1424 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1425 * or reg_03, but the value of reg_0[23] is read as the previous read
1426 * register value, so ignore it if reg_03 == reg_0[12].
1428 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1429 reg_03.raw != reg_01.raw) {
1430 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1431 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1432 if (reg_03.bits.__reserved_1)
1433 UNEXPECTED_IO_APIC();
1436 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1438 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1439 " Stat Dest Deli Vect: \n");
1441 for (i = 0; i <= reg_01.bits.entries; i++) {
1442 struct IO_APIC_route_entry entry;
1444 spin_lock_irqsave(&ioapic_lock, flags);
1445 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1446 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1447 spin_unlock_irqrestore(&ioapic_lock, flags);
1449 printk(KERN_DEBUG " %02x %03X %02X ",
1451 entry.dest.logical.logical_dest,
1452 entry.dest.physical.physical_dest
1455 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1460 entry.delivery_status,
1462 entry.delivery_mode,
1467 if (use_pci_vector())
1468 printk(KERN_INFO "Using vector-based indexing\n");
1469 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1470 for (i = 0; i < NR_IRQS; i++) {
1471 struct irq_pin_list *entry = irq_2_pin + i;
1474 if (use_pci_vector() && !platform_legacy_irq(i))
1475 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1477 printk(KERN_DEBUG "IRQ%d ", i);
1479 printk("-> %d:%d", entry->apic, entry->pin);
1482 entry = irq_2_pin + entry->next;
1487 printk(KERN_INFO ".................................... done.\n");
1494 static void print_APIC_bitfield (int base)
1499 if (apic_verbosity == APIC_QUIET)
1502 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1503 for (i = 0; i < 8; i++) {
1504 v = apic_read(base + i*0x10);
1505 for (j = 0; j < 32; j++) {
1515 void /*__init*/ print_local_APIC(void * dummy)
1517 unsigned int v, ver, maxlvt;
1519 if (apic_verbosity == APIC_QUIET)
1522 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1523 smp_processor_id(), hard_smp_processor_id());
1524 v = apic_read(APIC_ID);
1525 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1526 v = apic_read(APIC_LVR);
1527 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1528 ver = GET_APIC_VERSION(v);
1529 maxlvt = get_maxlvt();
1531 v = apic_read(APIC_TASKPRI);
1532 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1534 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1535 v = apic_read(APIC_ARBPRI);
1536 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1537 v & APIC_ARBPRI_MASK);
1538 v = apic_read(APIC_PROCPRI);
1539 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1542 v = apic_read(APIC_EOI);
1543 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1544 v = apic_read(APIC_RRR);
1545 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1546 v = apic_read(APIC_LDR);
1547 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1548 v = apic_read(APIC_DFR);
1549 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1550 v = apic_read(APIC_SPIV);
1551 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1553 printk(KERN_DEBUG "... APIC ISR field:\n");
1554 print_APIC_bitfield(APIC_ISR);
1555 printk(KERN_DEBUG "... APIC TMR field:\n");
1556 print_APIC_bitfield(APIC_TMR);
1557 printk(KERN_DEBUG "... APIC IRR field:\n");
1558 print_APIC_bitfield(APIC_IRR);
1560 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1561 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1562 apic_write(APIC_ESR, 0);
1563 v = apic_read(APIC_ESR);
1564 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1567 v = apic_read(APIC_ICR);
1568 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1569 v = apic_read(APIC_ICR2);
1570 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1572 v = apic_read(APIC_LVTT);
1573 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1575 if (maxlvt > 3) { /* PC is LVT#4. */
1576 v = apic_read(APIC_LVTPC);
1577 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1579 v = apic_read(APIC_LVT0);
1580 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1581 v = apic_read(APIC_LVT1);
1582 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1584 if (maxlvt > 2) { /* ERR is LVT#3. */
1585 v = apic_read(APIC_LVTERR);
1586 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1589 v = apic_read(APIC_TMICT);
1590 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1591 v = apic_read(APIC_TMCCT);
1592 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1593 v = apic_read(APIC_TDCR);
1594 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1598 void print_all_local_APICs (void)
1600 on_each_cpu(print_local_APIC, NULL, 1, 1);
1603 void /*__init*/ print_PIC(void)
1606 unsigned long flags;
1608 if (apic_verbosity == APIC_QUIET)
1611 printk(KERN_DEBUG "\nprinting PIC contents\n");
1613 spin_lock_irqsave(&i8259A_lock, flags);
1615 v = inb(0xa1) << 8 | inb(0x21);
1616 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1618 v = inb(0xa0) << 8 | inb(0x20);
1619 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1623 v = inb(0xa0) << 8 | inb(0x20);
1627 spin_unlock_irqrestore(&i8259A_lock, flags);
1629 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1631 v = inb(0x4d1) << 8 | inb(0x4d0);
1632 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1637 static void __init enable_IO_APIC(void)
1639 union IO_APIC_reg_01 reg_01;
1640 int i8259_apic, i8259_pin;
1642 unsigned long flags;
1644 for (i = 0; i < PIN_MAP_SIZE; i++) {
1645 irq_2_pin[i].pin = -1;
1646 irq_2_pin[i].next = 0;
1649 for (i = 0; i < MAX_PIRQS; i++)
1650 pirq_entries[i] = -1;
1653 * The number of IO-APIC IRQ registers (== #pins):
1655 for (apic = 0; apic < nr_ioapics; apic++) {
1656 spin_lock_irqsave(&ioapic_lock, flags);
1657 reg_01.raw = io_apic_read(apic, 1);
1658 spin_unlock_irqrestore(&ioapic_lock, flags);
1659 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1661 for(apic = 0; apic < nr_ioapics; apic++) {
1663 /* See if any of the pins is in ExtINT mode */
1664 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1665 struct IO_APIC_route_entry entry;
1666 spin_lock_irqsave(&ioapic_lock, flags);
1667 *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1668 *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1669 spin_unlock_irqrestore(&ioapic_lock, flags);
1672 /* If the interrupt line is enabled and in ExtInt mode
1673 * I have found the pin where the i8259 is connected.
1675 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1676 ioapic_i8259.apic = apic;
1677 ioapic_i8259.pin = pin;
1683 /* Look to see what if the MP table has reported the ExtINT */
1684 /* If we could not find the appropriate pin by looking at the ioapic
1685 * the i8259 probably is not connected the ioapic but give the
1686 * mptable a chance anyway.
1688 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1689 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1690 /* Trust the MP table if nothing is setup in the hardware */
1691 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1692 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1693 ioapic_i8259.pin = i8259_pin;
1694 ioapic_i8259.apic = i8259_apic;
1696 /* Complain if the MP table and the hardware disagree */
1697 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1698 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1700 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1704 * Do not trust the IO-APIC being empty at bootup
1710 * Not an __init, needed by the reboot code
1712 void disable_IO_APIC(void)
1715 * Clear the IO-APIC before rebooting:
1720 * If the i8259 is routed through an IOAPIC
1721 * Put that IOAPIC in virtual wire mode
1722 * so legacy interrupts can be delivered.
1724 if (ioapic_i8259.pin != -1) {
1725 struct IO_APIC_route_entry entry;
1726 unsigned long flags;
1728 memset(&entry, 0, sizeof(entry));
1729 entry.mask = 0; /* Enabled */
1730 entry.trigger = 0; /* Edge */
1732 entry.polarity = 0; /* High */
1733 entry.delivery_status = 0;
1734 entry.dest_mode = 0; /* Physical */
1735 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1737 entry.dest.physical.physical_dest =
1738 GET_APIC_ID(apic_read(APIC_ID));
1741 * Add it to the IO-APIC irq-routing table:
1743 spin_lock_irqsave(&ioapic_lock, flags);
1744 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1745 *(((int *)&entry)+1));
1746 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1747 *(((int *)&entry)+0));
1748 spin_unlock_irqrestore(&ioapic_lock, flags);
1750 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1754 * function to set the IO-APIC physical IDs based on the
1755 * values stored in the MPC table.
1757 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1760 #ifndef CONFIG_X86_NUMAQ
1761 static void __init setup_ioapic_ids_from_mpc(void)
1763 union IO_APIC_reg_00 reg_00;
1764 physid_mask_t phys_id_present_map;
1767 unsigned char old_id;
1768 unsigned long flags;
1771 * Don't check I/O APIC IDs for xAPIC systems. They have
1772 * no meaning without the serial APIC bus.
1774 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1775 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1778 * This is broken; anything with a real cpu count has to
1779 * circumvent this idiocy regardless.
1781 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1784 * Set the IOAPIC ID to the value stored in the MPC table.
1786 for (apic = 0; apic < nr_ioapics; apic++) {
1788 /* Read the register 0 value */
1789 spin_lock_irqsave(&ioapic_lock, flags);
1790 reg_00.raw = io_apic_read(apic, 0);
1791 spin_unlock_irqrestore(&ioapic_lock, flags);
1793 old_id = mp_ioapics[apic].mpc_apicid;
1795 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1796 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1797 apic, mp_ioapics[apic].mpc_apicid);
1798 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1800 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1804 * Sanity check, is the ID really free? Every APIC in a
1805 * system must have a unique ID or we get lots of nice
1806 * 'stuck on smp_invalidate_needed IPI wait' messages.
1808 if (check_apicid_used(phys_id_present_map,
1809 mp_ioapics[apic].mpc_apicid)) {
1810 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1811 apic, mp_ioapics[apic].mpc_apicid);
1812 for (i = 0; i < get_physical_broadcast(); i++)
1813 if (!physid_isset(i, phys_id_present_map))
1815 if (i >= get_physical_broadcast())
1816 panic("Max APIC ID exceeded!\n");
1817 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1819 physid_set(i, phys_id_present_map);
1820 mp_ioapics[apic].mpc_apicid = i;
1823 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1824 apic_printk(APIC_VERBOSE, "Setting %d in the "
1825 "phys_id_present_map\n",
1826 mp_ioapics[apic].mpc_apicid);
1827 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1832 * We need to adjust the IRQ routing table
1833 * if the ID changed.
1835 if (old_id != mp_ioapics[apic].mpc_apicid)
1836 for (i = 0; i < mp_irq_entries; i++)
1837 if (mp_irqs[i].mpc_dstapic == old_id)
1838 mp_irqs[i].mpc_dstapic
1839 = mp_ioapics[apic].mpc_apicid;
1842 * Read the right value from the MPC table and
1843 * write it into the ID register.
1845 apic_printk(APIC_VERBOSE, KERN_INFO
1846 "...changing IO-APIC physical APIC ID to %d ...",
1847 mp_ioapics[apic].mpc_apicid);
1849 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1850 spin_lock_irqsave(&ioapic_lock, flags);
1851 io_apic_write(apic, 0, reg_00.raw);
1852 spin_unlock_irqrestore(&ioapic_lock, flags);
1857 spin_lock_irqsave(&ioapic_lock, flags);
1858 reg_00.raw = io_apic_read(apic, 0);
1859 spin_unlock_irqrestore(&ioapic_lock, flags);
1860 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1861 printk("could not set ID!\n");
1863 apic_printk(APIC_VERBOSE, " ok.\n");
1867 static void __init setup_ioapic_ids_from_mpc(void) { }
1871 * There is a nasty bug in some older SMP boards, their mptable lies
1872 * about the timer IRQ. We do the following to work around the situation:
1874 * - timer IRQ defaults to IO-APIC IRQ
1875 * - if this function detects that timer IRQs are defunct, then we fall
1876 * back to ISA timer IRQs
1878 static int __init timer_irq_works(void)
1880 unsigned long t1 = jiffies;
1883 /* Let ten ticks pass... */
1884 mdelay((10 * 1000) / HZ);
1887 * Expect a few ticks at least, to be sure some possible
1888 * glue logic does not lock up after one or two first
1889 * ticks in a non-ExtINT mode. Also the local APIC
1890 * might have cached one ExtINT interrupt. Finally, at
1891 * least one tick may be lost due to delays.
1893 if (jiffies - t1 > 4)
1900 * In the SMP+IOAPIC case it might happen that there are an unspecified
1901 * number of pending IRQ events unhandled. These cases are very rare,
1902 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1903 * better to do it this way as thus we do not have to be aware of
1904 * 'pending' interrupts in the IRQ path, except at this point.
1907 * Edge triggered needs to resend any interrupt
1908 * that was delayed but this is now handled in the device
1913 * Starting up a edge-triggered IO-APIC interrupt is
1914 * nasty - we need to make sure that we get the edge.
1915 * If it is already asserted for some reason, we need
1916 * return 1 to indicate that is was pending.
1918 * This is not complete - we should be able to fake
1919 * an edge even if it isn't on the 8259A...
1921 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1923 int was_pending = 0;
1924 unsigned long flags;
1926 spin_lock_irqsave(&ioapic_lock, flags);
1928 disable_8259A_irq(irq);
1929 if (i8259A_irq_pending(irq))
1932 __unmask_IO_APIC_irq(irq);
1933 spin_unlock_irqrestore(&ioapic_lock, flags);
1939 * Once we have recorded IRQ_PENDING already, we can mask the
1940 * interrupt for real. This prevents IRQ storms from unhandled
1943 static void ack_edge_ioapic_irq(unsigned int irq)
1946 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1947 == (IRQ_PENDING | IRQ_DISABLED))
1948 mask_IO_APIC_irq(irq);
1953 * Level triggered interrupts can just be masked,
1954 * and shutting down and starting up the interrupt
1955 * is the same as enabling and disabling them -- except
1956 * with a startup need to return a "was pending" value.
1958 * Level triggered interrupts are special because we
1959 * do not touch any IO-APIC register while handling
1960 * them. We ack the APIC in the end-IRQ handler, not
1961 * in the start-IRQ-handler. Protection against reentrance
1962 * from the same interrupt is still provided, both by the
1963 * generic IRQ layer and by the fact that an unacked local
1964 * APIC does not accept IRQs.
1966 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1968 unmask_IO_APIC_irq(irq);
1970 return 0; /* don't check for pending */
1973 static void end_level_ioapic_irq (unsigned int irq)
1980 * It appears there is an erratum which affects at least version 0x11
1981 * of I/O APIC (that's the 82093AA and cores integrated into various
1982 * chipsets). Under certain conditions a level-triggered interrupt is
1983 * erroneously delivered as edge-triggered one but the respective IRR
1984 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1985 * message but it will never arrive and further interrupts are blocked
1986 * from the source. The exact reason is so far unknown, but the
1987 * phenomenon was observed when two consecutive interrupt requests
1988 * from a given source get delivered to the same CPU and the source is
1989 * temporarily disabled in between.
1991 * A workaround is to simulate an EOI message manually. We achieve it
1992 * by setting the trigger mode to edge and then to level when the edge
1993 * trigger mode gets detected in the TMR of a local APIC for a
1994 * level-triggered interrupt. We mask the source for the time of the
1995 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1996 * The idea is from Manfred Spraul. --macro
1998 i = IO_APIC_VECTOR(irq);
2000 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2004 if (!(v & (1 << (i & 0x1f)))) {
2005 atomic_inc(&irq_mis_count);
2006 spin_lock(&ioapic_lock);
2007 __mask_and_edge_IO_APIC_irq(irq);
2008 __unmask_and_level_IO_APIC_irq(irq);
2009 spin_unlock(&ioapic_lock);
2013 #ifdef CONFIG_PCI_MSI
2014 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
2016 int irq = vector_to_irq(vector);
2018 return startup_edge_ioapic_irq(irq);
2021 static void ack_edge_ioapic_vector(unsigned int vector)
2023 int irq = vector_to_irq(vector);
2025 move_native_irq(vector);
2026 ack_edge_ioapic_irq(irq);
2029 static unsigned int startup_level_ioapic_vector (unsigned int vector)
2031 int irq = vector_to_irq(vector);
2033 return startup_level_ioapic_irq (irq);
2036 static void end_level_ioapic_vector (unsigned int vector)
2038 int irq = vector_to_irq(vector);
2040 move_native_irq(vector);
2041 end_level_ioapic_irq(irq);
2044 static void mask_IO_APIC_vector (unsigned int vector)
2046 int irq = vector_to_irq(vector);
2048 mask_IO_APIC_irq(irq);
2051 static void unmask_IO_APIC_vector (unsigned int vector)
2053 int irq = vector_to_irq(vector);
2055 unmask_IO_APIC_irq(irq);
2059 static void set_ioapic_affinity_vector (unsigned int vector,
2062 int irq = vector_to_irq(vector);
2064 set_native_irq_info(vector, cpu_mask);
2065 set_ioapic_affinity_irq(irq, cpu_mask);
2071 * Level and edge triggered IO-APIC interrupts need different handling,
2072 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2073 * handled with the level-triggered descriptor, but that one has slightly
2074 * more overhead. Level-triggered interrupts cannot be handled with the
2075 * edge-triggered handler, without risking IRQ storms and other ugly
2078 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
2079 .typename = "IO-APIC-edge",
2080 .startup = startup_edge_ioapic,
2081 .shutdown = shutdown_edge_ioapic,
2082 .enable = enable_edge_ioapic,
2083 .disable = disable_edge_ioapic,
2084 .ack = ack_edge_ioapic,
2085 .end = end_edge_ioapic,
2087 .set_affinity = set_ioapic_affinity,
2091 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
2092 .typename = "IO-APIC-level",
2093 .startup = startup_level_ioapic,
2094 .shutdown = shutdown_level_ioapic,
2095 .enable = enable_level_ioapic,
2096 .disable = disable_level_ioapic,
2097 .ack = mask_and_ack_level_ioapic,
2098 .end = end_level_ioapic,
2100 .set_affinity = set_ioapic_affinity,
2104 static inline void init_IO_APIC_traps(void)
2109 * NOTE! The local APIC isn't very good at handling
2110 * multiple interrupts at the same interrupt level.
2111 * As the interrupt level is determined by taking the
2112 * vector number and shifting that right by 4, we
2113 * want to spread these out a bit so that they don't
2114 * all fall in the same interrupt level.
2116 * Also, we've got to be careful not to trash gate
2117 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2119 for (irq = 0; irq < NR_IRQS ; irq++) {
2121 if (use_pci_vector()) {
2122 if (!platform_legacy_irq(tmp))
2123 if ((tmp = vector_to_irq(tmp)) == -1)
2126 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2128 * Hmm.. We don't have an entry for this,
2129 * so default to an old-fashioned 8259
2130 * interrupt if we can..
2133 make_8259A_irq(irq);
2135 /* Strange. Oh, well.. */
2136 irq_desc[irq].handler = &no_irq_type;
2141 static void enable_lapic_irq (unsigned int irq)
2145 v = apic_read(APIC_LVT0);
2146 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2149 static void disable_lapic_irq (unsigned int irq)
2153 v = apic_read(APIC_LVT0);
2154 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2157 static void ack_lapic_irq (unsigned int irq)
2162 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2164 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
2165 .typename = "local-APIC-edge",
2166 .startup = NULL, /* startup_irq() not used for IRQ0 */
2167 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
2168 .enable = enable_lapic_irq,
2169 .disable = disable_lapic_irq,
2170 .ack = ack_lapic_irq,
2171 .end = end_lapic_irq
2174 static void setup_nmi (void)
2177 * Dirty trick to enable the NMI watchdog ...
2178 * We put the 8259A master into AEOI mode and
2179 * unmask on all local APICs LVT0 as NMI.
2181 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2182 * is from Maciej W. Rozycki - so we do not have to EOI from
2183 * the NMI handler or the timer interrupt.
2185 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2187 on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2189 apic_printk(APIC_VERBOSE, " done.\n");
2193 * This looks a bit hackish but it's about the only one way of sending
2194 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2195 * not support the ExtINT mode, unfortunately. We need to send these
2196 * cycles as some i82489DX-based boards have glue logic that keeps the
2197 * 8259A interrupt line asserted until INTA. --macro
2199 static inline void unlock_ExtINT_logic(void)
2202 struct IO_APIC_route_entry entry0, entry1;
2203 unsigned char save_control, save_freq_select;
2204 unsigned long flags;
2206 pin = find_isa_irq_pin(8, mp_INT);
2207 apic = find_isa_irq_apic(8, mp_INT);
2211 spin_lock_irqsave(&ioapic_lock, flags);
2212 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
2213 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
2214 spin_unlock_irqrestore(&ioapic_lock, flags);
2215 clear_IO_APIC_pin(apic, pin);
2217 memset(&entry1, 0, sizeof(entry1));
2219 entry1.dest_mode = 0; /* physical delivery */
2220 entry1.mask = 0; /* unmask IRQ now */
2221 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2222 entry1.delivery_mode = dest_ExtINT;
2223 entry1.polarity = entry0.polarity;
2227 spin_lock_irqsave(&ioapic_lock, flags);
2228 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2229 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2230 spin_unlock_irqrestore(&ioapic_lock, flags);
2232 save_control = CMOS_READ(RTC_CONTROL);
2233 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2234 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2236 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2241 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2245 CMOS_WRITE(save_control, RTC_CONTROL);
2246 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2247 clear_IO_APIC_pin(apic, pin);
2249 spin_lock_irqsave(&ioapic_lock, flags);
2250 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2251 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2252 spin_unlock_irqrestore(&ioapic_lock, flags);
2255 int timer_uses_ioapic_pin_0;
2258 * This code may look a bit paranoid, but it's supposed to cooperate with
2259 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2260 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2261 * fanatically on his truly buggy board.
2263 static inline void check_timer(void)
2265 int apic1, pin1, apic2, pin2;
2269 * get/set the timer IRQ vector:
2271 disable_8259A_irq(0);
2272 vector = assign_irq_vector(0);
2273 set_intr_gate(vector, interrupt[0]);
2276 * Subtle, code in do_timer_interrupt() expects an AEOI
2277 * mode for the 8259A whenever interrupts are routed
2278 * through I/O APICs. Also IRQ0 has to be enabled in
2279 * the 8259A which implies the virtual wire has to be
2280 * disabled in the local APIC.
2282 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2285 if (timer_over_8254 > 0)
2286 enable_8259A_irq(0);
2288 pin1 = find_isa_irq_pin(0, mp_INT);
2289 apic1 = find_isa_irq_apic(0, mp_INT);
2290 pin2 = ioapic_i8259.pin;
2291 apic2 = ioapic_i8259.apic;
2294 timer_uses_ioapic_pin_0 = 1;
2296 printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2297 vector, apic1, pin1, apic2, pin2);
2301 * Ok, does IRQ0 through the IOAPIC work?
2303 unmask_IO_APIC_irq(0);
2304 if (timer_irq_works()) {
2305 if (nmi_watchdog == NMI_IO_APIC) {
2306 disable_8259A_irq(0);
2308 enable_8259A_irq(0);
2310 if (disable_timer_pin_1 > 0)
2311 clear_IO_APIC_pin(0, pin1);
2314 clear_IO_APIC_pin(apic1, pin1);
2315 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2319 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2321 printk("\n..... (found pin %d) ...", pin2);
2323 * legacy devices should be connected to IO APIC #0
2325 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2326 if (timer_irq_works()) {
2329 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2331 add_pin_to_irq(0, apic2, pin2);
2332 if (nmi_watchdog == NMI_IO_APIC) {
2338 * Cleanup, just in case ...
2340 clear_IO_APIC_pin(apic2, pin2);
2342 printk(" failed.\n");
2344 if (nmi_watchdog == NMI_IO_APIC) {
2345 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2349 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2351 disable_8259A_irq(0);
2352 irq_desc[0].handler = &lapic_irq_type;
2353 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2354 enable_8259A_irq(0);
2356 if (timer_irq_works()) {
2357 printk(" works.\n");
2360 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2361 printk(" failed.\n");
2363 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2368 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2370 unlock_ExtINT_logic();
2372 if (timer_irq_works()) {
2373 printk(" works.\n");
2376 printk(" failed :(.\n");
2377 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2378 "report. Then try booting with the 'noapic' option");
2383 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2384 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2385 * Linux doesn't really care, as it's not actually used
2386 * for any interrupt handling anyway.
2388 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2390 void __init setup_IO_APIC(void)
2395 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2397 io_apic_irqs = ~PIC_IRQS;
2399 printk("ENABLING IO-APIC IRQs\n");
2402 * Set up IO-APIC IRQ routing.
2405 setup_ioapic_ids_from_mpc();
2407 setup_IO_APIC_irqs();
2408 init_IO_APIC_traps();
2414 static int __init setup_disable_8254_timer(char *s)
2416 timer_over_8254 = -1;
2419 static int __init setup_enable_8254_timer(char *s)
2421 timer_over_8254 = 2;
2425 __setup("disable_8254_timer", setup_disable_8254_timer);
2426 __setup("enable_8254_timer", setup_enable_8254_timer);
2429 * Called after all the initialization is done. If we didnt find any
2430 * APIC bugs then we can allow the modify fast path
2433 static int __init io_apic_bug_finalize(void)
2435 if(sis_apic_bug == -1)
2440 late_initcall(io_apic_bug_finalize);
2442 struct sysfs_ioapic_data {
2443 struct sys_device dev;
2444 struct IO_APIC_route_entry entry[0];
2446 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2448 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2450 struct IO_APIC_route_entry *entry;
2451 struct sysfs_ioapic_data *data;
2452 unsigned long flags;
2455 data = container_of(dev, struct sysfs_ioapic_data, dev);
2456 entry = data->entry;
2457 spin_lock_irqsave(&ioapic_lock, flags);
2458 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2459 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2460 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2462 spin_unlock_irqrestore(&ioapic_lock, flags);
2467 static int ioapic_resume(struct sys_device *dev)
2469 struct IO_APIC_route_entry *entry;
2470 struct sysfs_ioapic_data *data;
2471 unsigned long flags;
2472 union IO_APIC_reg_00 reg_00;
2475 data = container_of(dev, struct sysfs_ioapic_data, dev);
2476 entry = data->entry;
2478 spin_lock_irqsave(&ioapic_lock, flags);
2479 reg_00.raw = io_apic_read(dev->id, 0);
2480 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2481 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2482 io_apic_write(dev->id, 0, reg_00.raw);
2484 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2485 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2486 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2488 spin_unlock_irqrestore(&ioapic_lock, flags);
2493 static struct sysdev_class ioapic_sysdev_class = {
2494 set_kset_name("ioapic"),
2495 .suspend = ioapic_suspend,
2496 .resume = ioapic_resume,
2499 static int __init ioapic_init_sysfs(void)
2501 struct sys_device * dev;
2502 int i, size, error = 0;
2504 error = sysdev_class_register(&ioapic_sysdev_class);
2508 for (i = 0; i < nr_ioapics; i++ ) {
2509 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2510 * sizeof(struct IO_APIC_route_entry);
2511 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2512 if (!mp_ioapic_data[i]) {
2513 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2516 memset(mp_ioapic_data[i], 0, size);
2517 dev = &mp_ioapic_data[i]->dev;
2519 dev->cls = &ioapic_sysdev_class;
2520 error = sysdev_register(dev);
2522 kfree(mp_ioapic_data[i]);
2523 mp_ioapic_data[i] = NULL;
2524 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2532 device_initcall(ioapic_init_sysfs);
2534 /* --------------------------------------------------------------------------
2535 ACPI-based IOAPIC Configuration
2536 -------------------------------------------------------------------------- */
2540 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2542 union IO_APIC_reg_00 reg_00;
2543 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2545 unsigned long flags;
2549 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2550 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2551 * supports up to 16 on one shared APIC bus.
2553 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2554 * advantage of new APIC bus architecture.
2557 if (physids_empty(apic_id_map))
2558 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2560 spin_lock_irqsave(&ioapic_lock, flags);
2561 reg_00.raw = io_apic_read(ioapic, 0);
2562 spin_unlock_irqrestore(&ioapic_lock, flags);
2564 if (apic_id >= get_physical_broadcast()) {
2565 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2566 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2567 apic_id = reg_00.bits.ID;
2571 * Every APIC in a system must have a unique ID or we get lots of nice
2572 * 'stuck on smp_invalidate_needed IPI wait' messages.
2574 if (check_apicid_used(apic_id_map, apic_id)) {
2576 for (i = 0; i < get_physical_broadcast(); i++) {
2577 if (!check_apicid_used(apic_id_map, i))
2581 if (i == get_physical_broadcast())
2582 panic("Max apic_id exceeded!\n");
2584 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2585 "trying %d\n", ioapic, apic_id, i);
2590 tmp = apicid_to_cpu_present(apic_id);
2591 physids_or(apic_id_map, apic_id_map, tmp);
2593 if (reg_00.bits.ID != apic_id) {
2594 reg_00.bits.ID = apic_id;
2596 spin_lock_irqsave(&ioapic_lock, flags);
2597 io_apic_write(ioapic, 0, reg_00.raw);
2598 reg_00.raw = io_apic_read(ioapic, 0);
2599 spin_unlock_irqrestore(&ioapic_lock, flags);
2602 if (reg_00.bits.ID != apic_id) {
2603 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2608 apic_printk(APIC_VERBOSE, KERN_INFO
2609 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2615 int __init io_apic_get_version (int ioapic)
2617 union IO_APIC_reg_01 reg_01;
2618 unsigned long flags;
2620 spin_lock_irqsave(&ioapic_lock, flags);
2621 reg_01.raw = io_apic_read(ioapic, 1);
2622 spin_unlock_irqrestore(&ioapic_lock, flags);
2624 return reg_01.bits.version;
2628 int __init io_apic_get_redir_entries (int ioapic)
2630 union IO_APIC_reg_01 reg_01;
2631 unsigned long flags;
2633 spin_lock_irqsave(&ioapic_lock, flags);
2634 reg_01.raw = io_apic_read(ioapic, 1);
2635 spin_unlock_irqrestore(&ioapic_lock, flags);
2637 return reg_01.bits.entries;
2641 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2643 struct IO_APIC_route_entry entry;
2644 unsigned long flags;
2646 if (!IO_APIC_IRQ(irq)) {
2647 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2653 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2654 * Note that we mask (disable) IRQs now -- these get enabled when the
2655 * corresponding device driver registers for this IRQ.
2658 memset(&entry,0,sizeof(entry));
2660 entry.delivery_mode = INT_DELIVERY_MODE;
2661 entry.dest_mode = INT_DEST_MODE;
2662 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2663 entry.trigger = edge_level;
2664 entry.polarity = active_high_low;
2668 * IRQs < 16 are already in the irq_2_pin[] map
2671 add_pin_to_irq(irq, ioapic, pin);
2673 entry.vector = assign_irq_vector(irq);
2675 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2676 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2677 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2678 edge_level, active_high_low);
2680 ioapic_register_intr(irq, entry.vector, edge_level);
2682 if (!ioapic && (irq < 16))
2683 disable_8259A_irq(irq);
2685 spin_lock_irqsave(&ioapic_lock, flags);
2686 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2687 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2688 set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
2689 spin_unlock_irqrestore(&ioapic_lock, flags);
2694 #endif /* CONFIG_ACPI */