2 * (C) 2001-2004 Dave Jones. <davej@codemonkey.org.uk>
3 * (C) 2002 Padraig Brady. <padraig@antefacto.com>
5 * Licensed under the terms of the GNU GPL License version 2.
6 * Based upon datasheets & sample CPUs kindly provided by VIA.
8 * VIA have currently 3 different versions of Longhaul.
9 * Version 1 (Longhaul) uses the BCR2 MSR at 0x1147.
10 * It is present only in Samuel 1 (C5A), Samuel 2 (C5B) stepping 0.
11 * Version 2 of longhaul is the same as v1, but adds voltage scaling.
12 * Present in Samuel 2 (steppings 1-7 only) (C5B), and Ezra (C5C)
13 * voltage scaling support has currently been disabled in this driver
14 * until we have code that gets it right.
15 * Version 3 of longhaul got renamed to Powersaver and redesigned
16 * to use the POWERSAVER MSR at 0x110a.
17 * It is present in Ezra-T (C5M), Nehemiah (C5X) and above.
18 * It's pretty much the same feature wise to longhaul v2, though
19 * there is provision for scaling FSB too, but this doesn't work
20 * too well in practice so we don't even try to use this.
22 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/init.h>
29 #include <linux/cpufreq.h>
30 #include <linux/pci.h>
31 #include <linux/slab.h>
32 #include <linux/string.h>
35 #include <asm/timex.h>
38 #include <linux/acpi.h>
39 #include <acpi/processor.h>
43 #define PFX "longhaul: "
45 #define TYPE_LONGHAUL_V1 1
46 #define TYPE_LONGHAUL_V2 2
47 #define TYPE_POWERSAVER 3
53 #define CPU_NEHEMIAH 5
56 static unsigned int numscales=16;
57 static unsigned int fsb;
59 static struct mV_pos *vrm_mV_table;
60 static unsigned char *mV_vrm_table;
64 static struct f_msr f_msr_table[32];
66 static unsigned int highest_speed, lowest_speed; /* kHz */
67 static unsigned int minmult, maxmult;
68 static int can_scale_voltage;
69 static struct acpi_processor *pr = NULL;
70 static struct acpi_processor_cx *cx = NULL;
73 /* Module parameters */
74 static int scale_voltage;
75 static int ignore_latency;
77 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "longhaul", msg)
80 /* Clock ratios multiplied by 10 */
81 static int clock_ratio[32];
82 static int eblcr_table[32];
83 static unsigned int highest_speed, lowest_speed; /* kHz */
84 static int longhaul_version;
85 static struct cpufreq_frequency_table *longhaul_table;
87 #ifdef CONFIG_CPU_FREQ_DEBUG
88 static char speedbuffer[8];
90 static char *print_speed(int speed)
93 snprintf(speedbuffer, sizeof(speedbuffer),"%dMHz", speed);
98 snprintf(speedbuffer, sizeof(speedbuffer),
101 snprintf(speedbuffer, sizeof(speedbuffer),
102 "%d.%dGHz", speed/1000, (speed%1000)/100);
109 static unsigned int calc_speed(int mult)
120 static int longhaul_get_cpu_mult(void)
122 unsigned long invalue=0,lo, hi;
124 rdmsr (MSR_IA32_EBL_CR_POWERON, lo, hi);
125 invalue = (lo & (1<<22|1<<23|1<<24|1<<25)) >>22;
126 if (longhaul_version==TYPE_LONGHAUL_V2 || longhaul_version==TYPE_POWERSAVER) {
130 return eblcr_table[invalue];
133 /* For processor with BCR2 MSR */
135 static void do_longhaul1(unsigned int clock_ratio_index)
139 rdmsrl(MSR_VIA_BCR2, bcr2.val);
140 /* Enable software clock multiplier */
141 bcr2.bits.ESOFTBF = 1;
142 bcr2.bits.CLOCKMUL = clock_ratio_index;
144 /* Sync to timer tick */
146 /* Change frequency on next halt or sleep */
147 wrmsrl(MSR_VIA_BCR2, bcr2.val);
148 /* Invoke transition */
149 ACPI_FLUSH_CPU_CACHE();
152 /* Disable software clock multiplier */
154 rdmsrl(MSR_VIA_BCR2, bcr2.val);
155 bcr2.bits.ESOFTBF = 0;
156 wrmsrl(MSR_VIA_BCR2, bcr2.val);
159 /* For processor with Longhaul MSR */
161 static void do_powersaver(int cx_address, unsigned int clock_ratio_index)
163 union msr_longhaul longhaul;
166 rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
167 longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
168 longhaul.bits.SoftBusRatio = clock_ratio_index & 0xf;
169 longhaul.bits.SoftBusRatio4 = (clock_ratio_index & 0x10) >> 4;
170 longhaul.bits.EnableSoftBusRatio = 1;
172 if (can_scale_voltage) {
173 longhaul.bits.SoftVID = f_msr_table[clock_ratio_index].vrm;
174 longhaul.bits.EnableSoftVID = 1;
177 /* Sync to timer tick */
179 /* Change frequency on next halt or sleep */
180 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
181 ACPI_FLUSH_CPU_CACHE();
184 /* Dummy op - must do something useless after P_LVL3 read */
185 t = inl(acpi_fadt.xpm_tmr_blk.address);
187 /* Disable bus ratio bit */
189 longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
190 longhaul.bits.EnableSoftBusRatio = 0;
191 longhaul.bits.EnableSoftBSEL = 0;
192 longhaul.bits.EnableSoftVID = 0;
193 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
197 * longhaul_set_cpu_frequency()
198 * @clock_ratio_index : bitpattern of the new multiplier.
200 * Sets a new clock ratio.
203 static void longhaul_setstate(unsigned int clock_ratio_index)
206 struct cpufreq_freqs freqs;
207 static unsigned int old_ratio=-1;
209 unsigned int pic1_mask, pic2_mask;
211 if (old_ratio == clock_ratio_index)
213 old_ratio = clock_ratio_index;
215 mult = clock_ratio[clock_ratio_index];
219 speed = calc_speed(mult);
220 if ((speed > highest_speed) || (speed < lowest_speed))
223 freqs.old = calc_speed(longhaul_get_cpu_mult());
225 freqs.cpu = 0; /* longhaul.c is UP only driver */
227 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
229 dprintk ("Setting to FSB:%dMHz Mult:%d.%dx (%s)\n",
230 fsb, mult/10, mult%10, print_speed(speed/1000));
233 local_irq_save(flags);
235 pic2_mask = inb(0xA1);
236 pic1_mask = inb(0x21); /* works on C3. save mask. */
237 outb(0xFF,0xA1); /* Overkill */
238 outb(0xFE,0x21); /* TMR0 only */
240 if (pr->flags.bm_control) {
241 /* Disable bus master arbitration */
242 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1,
243 ACPI_MTX_DO_NOT_LOCK);
244 } else if (port22_en) {
245 /* Disable AGP and PCI arbiters */
249 switch (longhaul_version) {
252 * Longhaul v1. (Samuel[C5A] and Samuel2 stepping 0[C5B])
253 * Software controlled multipliers only.
255 * *NB* Until we get voltage scaling working v1 & v2 are the same code.
256 * Longhaul v2 appears in Samuel2 Steppings 1->7 [C5b] and Ezra [C5C]
258 case TYPE_LONGHAUL_V1:
259 case TYPE_LONGHAUL_V2:
260 do_longhaul1(clock_ratio_index);
264 * Longhaul v3 (aka Powersaver). (Ezra-T [C5M] & Nehemiah [C5N])
265 * We can scale voltage with this too, but that's currently
266 * disabled until we come up with a decent 'match freq to voltage'
268 * When we add voltage scaling, we will also need to do the
269 * voltage/freq setting in order depending on the direction
270 * of scaling (like we do in powernow-k7.c)
271 * Nehemiah can do FSB scaling too, but this has never been proven
272 * to work in practice.
274 case TYPE_POWERSAVER:
275 /* Don't allow wakeup */
276 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0,
277 ACPI_MTX_DO_NOT_LOCK);
278 do_powersaver(cx->address, clock_ratio_index);
282 if (pr->flags.bm_control) {
283 /* Enable bus master arbitration */
284 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0,
285 ACPI_MTX_DO_NOT_LOCK);
286 } else if (port22_en) {
287 /* Enable arbiters */
291 outb(pic2_mask,0xA1); /* restore mask */
292 outb(pic1_mask,0x21);
294 local_irq_restore(flags);
297 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
301 * Centaur decided to make life a little more tricky.
302 * Only longhaul v1 is allowed to read EBLCR BSEL[0:1].
303 * Samuel2 and above have to try and guess what the FSB is.
304 * We do this by assuming we booted at maximum multiplier, and interpolate
305 * between that value multiplied by possible FSBs and cpu_mhz which
306 * was calculated at boot time. Really ugly, but no other way to do this.
311 static int _guess(int guess)
315 target = ((maxmult/10)*guess);
318 target += ROUNDING/2;
324 static int guess_fsb(void)
326 int speed = (cpu_khz/1000);
328 int speeds[3] = { 66, 100, 133 };
333 for (i=0; i<3; i++) {
334 if (_guess(speeds[i]) == speed)
341 static int __init longhaul_get_ranges(void)
343 unsigned long invalue;
344 unsigned int ezra_t_multipliers[32]= {
345 90, 30, 40, 100, 55, 35, 45, 95,
346 50, 70, 80, 60, 120, 75, 85, 65,
347 -1, 110, 120, -1, 135, 115, 125, 105,
348 130, 150, 160, 140, -1, 155, -1, 145 };
349 unsigned int j, k = 0;
350 union msr_longhaul longhaul;
351 unsigned long lo, hi;
352 unsigned int eblcr_fsb_table_v1[] = { 66, 133, 100, -1 };
353 unsigned int eblcr_fsb_table_v2[] = { 133, 100, -1, 66 };
355 switch (longhaul_version) {
356 case TYPE_LONGHAUL_V1:
357 case TYPE_LONGHAUL_V2:
358 /* Ugh, Longhaul v1 didn't have the min/max MSRs.
359 Assume min=3.0x & max = whatever we booted at. */
361 maxmult = longhaul_get_cpu_mult();
362 rdmsr (MSR_IA32_EBL_CR_POWERON, lo, hi);
363 invalue = (lo & (1<<18|1<<19)) >>18;
364 if (cpu_model==CPU_SAMUEL || cpu_model==CPU_SAMUEL2)
365 fsb = eblcr_fsb_table_v1[invalue];
370 case TYPE_POWERSAVER:
372 if (cpu_model==CPU_EZRA_T) {
373 rdmsrl (MSR_VIA_LONGHAUL, longhaul.val);
374 invalue = longhaul.bits.MaxMHzBR;
375 if (longhaul.bits.MaxMHzBR4)
377 maxmult=ezra_t_multipliers[invalue];
379 invalue = longhaul.bits.MinMHzBR;
380 if (longhaul.bits.MinMHzBR4 == 1)
383 minmult = ezra_t_multipliers[invalue];
384 fsb = eblcr_fsb_table_v2[longhaul.bits.MaxMHzFSB];
389 if (cpu_model==CPU_NEHEMIAH) {
390 rdmsrl (MSR_VIA_LONGHAUL, longhaul.val);
393 * TODO: This code works, but raises a lot of questions.
394 * - Some Nehemiah's seem to have broken Min/MaxMHzBR's.
395 * We get around this by using a hardcoded multiplier of 4.0x
396 * for the minimimum speed, and the speed we booted up at for the max.
397 * This is done in longhaul_get_cpu_mult() by reading the EBLCR register.
398 * - According to some VIA documentation EBLCR is only
399 * in pre-Nehemiah C3s. How this still works is a mystery.
400 * We're possibly using something undocumented and unsupported,
401 * But it works, so we don't grumble.
404 maxmult=longhaul_get_cpu_mult();
406 /* Starting with the 1.2GHz parts, theres a 200MHz bus. */
407 if ((cpu_khz/1000) > 1200)
410 fsb = eblcr_fsb_table_v2[longhaul.bits.MaxMHzFSB];
415 dprintk ("MinMult:%d.%dx MaxMult:%d.%dx\n",
416 minmult/10, minmult%10, maxmult/10, maxmult%10);
419 printk (KERN_INFO PFX "Invalid (reserved) FSB!\n");
423 highest_speed = calc_speed(maxmult);
424 lowest_speed = calc_speed(minmult);
425 dprintk ("FSB:%dMHz Lowest speed: %s Highest speed:%s\n", fsb,
426 print_speed(lowest_speed/1000),
427 print_speed(highest_speed/1000));
429 if (lowest_speed == highest_speed) {
430 printk (KERN_INFO PFX "highestspeed == lowest, aborting.\n");
433 if (lowest_speed > highest_speed) {
434 printk (KERN_INFO PFX "nonsense! lowest (%d > %d) !\n",
435 lowest_speed, highest_speed);
439 longhaul_table = kmalloc((numscales + 1) * sizeof(struct cpufreq_frequency_table), GFP_KERNEL);
443 for (j=0; j < numscales; j++) {
445 ratio = clock_ratio[j];
448 if (ratio > maxmult || ratio < minmult)
450 longhaul_table[k].frequency = calc_speed(ratio);
451 longhaul_table[k].index = j;
455 longhaul_table[k].frequency = CPUFREQ_TABLE_END;
457 kfree (longhaul_table);
465 static void __init longhaul_setup_voltagescaling(void)
467 union msr_longhaul longhaul;
468 struct mV_pos minvid, maxvid;
469 unsigned int j, speed, pos, kHz_step, numvscales;
471 rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
472 if (!(longhaul.bits.RevisionID & 1)) {
473 printk(KERN_INFO PFX "Voltage scaling not supported by CPU.\n");
477 if (!longhaul.bits.VRMRev) {
478 printk (KERN_INFO PFX "VRM 8.5\n");
479 vrm_mV_table = &vrm85_mV[0];
480 mV_vrm_table = &mV_vrm85[0];
482 printk (KERN_INFO PFX "Mobile VRM\n");
483 vrm_mV_table = &mobilevrm_mV[0];
484 mV_vrm_table = &mV_mobilevrm[0];
487 minvid = vrm_mV_table[longhaul.bits.MinimumVID];
488 maxvid = vrm_mV_table[longhaul.bits.MaximumVID];
489 numvscales = maxvid.pos - minvid.pos + 1;
490 kHz_step = (highest_speed - lowest_speed) / numvscales;
492 if (minvid.mV == 0 || maxvid.mV == 0 || minvid.mV > maxvid.mV) {
493 printk (KERN_INFO PFX "Bogus values Min:%d.%03d Max:%d.%03d. "
494 "Voltage scaling disabled.\n",
495 minvid.mV/1000, minvid.mV%1000, maxvid.mV/1000, maxvid.mV%1000);
499 if (minvid.mV == maxvid.mV) {
500 printk (KERN_INFO PFX "Claims to support voltage scaling but min & max are "
501 "both %d.%03d. Voltage scaling disabled\n",
502 maxvid.mV/1000, maxvid.mV%1000);
506 printk(KERN_INFO PFX "Max VID=%d.%03d Min VID=%d.%03d, %d possible voltage scales\n",
507 maxvid.mV/1000, maxvid.mV%1000,
508 minvid.mV/1000, minvid.mV%1000,
512 while (longhaul_table[j].frequency != CPUFREQ_TABLE_END) {
513 speed = longhaul_table[j].frequency;
514 pos = (speed - lowest_speed) / kHz_step + minvid.pos;
515 f_msr_table[longhaul_table[j].index].vrm = mV_vrm_table[pos];
519 can_scale_voltage = 1;
523 static int longhaul_verify(struct cpufreq_policy *policy)
525 return cpufreq_frequency_table_verify(policy, longhaul_table);
529 static int longhaul_target(struct cpufreq_policy *policy,
530 unsigned int target_freq, unsigned int relation)
532 unsigned int table_index = 0;
533 unsigned int new_clock_ratio = 0;
535 if (cpufreq_frequency_table_target(policy, longhaul_table, target_freq, relation, &table_index))
538 new_clock_ratio = longhaul_table[table_index].index & 0xFF;
540 longhaul_setstate(new_clock_ratio);
546 static unsigned int longhaul_get(unsigned int cpu)
550 return calc_speed(longhaul_get_cpu_mult());
553 static acpi_status longhaul_walk_callback(acpi_handle obj_handle,
555 void *context, void **return_value)
557 struct acpi_device *d;
559 if ( acpi_bus_get_device(obj_handle, &d) ) {
562 *return_value = (void *)acpi_driver_data(d);
566 /* VIA don't support PM2 reg, but have something similar */
567 static int enable_arbiter_disable(void)
572 /* Find PLE133 host bridge */
573 dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8601_0, NULL);
575 /* Enable access to port 0x22 */
576 pci_read_config_byte(dev, 0x78, &pci_cmd);
577 if ( !(pci_cmd & 1<<7) ) {
579 pci_write_config_byte(dev, 0x78, pci_cmd);
586 static int __init longhaul_cpu_init(struct cpufreq_policy *policy)
588 struct cpuinfo_x86 *c = cpu_data;
592 /* Check what we have on this motherboard */
593 switch (c->x86_model) {
595 cpu_model = CPU_SAMUEL;
596 cpuname = "C3 'Samuel' [C5A]";
597 longhaul_version = TYPE_LONGHAUL_V1;
598 memcpy (clock_ratio, samuel1_clock_ratio, sizeof(samuel1_clock_ratio));
599 memcpy (eblcr_table, samuel1_eblcr, sizeof(samuel1_eblcr));
603 longhaul_version = TYPE_LONGHAUL_V1;
604 switch (c->x86_mask) {
606 cpu_model = CPU_SAMUEL2;
607 cpuname = "C3 'Samuel 2' [C5B]";
608 /* Note, this is not a typo, early Samuel2's had Samuel1 ratios. */
609 memcpy (clock_ratio, samuel1_clock_ratio, sizeof(samuel1_clock_ratio));
610 memcpy (eblcr_table, samuel2_eblcr, sizeof(samuel2_eblcr));
613 if (c->x86_mask < 8) {
614 cpu_model = CPU_SAMUEL2;
615 cpuname = "C3 'Samuel 2' [C5B]";
617 cpu_model = CPU_EZRA;
618 cpuname = "C3 'Ezra' [C5C]";
620 memcpy (clock_ratio, ezra_clock_ratio, sizeof(ezra_clock_ratio));
621 memcpy (eblcr_table, ezra_eblcr, sizeof(ezra_eblcr));
627 cpu_model = CPU_EZRA_T;
628 cpuname = "C3 'Ezra-T' [C5M]";
629 longhaul_version = TYPE_POWERSAVER;
631 memcpy (clock_ratio, ezrat_clock_ratio, sizeof(ezrat_clock_ratio));
632 memcpy (eblcr_table, ezrat_eblcr, sizeof(ezrat_eblcr));
636 cpu_model = CPU_NEHEMIAH;
637 longhaul_version = TYPE_POWERSAVER;
639 switch (c->x86_mask) {
641 cpuname = "C3 'Nehemiah A' [C5N]";
642 memcpy (clock_ratio, nehemiah_a_clock_ratio, sizeof(nehemiah_a_clock_ratio));
643 memcpy (eblcr_table, nehemiah_a_eblcr, sizeof(nehemiah_a_eblcr));
646 cpuname = "C3 'Nehemiah B' [C5N]";
647 memcpy (clock_ratio, nehemiah_b_clock_ratio, sizeof(nehemiah_b_clock_ratio));
648 memcpy (eblcr_table, nehemiah_b_eblcr, sizeof(nehemiah_b_eblcr));
651 cpuname = "C3 'Nehemiah C' [C5N]";
652 memcpy (clock_ratio, nehemiah_c_clock_ratio, sizeof(nehemiah_c_clock_ratio));
653 memcpy (eblcr_table, nehemiah_c_eblcr, sizeof(nehemiah_c_eblcr));
663 printk (KERN_INFO PFX "VIA %s CPU detected. ", cpuname);
664 switch (longhaul_version) {
665 case TYPE_LONGHAUL_V1:
666 case TYPE_LONGHAUL_V2:
667 printk ("Longhaul v%d supported.\n", longhaul_version);
669 case TYPE_POWERSAVER:
670 printk ("Powersaver supported.\n");
674 /* Find ACPI data for processor */
675 acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT, ACPI_UINT32_MAX,
676 &longhaul_walk_callback, NULL, (void *)&pr);
680 if (longhaul_version == TYPE_POWERSAVER) {
681 /* Check ACPI support for C3 state */
682 cx = &pr->power.states[ACPI_STATE_C3];
683 if (cx->address == 0 ||
684 (cx->latency > 1000 && ignore_latency == 0) )
688 /* Check ACPI support for bus master arbiter disable */
689 if (!pr->flags.bm_control) {
690 if (!enable_arbiter_disable()) {
691 printk(KERN_ERR PFX "No ACPI support. No VT8601 host bridge. Aborting.\n");
698 ret = longhaul_get_ranges();
702 if ((longhaul_version==TYPE_LONGHAUL_V2 || longhaul_version==TYPE_POWERSAVER) &&
703 (scale_voltage != 0))
704 longhaul_setup_voltagescaling();
706 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
707 policy->cpuinfo.transition_latency = 200000; /* nsec */
708 policy->cur = calc_speed(longhaul_get_cpu_mult());
710 ret = cpufreq_frequency_table_cpuinfo(policy, longhaul_table);
714 cpufreq_frequency_table_get_attr(longhaul_table, policy->cpu);
719 printk(KERN_ERR PFX "No ACPI support for CPU frequency changes.\n");
723 static int __devexit longhaul_cpu_exit(struct cpufreq_policy *policy)
725 cpufreq_frequency_table_put_attr(policy->cpu);
729 static struct freq_attr* longhaul_attr[] = {
730 &cpufreq_freq_attr_scaling_available_freqs,
734 static struct cpufreq_driver longhaul_driver = {
735 .verify = longhaul_verify,
736 .target = longhaul_target,
738 .init = longhaul_cpu_init,
739 .exit = __devexit_p(longhaul_cpu_exit),
741 .owner = THIS_MODULE,
742 .attr = longhaul_attr,
746 static int __init longhaul_init(void)
748 struct cpuinfo_x86 *c = cpu_data;
750 if (c->x86_vendor != X86_VENDOR_CENTAUR || c->x86 != 6)
754 if (num_online_cpus() > 1) {
756 printk(KERN_ERR PFX "More than 1 CPU detected, longhaul disabled.\n");
759 #ifdef CONFIG_X86_IO_APIC
761 printk(KERN_ERR PFX "APIC detected. Longhaul is currently broken in this configuration.\n");
765 switch (c->x86_model) {
767 return cpufreq_register_driver(&longhaul_driver);
769 printk (KERN_INFO PFX "Unknown VIA CPU. Contact davej@codemonkey.org.uk\n");
776 static void __exit longhaul_exit(void)
780 for (i=0; i < numscales; i++) {
781 if (clock_ratio[i] == maxmult) {
782 longhaul_setstate(i);
787 cpufreq_unregister_driver(&longhaul_driver);
788 kfree(longhaul_table);
791 module_param (scale_voltage, int, 0644);
792 MODULE_PARM_DESC(scale_voltage, "Scale voltage of processor");
793 module_param(ignore_latency, int, 0644);
794 MODULE_PARM_DESC(ignore_latency, "Skip ACPI C3 latency test");
796 MODULE_AUTHOR ("Dave Jones <davej@codemonkey.org.uk>");
797 MODULE_DESCRIPTION ("Longhaul driver for VIA Cyrix processors.");
798 MODULE_LICENSE ("GPL");
800 late_initcall(longhaul_init);
801 module_exit(longhaul_exit);