3 * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* This file is largely based on code obtned from AMD. AMD's original
25 * copyright is included below
28 /* TITLE SIZER - Aspen DRAM Sizing Routine.
29 * =============================================================================
31 * Copyright 1999 Advanced Micro Devices, Inc.
32 * You may redistribute this program and/or modify this program under the terms
33 * of the GNU General Public License as published by the Free Software Foundation;
34 * either version 2 of the License, or (at your option) any later version.
36 * This program is distributed WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
37 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
38 * General Public License for more details.
40 * You should have received a copy of the GNU General Public License along with
41 * this program; if not, write to the Free Software Foundation, Inc.,
42 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
44 * THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY
45 * OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF
46 * THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE.
47 * IN NO EVENT SHALL AMD OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES WHATSOEVER
48 * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
49 * INTERRUPTION, LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR INABILITY
50 * TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE POSSIBILITY OF
51 * SUCH DAMAGES. BECAUSE SOME JURSIDICTIONS PROHIBIT THE EXCLUSION OR
52 * LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
53 * LIMITATION MAY NOT APPLY TO YOU.
55 * AMD does not assume any responsibility for any errors that may appear in
56 * the Materials nor any responsibility to support or update the Materials.
57 * AMD retains the right to make changes to its test specifications at any
58 * time, without notice.
59 * ==============================================================================
63 ******************************************************************************
65 * FILE : sizer.asm - SDRAM DIMM Sizing Algorithm
69 * FUNCTIONS : sizemem() - jumped to, not called. To be executed after
70 * reset to determine the size of the SDRAM DIMMs. Initializes
71 * the memory subsystem.
74 * AUTHOR : Buddy Fey - Original.
77 * DESCRIPTION : Performs sizing on SDRAM DIMMs on ASPEN processor.
78 * NOTE: This is a small memory model version
81 * INPUTS : BP contains return address offset
82 * CACHE is assumed to be disabled.
83 * The FS segment limit has already been set to big real mode
84 * (full 32-bit addressing capability)
90 * REG USE : ax,bx,cx,dx,di,si,bp, fs
93 * REVISION : See PVCS info below
96 * TEST PLAN CROSS REFERENCE:
101 * $Date: 1999/09/22 12:49:33 $
104 * Revision 1.2 1999/09/22 12:49:33 chipf
107 *******************************************************************************
111 /*******************************************************************************
112 * FUNCTIONAL DESCRIPTION:
113 * This routine is called to autodetect the geometry of the DRAM.
115 * This routine is called to determine the number of column bits for the DRAM
116 * devices in this external bank. This routine assumes that the external bank
117 * has been configured for an 11-bit column and for 4 internal banks. This gives
118 * us the maximum address reach in memory. By writing a test value to the max
119 * address and locating where it aliases to, we can determine the number of valid
122 * This routine is called to determine the number of internal banks each DRAM
123 * device has. The external bank (under test) is configured for maximum reach
124 * with 11-bit columns and 4 internal banks. This routine will write to a max
125 * address (BA1 and BA0 = 1) and then read from an address with BA1=0 to see if
126 * that column is a "don't care". If BA1 does not affect write/read of data,
127 * then this device has only 2 internal banks.
129 * This routine is called to determine the ending address for this external
130 * bank of SDRAM. We write to a max address with a data value and then disable
131 * row address bits looking for "don't care" locations. Each "don't care" bit
132 * represents a dividing of the maximum density (128M) by 2. By dividing the
133 * maximum of 32 4M chunks in an external bank down by all the "don't care" bits
134 * determined during sizing, we set the proper density.
137 * bp must be preserved because it is used for return linkage.
140 * nothing returned - but the memory subsystem is enabled
141 *******************************************************************************
147 .equ DRCCTL, 0x0fffef010 /* DRAM control register */
148 .equ DRCTMCTL, 0x0fffef012 /* DRAM timing control register */
149 .equ DRCCFG, 0x0fffef014 /* DRAM bank configuration register */
150 .equ DRCBENDADR, 0x0fffef018 /* DRAM bank ending address register */
151 .equ ECCCTL, 0x0fffef020 /* DRAM ECC control register */
152 .equ ECCINT, 0x0fffefd18 /* DRAM ECC nmi-INT mapping */
153 .equ DBCTL, 0x0fffef040 /* DRAM buffer control register */
155 .equ CACHELINESZ, 0x00000010 /* size of our cache line (read buffer) */
156 .equ COL11_ADR, 0x0e001e00 /* 11 col addrs */
157 .equ COL10_ADR, 0x0e000e00 /* 10 col addrs */
158 .equ COL09_ADR, 0x0e000600 /* 9 col addrs */
159 .equ COL08_ADR, 0x0e000200 /* 8 col addrs */
160 .equ ROW14_ADR, 0x0f000000 /* 14 row addrs */
161 .equ ROW13_ADR, 0x07000000 /* 13 row addrs */
162 .equ ROW12_ADR, 0x03000000 /* 12 row addrs */
163 .equ ROW11_ADR, 0x01000000 /* 11 row addrs/also bank switch */
164 .equ ROW10_ADR, 0x00000000 /* 10 row addrs/also bank switch */
165 .equ COL11_DATA, 0x0b0b0b0b /* 11 col addrs */
166 .equ COL10_DATA, 0x0a0a0a0a /* 10 col data */
167 .equ COL09_DATA, 0x09090909 /* 9 col data */
168 .equ COL08_DATA, 0x08080808 /* 8 col data */
169 .equ ROW14_DATA, 0x3f3f3f3f /* 14 row data (MASK) */
170 .equ ROW13_DATA, 0x1f1f1f1f /* 13 row data (MASK) */
171 .equ ROW12_DATA, 0x0f0f0f0f /* 12 row data (MASK) */
172 .equ ROW11_DATA, 0x07070707 /* 11 row data/also bank switch (MASK) */
173 .equ ROW10_DATA, 0xaaaaaaaa /* 10 row data/also bank switch (MASK) */
177 /* Preserve Boot Flags */
180 /* initialize dram controller registers */
183 movb %al, (%edi) /* disable write buffer */
186 movb %al, (%edi) /* disable ECC */
189 movb $0x1e, %al /* Set SDRAM timing for slowest */
192 /* setup loop to do 4 external banks starting with bank 3 */
193 movl $0xff000000, %eax /* enable last bank and setup */
194 movl $DRCBENDADR, %edi /* ending address register */
197 movl $DRCCFG, %edi /* setup */
198 movw $0xbbbb, %ax /* dram config register for */
201 /* issue a NOP to all DRAMs */
202 movl $DRCCTL, %edi /* setup DRAM control register with */
203 movb $0x01, %al /* Disable refresh,disable write buffer */
205 movl $CACHELINESZ, %esi /* just a dummy address to write for */
208 /* delay for 100 usec? */
213 /* issue all banks precharge */
218 /* issue 2 auto refreshes to all banks */
219 movb $0x04, %al /* Auto refresh cmd */
226 /* issue LOAD MODE REGISTER command */
227 movb $0x03, %al /* Load mode register cmd */
231 /* issue 8 more auto refreshes to all banks */
232 movb $0x04, %al /* Auto refresh cmd */
239 /* set control register to NORMAL mode */
240 movb $0x00, %al /* Normal mode value */
244 * size dram starting with external bank 3
245 * moving to external bank 0
247 movl $0x3, %ecx /* start with external bank 3 */
251 /* write col 11 wrap adr */
252 movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
253 movl $COL11_DATA, %eax /* pattern for max supported columns(11) */
254 movl %eax, (%esi) /* write max col pattern at max col adr */
255 movl (%esi), %ebx /* optional read */
256 cmpl %ebx, %eax /* to verify write */
257 jnz bad_ram /* this ram is bad */
259 /* write col 10 wrap adr */
260 movl $COL10_ADR, %esi /* set address to 10 col wrap address */
261 movl $COL10_DATA, %eax /* pattern for 10 col wrap */
262 movl %eax, (%esi) /* write 10 col pattern @ 10 col wrap adr */
263 movl (%esi), %ebx /* optional read */
264 cmpl %ebx, %eax /* to verify write */
265 jnz bad_ram /* this ram is bad */
267 /* write col 9 wrap adr */
268 movl $COL09_ADR, %esi /* set address to 9 col wrap address */
269 movl $COL09_DATA, %eax /* pattern for 9 col wrap */
270 movl %eax, (%esi) /* write 9 col pattern @ 9 col wrap adr */
271 movl (%esi), %ebx /* optional read */
272 cmpl %ebx, %eax /* to verify write */
273 jnz bad_ram /* this ram is bad */
275 /* write col 8 wrap adr */
276 movl $COL08_ADR, %esi /* set address to min(8) col wrap address */
277 movl $COL08_DATA, %eax /* pattern for min (8) col wrap */
278 movl %eax, (%esi) /* write min col pattern @ min col adr */
279 movl (%esi), %ebx /* optional read */
280 cmpl %ebx, %eax /* to verify write */
281 jnz bad_ram /* this ram is bad */
283 /* write row 14 wrap adr */
284 movl $ROW14_ADR, %esi /* set address to max row (14) wrap addr */
285 movl $ROW14_DATA, %eax /* pattern for max supported rows(14) */
286 movl %eax, (%esi) /* write max row pattern at max row adr */
287 movl (%esi), %ebx /* optional read */
288 cmpl %ebx, %eax /* to verify write */
289 jnz bad_ram /* this ram is bad */
291 /* write row 13 wrap adr */
292 movl $ROW13_ADR, %esi /* set address to 13 row wrap address */
293 movl $ROW13_DATA, %eax /* pattern for 13 row wrap */
294 movl %eax, (%esi) /* write 13 row pattern @ 13 row wrap adr */
295 movl (%esi), %ebx /* optional read */
296 cmpl %ebx, %eax /* to verify write */
297 jnz bad_ram /* this ram is bad */
299 /* write row 12 wrap adr */
300 movl $ROW12_ADR, %esi /* set address to 12 row wrap address */
301 movl $ROW12_DATA, %eax /* pattern for 12 row wrap */
302 movl %eax, (%esi) /* write 12 row pattern @ 12 row wrap adr */
303 movl (%esi), %ebx /* optional read */
304 cmpl %ebx, %eax /* to verify write */
305 jnz bad_ram /* this ram is bad */
307 /* write row 11 wrap adr */
308 movl $ROW11_ADR, %edi /* set address to 11 row wrap address */
309 movl $ROW11_DATA, %eax /* pattern for 11 row wrap */
310 movl %eax, (%edi) /* write 11 row pattern @ 11 row wrap adr */
311 movl (%edi), %ebx /* optional read */
312 cmpl %ebx, %eax /* to verify write */
313 jnz bad_ram /* this ram is bad */
316 * write row 10 wrap adr --- this write is really to determine
319 movl $ROW10_ADR, %edi /* set address to 10 row wrap address */
320 movl $ROW10_DATA, %eax /* pattern for 10 row wrap (AA) */
321 movl %eax, (%edi) /* write 10 row pattern @ 10 row wrap adr */
322 movl (%edi), %ebx /* optional read */
323 cmpl %ebx, %eax /* to verify write */
324 jnz bad_ram /* this ram is bad */
327 * read data @ row 12 wrap adr to determine * banks,
328 * and read data @ row 14 wrap adr to determine * rows.
329 * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
330 * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
331 * if data @ row 12 wrap == 11 or 12, we have 4 banks,
333 xorw %di, %di /* value for 2 banks in DI */
334 movl (%esi), %ebx /* read from 12 row wrap to check banks */
335 /* (esi is setup from the write to row 12 wrap) */
336 cmpl %ebx, %eax /* check for AA pattern (eax holds the aa pattern) */
337 jz only2 /* if pattern == AA, we only have 2 banks */
341 movw $0x008, %di /* value for 4 banks in DI (BNK_CNT bit) */
342 cmpl $ROW11_DATA, %ebx /* only other legitimate values are 11 */
344 cmpl $ROW12_DATA, %ebx /* and 12 */
345 jnz bad_ram /* its bad if not 11 or 12! */
352 movl $ROW14_ADR, %esi /* set address back to max row wrap addr */
353 movl (%esi), %eax /* read actual number of rows @ row14 adr */
355 cmpl $ROW11_DATA, %eax /* row must be greater than 11 pattern */
358 cmpl $ROW14_DATA, %eax /* and row must be less than 14 pattern */
361 cmpb %ah, %al /* verify all 4 bytes of dword same */
369 * read col 11 wrap adr for real column data value
371 movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
372 movl (%esi), %eax /* read real col number at max col adr */
375 * validate column data
377 cmpl $COL08_DATA, %eax /* col must be greater than 8 pattern */
380 cmpl $COL11_DATA, %eax /* and row must be less than 11 pattern */
383 subl $COL08_DATA, %eax /* normalize column data to zero */
385 cmpb %ah, %al /* verify all 4 bytes of dword equal */
393 * merge bank and col data together
395 addw %di, %dx /* merge of bank and col info in dl */
398 * fix ending addr mask based upon col info
401 subb %dh, %al /* dh contains the overflow from the bank/col merge */
402 movb %bl, %dh /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */
403 xchgw %cx, %ax /* cx = ax = 3 or 2 depending on 2 or 4 bank device */
405 incb %dh /* ending addr is 1 greater than real end */
406 xchgw %cx, %ax /* cx is bank number again */
410 * issue all banks precharge
412 movl $DRCCTL, %esi /* setup DRAM control register with */
413 movb $0x02, %al /* All banks precharge */
415 movl $CACHELINESZ, %esi /* address to init read buffer */
419 * update ENDING ADDRESS REGISTER
421 movl $DRCBENDADR, %edi /* DRAM ending address register */
427 * update CONFIG REGISTER
447 movl $DRCBENDADR, %edi /* DRAM ending address register */
453 * set control register to NORMAL mode
455 movl $DRCCTL, %esi /* setup DRAM control register with */
456 movb $0x00, %al /* Normal mode value */
458 movl $CACHELINESZ, %esi /* address to init read buffer */
463 movl $DRCBENDADR, %edi /* DRAM ending address register */
483 #if defined CONFIG_SYS_SDRAM_DRCTMCTL
484 /* just have your hardware desinger _GIVE_ you what you need here! */
486 movb $CONFIG_SYS_SDRAM_DRCTMCTL, %al
489 #if defined(CONFIG_SYS_SDRAM_CAS_LATENCY_2T) || defined(CONFIG_SYS_SDRAM_CAS_LATENCY_3T)
491 * Set the CAS latency now since it is hard to do
492 * when we run from the RAM
494 movl $DRCTMCTL, %edi /* DRAM timing register */
496 #ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
499 #ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
505 movl $DRCCTL, %edi /* DRAM Control register */
506 movb $0x03, %al /* Load mode register cmd */
511 movl $DRCCTL, %edi /* DRAM Control register */
512 movb $0x18, %al /* Enable refresh and NORMAL mode */
523 /* Restore Boot Flags */
527 #if CONFIG_SYS_SDRAM_ECC_ENABLE
530 /* A nominal memory test: just a byte at each address line */
545 /* clear all ram with a memset */
554 /* enable read, write buffers */
559 /* enable NMI mapping for ECC */
574 * Read and decode the sc520 DRCBENDADR MMCR and return the number of
575 * available ram bytes in %eax
579 movl $DRCBENDADR, %edi /* DRAM ending address register */
581 bank0: movl (%edi), %eax
583 andl $0x00000080, %ecx
585 andl $0x0000007f, %eax
589 bank1: movl (%edi), %eax
591 andl $0x00008000, %ecx
593 andl $0x00007f00, %eax
597 bank2: movl (%edi), %eax
599 andl $0x00800000, %ecx
601 andl $0x007f0000, %eax
605 bank3: movl (%edi), %eax
607 andl $0x80000000, %ecx
609 andl $0x7f000000, %eax