arch/blackfin/mach-common/cpufreq.c

   1 /*
   2  * Blackfin core clock scaling
   3  *
   4  * Copyright 2008-2011 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/types.h>
  12 #include <linux/init.h>
  13 #include <linux/clk.h>
  14 #include <linux/cpufreq.h>
  15 #include <linux/fs.h>
  16 #include <linux/delay.h>
  17 #include <asm/blackfin.h>
  18 #include <asm/time.h>
  19 #include <asm/dpmc.h>
  20
  21
  22 /* this is the table of CCLK frequencies, in Hz */
  23 /* .index is the entry in the auxiliary dpm_state_table[] */
  24 static struct cpufreq_frequency_table bfin_freq_table[] = {
  25         {
  26                 .frequency = CPUFREQ_TABLE_END,
  27                 .index = 0,
  28         },
  29         {
  30                 .frequency = CPUFREQ_TABLE_END,
  31                 .index = 1,
  32         },
  33         {
  34                 .frequency = CPUFREQ_TABLE_END,
  35                 .index = 2,
  36         },
  37         {
  38                 .frequency = CPUFREQ_TABLE_END,
  39                 .index = 0,
  40         },
  41 };
  42
  43 static struct bfin_dpm_state {
  44         unsigned int csel; /* system clock divider */
  45         unsigned int tscale; /* change the divider on the core timer interrupt */
  46 } dpm_state_table[3];
  47
  48 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
  49 /*
  50  * normalized to maximum frequency offset for CYCLES,
  51  * used in time-ts cycles clock source, but could be used
  52  * somewhere also.
  53  */
  54 unsigned long long __bfin_cycles_off;
  55 unsigned int __bfin_cycles_mod;
  56 #endif
  57
  58 /**************************************************************************/
  59 static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk)
  60 {
  61
  62         unsigned long csel, min_cclk;
  63         int index;
  64
  65         /* Anomaly 273 seems to still exist on non-BF54x w/dcache turned on */
  66 #if ANOMALY_05000273 || ANOMALY_05000274 || \
  67         (!(defined(CONFIG_BF54x) || defined(CONFIG_BF60x)) \
  68         && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE))
  69         min_cclk = sclk * 2;
  70 #else
  71         min_cclk = sclk;
  72 #endif
  73
  74 #ifndef CONFIG_BF60x
  75         csel = ((bfin_read_PLL_DIV() & CSEL) >> 4);
  76 #else
  77         csel = bfin_read32(CGU0_DIV) & 0x1F;
  78 #endif
  79
  80         for (index = 0;  (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) {
  81                 bfin_freq_table[index].frequency = cclk >> index;
  82 #ifndef CONFIG_BF60x
  83                 dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */
  84                 dpm_state_table[index].tscale =  (TIME_SCALE / (1 << csel)) - 1;
  85 #else
  86                 dpm_state_table[index].csel = csel;
  87                 dpm_state_table[index].tscale =  TIME_SCALE >> index;
  88 #endif
  89
  90                 pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n",
  91                                                  bfin_freq_table[index].frequency,
  92                                                  dpm_state_table[index].csel,
  93                                                  dpm_state_table[index].tscale);
  94         }
  95         return;
  96 }
  97
  98 static void bfin_adjust_core_timer(void *info)
  99 {
 100         unsigned int tscale;
 101         unsigned int index = *(unsigned int *)info;
 102
 103         /* we have to adjust the core timer, because it is using cclk */
 104         tscale = dpm_state_table[index].tscale;
 105         bfin_write_TSCALE(tscale);
 106         return;
 107 }
 108
 109 static unsigned int bfin_getfreq_khz(unsigned int cpu)
 110 {
 111         /* Both CoreA/B have the same core clock */
 112         return get_cclk() / 1000;
 113 }
 114
 115 #ifdef CONFIG_BF60x
 116 unsigned long cpu_set_cclk(int cpu, unsigned long new)
 117 {
 118         struct clk *clk;
 119         int ret;
 120
 121         clk = clk_get(NULL, "CCLK");
 122         if (IS_ERR(clk))
 123                 return -ENODEV;
 124
 125         ret = clk_set_rate(clk, new);
 126         clk_put(clk);
 127         return ret;
 128 }
 129 #endif
 130
 131 static int bfin_target(struct cpufreq_policy *poli,
 132                         unsigned int target_freq, unsigned int relation)
 133 {
 134 #ifndef CONFIG_BF60x
 135         unsigned int plldiv;
 136 #endif
 137         unsigned int index, cpu;
 138         unsigned long flags, cclk_hz;
 139         struct cpufreq_freqs freqs;
 140         static unsigned long lpj_ref;
 141         static unsigned int  lpj_ref_freq;
 142         int ret = 0;
 143
 144 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
 145         cycles_t cycles;
 146 #endif
 147
 148         for_each_online_cpu(cpu) {
 149                 struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
 150
 151                 if (!policy)
 152                         continue;
 153
 154                 if (cpufreq_frequency_table_target(policy, bfin_freq_table,
 155                                  target_freq, relation, &index))
 156                         return -EINVAL;
 157
 158                 cclk_hz = bfin_freq_table[index].frequency;
 159
 160                 freqs.old = bfin_getfreq_khz(0);
 161                 freqs.new = cclk_hz;
 162                 freqs.cpu = cpu;
 163
 164                 pr_debug("cpufreq: changing cclk to %lu; target = %u, oldfreq = %u\n",
 165                          cclk_hz, target_freq, freqs.old);
 166
 167                 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 168                 if (cpu == CPUFREQ_CPU) {
 169                         flags = hard_local_irq_save();
 170 #ifndef CONFIG_BF60x
 171                         plldiv = (bfin_read_PLL_DIV() & SSEL) |
 172                                                 dpm_state_table[index].csel;
 173                         bfin_write_PLL_DIV(plldiv);
 174 #else
 175                         ret = cpu_set_cclk(cpu, freqs.new * 1000);
 176                         if (ret != 0) {
 177                                 WARN_ONCE(ret, "cpufreq set freq failed %d\n", ret);
 178                                 break;
 179                         }
 180 #endif
 181                         on_each_cpu(bfin_adjust_core_timer, &index, 1);
 182 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
 183                         cycles = get_cycles();
 184                         SSYNC();
 185                         cycles += 10; /* ~10 cycles we lose after get_cycles() */
 186                         __bfin_cycles_off +=
 187                             (cycles << __bfin_cycles_mod) - (cycles << index);
 188                         __bfin_cycles_mod = index;
 189 #endif
 190                         if (!lpj_ref_freq) {
 191                                 lpj_ref = loops_per_jiffy;
 192                                 lpj_ref_freq = freqs.old;
 193                         }
 194                         if (freqs.new != freqs.old) {
 195                                 loops_per_jiffy = cpufreq_scale(lpj_ref,
 196                                                 lpj_ref_freq, freqs.new);
 197                         }
 198                         hard_local_irq_restore(flags);
 199                 }
 200                 /* TODO: just test case for cycles clock source, remove later */
 201                 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 202         }
 203
 204         pr_debug("cpufreq: done\n");
 205         return ret;
 206 }
 207
 208 static int bfin_verify_speed(struct cpufreq_policy *policy)
 209 {
 210         return cpufreq_frequency_table_verify(policy, bfin_freq_table);
 211 }
 212
 213 static int __bfin_cpu_init(struct cpufreq_policy *policy)
 214 {
 215
 216         unsigned long cclk, sclk;
 217
 218         cclk = get_cclk() / 1000;
 219         sclk = get_sclk() / 1000;
 220
 221         if (policy->cpu == CPUFREQ_CPU)
 222                 bfin_init_tables(cclk, sclk);
 223
 224         policy->cpuinfo.transition_latency = 50000; /* 50us assumed */
 225
 226         policy->cur = cclk;
 227         cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu);
 228         return cpufreq_frequency_table_cpuinfo(policy, bfin_freq_table);
 229 }
 230
 231 static struct freq_attr *bfin_freq_attr[] = {
 232         &cpufreq_freq_attr_scaling_available_freqs,
 233         NULL,
 234 };
 235
 236 static struct cpufreq_driver bfin_driver = {
 237         .verify = bfin_verify_speed,
 238         .target = bfin_target,
 239         .get = bfin_getfreq_khz,
 240         .init = __bfin_cpu_init,
 241         .name = "bfin cpufreq",
 242         .owner = THIS_MODULE,
 243         .attr = bfin_freq_attr,
 244 };
 245
 246 static int __init bfin_cpu_init(void)
 247 {
 248         return cpufreq_register_driver(&bfin_driver);
 249 }
 250
 251 static void __exit bfin_cpu_exit(void)
 252 {
 253         cpufreq_unregister_driver(&bfin_driver);
 254 }
 255
 256 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
 257 MODULE_DESCRIPTION("cpufreq driver for Blackfin");
 258 MODULE_LICENSE("GPL");
 259
 260 module_init(bfin_cpu_init);
 261 module_exit(bfin_cpu_exit);