2 * Blackfin bf609 power management
4 * Copyright 2011 Analog Devices Inc.
6 * Licensed under the GPL-2
9 #include <linux/suspend.h>
11 #include <linux/interrupt.h>
12 #include <linux/gpio.h>
13 #include <linux/irq.h>
14 #include <linux/delay.h>
15 #include <linux/syscore_ops.h>
20 #include <asm/blackfin.h>
21 #include <asm/mem_init.h>
23 /***********************************************************/
25 /* Wakeup Actions for DPM_RESTORE */
27 /***********************************************************/
28 #define BITP_ROM_WUA_CHKHDR 24
29 #define BITP_ROM_WUA_DDRLOCK 7
30 #define BITP_ROM_WUA_DDRDLLEN 6
31 #define BITP_ROM_WUA_DDR 5
32 #define BITP_ROM_WUA_CGU 4
33 #define BITP_ROM_WUA_MEMBOOT 2
34 #define BITP_ROM_WUA_EN 1
36 #define BITM_ROM_WUA_CHKHDR (0xFF000000)
37 #define ENUM_ROM_WUA_CHKHDR_AD 0xAD000000
39 #define BITM_ROM_WUA_DDRLOCK (0x00000080)
40 #define BITM_ROM_WUA_DDRDLLEN (0x00000040)
41 #define BITM_ROM_WUA_DDR (0x00000020)
42 #define BITM_ROM_WUA_CGU (0x00000010)
43 #define BITM_ROM_WUA_MEMBOOT (0x00000002)
44 #define BITM_ROM_WUA_EN (0x00000001)
46 /***********************************************************/
50 /***********************************************************/
51 #define BITP_ROM_SYSCTRL_CGU_LOCKINGEN 28 /* unlocks CGU_CTL register */
52 #define BITP_ROM_SYSCTRL_WUA_OVERRIDE 24
53 #define BITP_ROM_SYSCTRL_WUA_DDRDLLEN 20 /* Saves the DDR DLL and PADS registers to the DPM registers */
54 #define BITP_ROM_SYSCTRL_WUA_DDR 19 /* Saves the DDR registers to the DPM registers */
55 #define BITP_ROM_SYSCTRL_WUA_CGU 18 /* Saves the CGU registers into DPM registers */
56 #define BITP_ROM_SYSCTRL_WUA_DPMWRITE 17 /* Saves the Syscontrol structure structure contents into DPM registers */
57 #define BITP_ROM_SYSCTRL_WUA_EN 16 /* reads current PLL and DDR configuration into structure */
58 #define BITP_ROM_SYSCTRL_DDR_WRITE 13 /* writes the DDR registers from Syscontrol structure for wakeup initialization of DDR */
59 #define BITP_ROM_SYSCTRL_DDR_READ 12 /* Read the DDR registers into the Syscontrol structure for storing prior to hibernate */
60 #define BITP_ROM_SYSCTRL_CGU_AUTODIS 11 /* Disables auto handling of UPDT and ALGN fields */
61 #define BITP_ROM_SYSCTRL_CGU_CLKOUTSEL 7 /* access CGU_CLKOUTSEL register */
62 #define BITP_ROM_SYSCTRL_CGU_DIV 6 /* access CGU_DIV register */
63 #define BITP_ROM_SYSCTRL_CGU_STAT 5 /* access CGU_STAT register */
64 #define BITP_ROM_SYSCTRL_CGU_CTL 4 /* access CGU_CTL register */
65 #define BITP_ROM_SYSCTRL_CGU_RTNSTAT 2 /* Update structure STAT field upon error */
66 #define BITP_ROM_SYSCTRL_WRITE 1 /* write registers */
67 #define BITP_ROM_SYSCTRL_READ 0 /* read registers */
69 #define BITM_ROM_SYSCTRL_CGU_READ (0x00000001) /* Read CGU registers */
70 #define BITM_ROM_SYSCTRL_CGU_WRITE (0x00000002) /* Write registers */
71 #define BITM_ROM_SYSCTRL_CGU_RTNSTAT (0x00000004) /* Update structure STAT field upon error or after a write operation */
72 #define BITM_ROM_SYSCTRL_CGU_CTL (0x00000010) /* Access CGU_CTL register */
73 #define BITM_ROM_SYSCTRL_CGU_STAT (0x00000020) /* Access CGU_STAT register */
74 #define BITM_ROM_SYSCTRL_CGU_DIV (0x00000040) /* Access CGU_DIV register */
75 #define BITM_ROM_SYSCTRL_CGU_CLKOUTSEL (0x00000080) /* Access CGU_CLKOUTSEL register */
76 #define BITM_ROM_SYSCTRL_CGU_AUTODIS (0x00000800) /* Disables auto handling of UPDT and ALGN fields */
77 #define BITM_ROM_SYSCTRL_DDR_READ (0x00001000) /* Reads the contents of the DDR registers and stores them into the structure */
78 #define BITM_ROM_SYSCTRL_DDR_WRITE (0x00002000) /* Writes the DDR registers from the structure, only really intented for wakeup functionality and not for full DDR configuration */
79 #define BITM_ROM_SYSCTRL_WUA_EN (0x00010000) /* Wakeup entry or exit opertation enable */
80 #define BITM_ROM_SYSCTRL_WUA_DPMWRITE (0x00020000) /* When set indicates a restore of the PLL and DDR is to be performed otherwise a save is required */
81 #define BITM_ROM_SYSCTRL_WUA_CGU (0x00040000) /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */
82 #define BITM_ROM_SYSCTRL_WUA_DDR (0x00080000) /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */
83 #define BITM_ROM_SYSCTRL_WUA_DDRDLLEN (0x00100000) /* Enables saving/restoring of the DDR DLLCTL register */
84 #define BITM_ROM_SYSCTRL_WUA_OVERRIDE (0x01000000)
85 #define BITM_ROM_SYSCTRL_CGU_LOCKINGEN (0x10000000) /* Unlocks the CGU_CTL register */
88 /* Structures for the syscontrol() function */
89 struct STRUCT_ROM_SYSCTRL {
93 uint32_t ulCGU_CLKOUTSEL;
95 uint32_t ulWUA_BootAddr;
105 uint32_t ulDDR_PADCTL;
106 uint32_t ulDDR_DLLCTL;
110 struct bfin_pm_data {
112 uint32_t resume_addr;
116 struct bfin_pm_data bf609_pm_data;
118 struct STRUCT_ROM_SYSCTRL configvalues;
119 uint32_t dactionflags;
121 #define FUNC_ROM_SYSCONTROL 0xC8000080
122 __attribute__((l1_data))
123 static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, struct STRUCT_ROM_SYSCTRL *settings, void *reserved) = (void *)FUNC_ROM_SYSCONTROL;
125 __attribute__((l1_text))
126 void bfin_cpu_suspend(void)
128 __asm__ __volatile__( \
135 __attribute__((l1_text))
136 void bf609_ddr_sr(void)
138 dmc_enter_self_refresh();
141 __attribute__((l1_text))
142 void bf609_ddr_sr_exit(void)
144 dmc_exit_self_refresh();
146 /* After wake up from deep sleep and exit DDR from self refress mode,
147 * should wait till CGU PLL is locked.
149 while (bfin_read32(CGU0_STAT) & CLKSALGN)
153 __attribute__((l1_text))
154 void bf609_resume_ccbuf(void)
156 bfin_write32(DPM0_CCBF_EN, 3);
157 bfin_write32(DPM0_CTL, 2);
159 while ((bfin_read32(DPM0_STAT) & 0xf) != 1);
162 __attribute__((l1_text))
163 void bfin_hibernate_syscontrol(void)
165 configvalues.ulWUA_Flags = (0xAD000000 | BITM_ROM_WUA_EN
166 | BITM_ROM_WUA_CGU | BITM_ROM_WUA_DDR | BITM_ROM_WUA_DDRDLLEN);
168 dactionflags = (BITM_ROM_SYSCTRL_WUA_EN
169 | BITM_ROM_SYSCTRL_WUA_DPMWRITE | BITM_ROM_SYSCTRL_WUA_CGU
170 | BITM_ROM_SYSCTRL_WUA_DDR | BITM_ROM_SYSCTRL_WUA_DDRDLLEN);
172 bfrom_SysControl(dactionflags, &configvalues, NULL);
174 bfin_write32(DPM0_RESTORE5, bfin_read32(DPM0_RESTORE5) | 4);
178 # define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
180 # define SIC_SYSIRQ(irq) ((irq) - IVG15)
182 asmlinkage void enter_deepsleep(void);
184 __attribute__((l1_text))
185 void bfin_deepsleep(unsigned long mask)
187 bfin_write32(DPM0_WAKE_EN, 0x10);
188 bfin_write32(DPM0_WAKE_POL, 0x10);
193 void bfin_hibernate(unsigned long mask)
195 bfin_write32(DPM0_WAKE_EN, 0x10);
196 bfin_write32(DPM0_WAKE_POL, 0x10);
197 bfin_write32(DPM0_PGCNTR, 0x0000FFFF);
198 bfin_write32(DPM0_HIB_DIS, 0xFFFF);
203 void bf609_cpu_pm_enter(suspend_state_t state)
206 unsigned long wakeup = 0;
207 unsigned long wakeup_pol = 0;
209 #ifdef CONFIG_PM_BFIN_WAKE_PA15
211 # if CONFIG_PM_BFIN_WAKE_PA15_POL
212 wakeup_pol |= PA15WE;
216 #ifdef CONFIG_PM_BFIN_WAKE_PB15
218 # if CONFIG_PM_BFIN_WAKE_PA15_POL
219 wakeup_pol |= PB15WE;
223 #ifdef CONFIG_PM_BFIN_WAKE_PC15
225 # if CONFIG_PM_BFIN_WAKE_PC15_POL
226 wakeup_pol |= PC15WE;
230 #ifdef CONFIG_PM_BFIN_WAKE_PD06
232 # if CONFIG_PM_BFIN_WAKE_PD06_POL
233 wakeup_pol |= PD06WE;
237 #ifdef CONFIG_PM_BFIN_WAKE_PE12
239 # if CONFIG_PM_BFIN_WAKE_PE12_POL
240 wakeup_pol |= PE12WE;
244 #ifdef CONFIG_PM_BFIN_WAKE_PG04
246 # if CONFIG_PM_BFIN_WAKE_PG04_POL
247 wakeup_pol |= PG04WE;
251 #ifdef CONFIG_PM_BFIN_WAKE_PG13
253 # if CONFIG_PM_BFIN_WAKE_PG13_POL
254 wakeup_pol |= PG13WE;
258 #ifdef CONFIG_PM_BFIN_WAKE_USB
260 # if CONFIG_PM_BFIN_WAKE_USB_POL
265 error = irq_set_irq_wake(255, 1);
267 printk(KERN_DEBUG "Unable to get irq wake\n");
268 error = irq_set_irq_wake(231, 1);
270 printk(KERN_DEBUG "Unable to get irq wake\n");
272 if (state == PM_SUSPEND_STANDBY)
273 bfin_deepsleep(wakeup);
275 bfin_hibernate(wakeup);
280 int bf609_cpu_pm_prepare(void)
285 void bf609_cpu_pm_finish(void)
290 static struct bfin_cpu_pm_fns bf609_cpu_pm = {
291 .enter = bf609_cpu_pm_enter,
292 .prepare = bf609_cpu_pm_prepare,
293 .finish = bf609_cpu_pm_finish,
296 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
297 static void smc_pm_syscore_suspend(void)
299 bf609_nor_flash_exit();
302 static void smc_pm_syscore_resume(void)
304 bf609_nor_flash_init();
307 static struct syscore_ops smc_pm_syscore_ops = {
308 .suspend = smc_pm_syscore_suspend,
309 .resume = smc_pm_syscore_resume,
313 static irqreturn_t test_isr(int irq, void *dev_id)
315 printk(KERN_DEBUG "gpio irq %d\n", irq);
319 static irqreturn_t dpm0_isr(int irq, void *dev_id)
321 bfin_write32(DPM0_WAKE_STAT, bfin_read32(DPM0_WAKE_STAT));
322 bfin_write32(CGU0_STAT, bfin_read32(CGU0_STAT));
327 static int __init bf609_init_pm(void)
332 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
333 register_syscore_ops(&smc_pm_syscore_ops);
336 #ifdef CONFIG_PM_BFIN_WAKE_PE12
337 irq = gpio_to_irq(GPIO_PE12);
340 printk(KERN_DEBUG "Unable to get irq number for GPIO %d, error %d\n",
344 error = request_irq(irq, test_isr, IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND, "gpiope12", NULL);
346 printk(KERN_DEBUG "Unable to get irq\n");
349 error = request_irq(IRQ_CGU_EVT, dpm0_isr, IRQF_NO_SUSPEND, "cgu0 event", NULL);
351 printk(KERN_DEBUG "Unable to get irq\n");
353 error = request_irq(IRQ_DPM, dpm0_isr, IRQF_NO_SUSPEND, "dpm0 event", NULL);
355 printk(KERN_DEBUG "Unable to get irq\n");
357 bfin_cpu_pm = &bf609_cpu_pm;
361 late_initcall(bf609_init_pm);