arch/blackfin/mach-bf533/dma.c

   1 /*
   2  * simple DMA Implementation for Blackfin
   3  *
   4  * Copyright 2007-2009 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <linux/module.h>
  10
  11 #include <asm/blackfin.h>
  12 #include <asm/dma.h>
  13
  14 struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
  15         (struct dma_register *) DMA0_NEXT_DESC_PTR,
  16         (struct dma_register *) DMA1_NEXT_DESC_PTR,
  17         (struct dma_register *) DMA2_NEXT_DESC_PTR,
  18         (struct dma_register *) DMA3_NEXT_DESC_PTR,
  19         (struct dma_register *) DMA4_NEXT_DESC_PTR,
  20         (struct dma_register *) DMA5_NEXT_DESC_PTR,
  21         (struct dma_register *) DMA6_NEXT_DESC_PTR,
  22         (struct dma_register *) DMA7_NEXT_DESC_PTR,
  23         (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
  24         (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
  25         (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
  26         (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
  27 };
  28 EXPORT_SYMBOL(dma_io_base_addr);
  29
  30 int channel2irq(unsigned int channel)
  31 {
  32         int ret_irq = -1;
  33
  34         switch (channel) {
  35         case CH_PPI:
  36                 ret_irq = IRQ_PPI;
  37                 break;
  38
  39         case CH_SPORT0_RX:
  40                 ret_irq = IRQ_SPORT0_RX;
  41                 break;
  42
  43         case CH_SPORT0_TX:
  44                 ret_irq = IRQ_SPORT0_TX;
  45                 break;
  46
  47         case CH_SPORT1_RX:
  48                 ret_irq = IRQ_SPORT1_RX;
  49                 break;
  50
  51         case CH_SPORT1_TX:
  52                 ret_irq = IRQ_SPORT1_TX;
  53                 break;
  54
  55         case CH_SPI:
  56                 ret_irq = IRQ_SPI;
  57                 break;
  58
  59         case CH_UART0_RX:
  60                 ret_irq = IRQ_UART0_RX;
  61                 break;
  62
  63         case CH_UART0_TX:
  64                 ret_irq = IRQ_UART0_TX;
  65                 break;
  66
  67         case CH_MEM_STREAM0_SRC:
  68         case CH_MEM_STREAM0_DEST:
  69                 ret_irq = IRQ_MEM_DMA0;
  70                 break;
  71
  72         case CH_MEM_STREAM1_SRC:
  73         case CH_MEM_STREAM1_DEST:
  74                 ret_irq = IRQ_MEM_DMA1;
  75                 break;
  76         }
  77         return ret_irq;
  78 }