2 * Based on arm clockevents implementation and old bfin time tick.
4 * Copyright 2008-2009 Analog Devics Inc.
8 * Licensed under the GPL-2
11 #include <linux/module.h>
12 #include <linux/profile.h>
13 #include <linux/interrupt.h>
14 #include <linux/time.h>
15 #include <linux/timex.h>
16 #include <linux/irq.h>
17 #include <linux/clocksource.h>
18 #include <linux/clockchips.h>
19 #include <linux/cpufreq.h>
21 #include <asm/blackfin.h>
23 #include <asm/gptimers.h>
26 /* Accelerators for sched_clock()
27 * convert from cycles(64bits) => nanoseconds (64bits)
29 * ns = cycles / (freq / ns_per_sec)
30 * ns = cycles * (ns_per_sec / freq)
31 * ns = cycles * (10^9 / (cpu_khz * 10^3))
32 * ns = cycles * (10^6 / cpu_khz)
34 * Then we use scaling math (suggested by george@mvista.com) to get:
35 * ns = cycles * (10^6 * SC / cpu_khz) / SC
36 * ns = cycles * cyc2ns_scale / SC
38 * And since SC is a constant power of two, we can convert the div
41 * We can use khz divisor instead of mhz to keep a better precision, since
42 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
43 * (mathieu.desnoyers@polymtl.ca)
45 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
48 #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
50 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
52 static notrace cycle_t bfin_read_cycles(struct clocksource *cs)
54 #ifdef CONFIG_CPU_FREQ
55 return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod);
61 static struct clocksource bfin_cs_cycles = {
62 .name = "bfin_cs_cycles",
64 .read = bfin_read_cycles,
65 .mask = CLOCKSOURCE_MASK(64),
66 .shift = CYC2NS_SCALE_FACTOR,
67 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
70 static inline unsigned long long bfin_cs_cycles_sched_clock(void)
72 return clocksource_cyc2ns(bfin_read_cycles(&bfin_cs_cycles),
73 bfin_cs_cycles.mult, bfin_cs_cycles.shift);
76 static int __init bfin_cs_cycles_init(void)
78 bfin_cs_cycles.mult = \
79 clocksource_hz2mult(get_cclk(), bfin_cs_cycles.shift);
81 if (clocksource_register(&bfin_cs_cycles))
82 panic("failed to register clocksource");
87 # define bfin_cs_cycles_init()
90 #ifdef CONFIG_GPTMR0_CLOCKSOURCE
92 void __init setup_gptimer0(void)
94 disable_gptimers(TIMER0bit);
96 set_gptimer_config(TIMER0_id, \
97 TIMER_OUT_DIS | TIMER_PERIOD_CNT | TIMER_MODE_PWM);
98 set_gptimer_period(TIMER0_id, -1);
99 set_gptimer_pwidth(TIMER0_id, -2);
101 enable_gptimers(TIMER0bit);
104 static cycle_t bfin_read_gptimer0(struct clocksource *cs)
106 return bfin_read_TIMER0_COUNTER();
109 static struct clocksource bfin_cs_gptimer0 = {
110 .name = "bfin_cs_gptimer0",
112 .read = bfin_read_gptimer0,
113 .mask = CLOCKSOURCE_MASK(32),
114 .shift = CYC2NS_SCALE_FACTOR,
115 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
118 static inline unsigned long long bfin_cs_gptimer0_sched_clock(void)
120 return clocksource_cyc2ns(bfin_read_TIMER0_COUNTER(),
121 bfin_cs_gptimer0.mult, bfin_cs_gptimer0.shift);
124 static int __init bfin_cs_gptimer0_init(void)
128 bfin_cs_gptimer0.mult = \
129 clocksource_hz2mult(get_sclk(), bfin_cs_gptimer0.shift);
131 if (clocksource_register(&bfin_cs_gptimer0))
132 panic("failed to register clocksource");
137 # define bfin_cs_gptimer0_init()
140 #if defined(CONFIG_GPTMR0_CLOCKSOURCE) || defined(CONFIG_CYCLES_CLOCKSOURCE)
141 /* prefer to use cycles since it has higher rating */
142 notrace unsigned long long sched_clock(void)
144 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
145 return bfin_cs_cycles_sched_clock();
147 return bfin_cs_gptimer0_sched_clock();
152 #if defined(CONFIG_TICKSOURCE_GPTMR0)
153 static int bfin_gptmr0_set_next_event(unsigned long cycles,
154 struct clock_event_device *evt)
156 disable_gptimers(TIMER0bit);
158 /* it starts counting three SCLK cycles after the TIMENx bit is set */
159 set_gptimer_pwidth(TIMER0_id, cycles - 3);
160 enable_gptimers(TIMER0bit);
164 static void bfin_gptmr0_set_mode(enum clock_event_mode mode,
165 struct clock_event_device *evt)
168 case CLOCK_EVT_MODE_PERIODIC: {
169 set_gptimer_config(TIMER0_id, \
170 TIMER_OUT_DIS | TIMER_IRQ_ENA | \
171 TIMER_PERIOD_CNT | TIMER_MODE_PWM);
172 set_gptimer_period(TIMER0_id, get_sclk() / HZ);
173 set_gptimer_pwidth(TIMER0_id, get_sclk() / HZ - 1);
174 enable_gptimers(TIMER0bit);
177 case CLOCK_EVT_MODE_ONESHOT:
178 disable_gptimers(TIMER0bit);
179 set_gptimer_config(TIMER0_id, \
180 TIMER_OUT_DIS | TIMER_IRQ_ENA | TIMER_MODE_PWM);
181 set_gptimer_period(TIMER0_id, 0);
183 case CLOCK_EVT_MODE_UNUSED:
184 case CLOCK_EVT_MODE_SHUTDOWN:
185 disable_gptimers(TIMER0bit);
187 case CLOCK_EVT_MODE_RESUME:
192 static void bfin_gptmr0_ack(void)
194 set_gptimer_status(TIMER_GROUP1, TIMER_STATUS_TIMIL0);
197 static void __init bfin_gptmr0_init(void)
199 disable_gptimers(TIMER0bit);
202 #ifdef CONFIG_CORE_TIMER_IRQ_L1
203 __attribute__((l1_text))
205 irqreturn_t bfin_gptmr0_interrupt(int irq, void *dev_id)
207 struct clock_event_device *evt = dev_id;
210 * We want to ACK before we handle so that we can handle smaller timer
211 * intervals. This way if the timer expires again while we're handling
212 * things, we're more likely to see that 2nd int rather than swallowing
213 * it by ACKing the int at the end of this handler.
216 evt->event_handler(evt);
220 static struct irqaction gptmr0_irq = {
221 .name = "Blackfin GPTimer0",
222 .flags = IRQF_DISABLED | IRQF_TIMER | \
223 IRQF_IRQPOLL | IRQF_PERCPU,
224 .handler = bfin_gptmr0_interrupt,
227 static struct clock_event_device clockevent_gptmr0 = {
228 .name = "bfin_gptimer0",
232 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
233 .set_next_event = bfin_gptmr0_set_next_event,
234 .set_mode = bfin_gptmr0_set_mode,
237 static void __init bfin_gptmr0_clockevent_init(struct clock_event_device *evt)
239 unsigned long clock_tick;
241 clock_tick = get_sclk();
242 evt->mult = div_sc(clock_tick, NSEC_PER_SEC, evt->shift);
243 evt->max_delta_ns = clockevent_delta2ns(-1, evt);
244 evt->min_delta_ns = clockevent_delta2ns(100, evt);
246 evt->cpumask = cpumask_of(0);
248 clockevents_register_device(evt);
250 #endif /* CONFIG_TICKSOURCE_GPTMR0 */
252 #if defined(CONFIG_TICKSOURCE_CORETMR)
253 /* per-cpu local core timer */
254 static DEFINE_PER_CPU(struct clock_event_device, coretmr_events);
256 static int bfin_coretmr_set_next_event(unsigned long cycles,
257 struct clock_event_device *evt)
259 bfin_write_TCNTL(TMPWR);
261 bfin_write_TCOUNT(cycles);
263 bfin_write_TCNTL(TMPWR | TMREN);
267 static void bfin_coretmr_set_mode(enum clock_event_mode mode,
268 struct clock_event_device *evt)
271 case CLOCK_EVT_MODE_PERIODIC: {
272 unsigned long tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1);
273 bfin_write_TCNTL(TMPWR);
275 bfin_write_TSCALE(TIME_SCALE - 1);
276 bfin_write_TPERIOD(tcount);
277 bfin_write_TCOUNT(tcount);
279 bfin_write_TCNTL(TMPWR | TMREN | TAUTORLD);
282 case CLOCK_EVT_MODE_ONESHOT:
283 bfin_write_TCNTL(TMPWR);
285 bfin_write_TSCALE(TIME_SCALE - 1);
286 bfin_write_TPERIOD(0);
287 bfin_write_TCOUNT(0);
289 case CLOCK_EVT_MODE_UNUSED:
290 case CLOCK_EVT_MODE_SHUTDOWN:
294 case CLOCK_EVT_MODE_RESUME:
299 void bfin_coretmr_init(void)
301 /* power up the timer, but don't enable it just yet */
302 bfin_write_TCNTL(TMPWR);
305 /* the TSCALE prescaler counter. */
306 bfin_write_TSCALE(TIME_SCALE - 1);
307 bfin_write_TPERIOD(0);
308 bfin_write_TCOUNT(0);
313 #ifdef CONFIG_CORE_TIMER_IRQ_L1
314 __attribute__((l1_text))
316 irqreturn_t bfin_coretmr_interrupt(int irq, void *dev_id)
318 int cpu = smp_processor_id();
319 struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
322 evt->event_handler(evt);
324 touch_nmi_watchdog();
329 static struct irqaction coretmr_irq = {
330 .name = "Blackfin CoreTimer",
331 .flags = IRQF_DISABLED | IRQF_TIMER | \
332 IRQF_IRQPOLL | IRQF_PERCPU,
333 .handler = bfin_coretmr_interrupt,
336 void bfin_coretmr_clockevent_init(void)
338 unsigned long clock_tick;
339 unsigned int cpu = smp_processor_id();
340 struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
342 evt->name = "bfin_core_timer";
346 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
347 evt->set_next_event = bfin_coretmr_set_next_event;
348 evt->set_mode = bfin_coretmr_set_mode;
350 clock_tick = get_cclk() / TIME_SCALE;
351 evt->mult = div_sc(clock_tick, NSEC_PER_SEC, evt->shift);
352 evt->max_delta_ns = clockevent_delta2ns(-1, evt);
353 evt->min_delta_ns = clockevent_delta2ns(100, evt);
355 evt->cpumask = cpumask_of(cpu);
357 clockevents_register_device(evt);
359 #endif /* CONFIG_TICKSOURCE_CORETMR */
362 void read_persistent_clock(struct timespec *ts)
364 time_t secs_since_1970 = (365 * 37 + 9) * 24 * 60 * 60; /* 1 Jan 2007 */
365 ts->tv_sec = secs_since_1970;
369 void __init time_init(void)
372 #ifdef CONFIG_RTC_DRV_BFIN
373 /* [#2663] hack to filter junk RTC values that would cause
374 * userspace to have to deal with time values greater than
375 * 2^31 seconds (which uClibc cannot cope with yet)
377 if ((bfin_read_RTC_STAT() & 0xC0000000) == 0xC0000000) {
378 printk(KERN_NOTICE "bfin-rtc: invalid date; resetting\n");
379 bfin_write_RTC_STAT(0);
383 bfin_cs_cycles_init();
384 bfin_cs_gptimer0_init();
386 #if defined(CONFIG_TICKSOURCE_CORETMR)
388 setup_irq(IRQ_CORETMR, &coretmr_irq);
389 bfin_coretmr_clockevent_init();
392 #if defined(CONFIG_TICKSOURCE_GPTMR0)
394 setup_irq(IRQ_TIMER0, &gptmr0_irq);
395 gptmr0_irq.dev_id = &clockevent_gptmr0;
396 bfin_gptmr0_clockevent_init(&clockevent_gptmr0);
399 #if !defined(CONFIG_TICKSOURCE_CORETMR) && !defined(CONFIG_TICKSOURCE_GPTMR0)
400 # error at least one clock event device is required