2 * bfin_sport.h - interface to Blackfin SPORTs
4 * Copyright 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
9 #ifndef __BFIN_SPORT_H__
10 #define __BFIN_SPORT_H__
12 /* Sport mode: it can be set to TDM, i2s or others */
17 /* Data format, normal, a-law or u-law */
18 #define NORM_FORMAT 0x0
19 #define ALAW_FORMAT 0x2
20 #define ULAW_FORMAT 0x3
22 /* Function driver which use sport must initialize the structure */
24 /* TDM (multichannels), I2S or other mode */
27 /* if TDM mode is selected, channels must be set */
28 int channels; /* Must be in 8 units */
29 unsigned int frame_delay:4; /* Delay between frame sync pulse and first bit */
32 unsigned int right_first:1; /* Right stereo channel first */
34 /* In mormal mode, the following item need to be set */
35 unsigned int lsb_first:1; /* order of transmit or receive data */
36 unsigned int fsync:1; /* Frame sync required */
37 unsigned int data_indep:1; /* data independent frame sync generated */
38 unsigned int act_low:1; /* Active low TFS */
39 unsigned int late_fsync:1; /* Late frame sync */
41 unsigned int sec_en:1; /* Secondary side enabled */
43 /* Choose clock source */
44 unsigned int int_clk:1; /* Internal or external clock */
46 /* If external clock is used, the following fields are ignored */
50 unsigned int data_format:2; /* Normal, u-law or a-law */
52 int word_len; /* How length of the word in bits, 3-32 bits */
56 /* Userspace interface */
57 #define SPORT_IOC_MAGIC 'P'
58 #define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config)
62 #include <linux/types.h>
65 * All Blackfin system MMRs are padded to 32bits even if the register
66 * itself is only 16bits. So use a helper macro to streamline this.
68 #define __BFP(m) u16 m; u16 __pad_##m
69 struct sport_register {
80 u32 rx32; /* use the anomaly wrapper below */
103 #define bfin_read_sport_rx32(base) \
105 struct sport_register *__mmrs = (void *)base; \
107 unsigned long flags; \
108 if (ANOMALY_05000473) \
109 local_irq_save(flags); \
110 __ret = __mmrs->rx32; \
111 if (ANOMALY_05000473) \
112 local_irq_restore(flags); \
118 /* Workaround defBF*.h SPORT MMRs till they get cleansed */
124 /* SPORT_TCR1 Masks */
125 #define TSPEN 0x0001 /* TX enable */
126 #define ITCLK 0x0002 /* Internal TX Clock Select */
127 #define TDTYPE 0x000C /* TX Data Formatting Select */
128 #define DTYPE_NORM 0x0000 /* Data Format Normal */
129 #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
130 #define DTYPE_ALAW 0x000C /* Compand Using A-Law */
131 #define TLSBIT 0x0010 /* TX Bit Order */
132 #define ITFS 0x0200 /* Internal TX Frame Sync Select */
133 #define TFSR 0x0400 /* TX Frame Sync Required Select */
134 #define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
135 #define LTFS 0x1000 /* Low TX Frame Sync Select */
136 #define LATFS 0x2000 /* Late TX Frame Sync Select */
137 #define TCKFE 0x4000 /* TX Clock Falling Edge Select */
139 /* SPORT_TCR2 Masks */
140 #define SLEN 0x001F /* SPORT TX Word Length (2 - 31) */
141 #define DP_SLEN(x) BFIN_DEPOSIT(SLEN, x)
142 #define EX_SLEN(x) BFIN_EXTRACT(SLEN, x)
143 #define TXSE 0x0100 /* TX Secondary Enable */
144 #define TSFSE 0x0200 /* TX Stereo Frame Sync Enable */
145 #define TRFST 0x0400 /* TX Right-First Data Order */
147 /* SPORT_RCR1 Masks */
148 #define RSPEN 0x0001 /* RX enable */
149 #define IRCLK 0x0002 /* Internal RX Clock Select */
150 #define RDTYPE 0x000C /* RX Data Formatting Select */
151 /* DTYPE_* defined above */
152 #define RLSBIT 0x0010 /* RX Bit Order */
153 #define IRFS 0x0200 /* Internal RX Frame Sync Select */
154 #define RFSR 0x0400 /* RX Frame Sync Required Select */
155 #define LRFS 0x1000 /* Low RX Frame Sync Select */
156 #define LARFS 0x2000 /* Late RX Frame Sync Select */
157 #define RCKFE 0x4000 /* RX Clock Falling Edge Select */
159 /* SPORT_RCR2 Masks */
160 /* SLEN defined above */
161 #define RXSE 0x0100 /* RX Secondary Enable */
162 #define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
163 #define RRFST 0x0400 /* Right-First Data Order */
165 /* SPORT_STAT Masks */
166 #define RXNE 0x0001 /* RX FIFO Not Empty Status */
167 #define RUVF 0x0002 /* RX Underflow Status */
168 #define ROVF 0x0004 /* RX Overflow Status */
169 #define TXF 0x0008 /* TX FIFO Full Status */
170 #define TUVF 0x0010 /* TX Underflow Status */
171 #define TOVF 0x0020 /* TX Overflow Status */
172 #define TXHRE 0x0040 /* TX Hold Register Empty */
174 /* SPORT_MCMC1 Masks */
175 #define SP_WOFF 0x03FF /* Multichannel Window Offset Field */
176 #define DP_SP_WOFF(x) BFIN_DEPOSIT(SP_WOFF, x)
177 #define EX_SP_WOFF(x) BFIN_EXTRACT(SP_WOFF, x)
178 #define SP_WSIZE 0xF000 /* Multichannel Window Size Field */
179 #define DP_SP_WSIZE(x) BFIN_DEPOSIT(SP_WSIZE, x)
180 #define EX_SP_WSIZE(x) BFIN_EXTRACT(SP_WSIZE, x)
182 /* SPORT_MCMC2 Masks */
183 #define MCCRM 0x0003 /* Multichannel Clock Recovery Mode */
184 #define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
185 #define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
186 #define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
187 #define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
188 #define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
189 #define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
190 #define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
191 #define MFD 0xF000 /* Multichannel Frame Delay */
192 #define DP_MFD(x) BFIN_DEPOSIT(MFD, x)
193 #define EX_MFD(x) BFIN_EXTRACT(MFD, x)