arch/blackfin/cpu/initcode.c

   1 /*
   2  * initcode.c - Initialize the processor.  This is usually entails things
   3  * like external memory, voltage regulators, etc...  Note that this file
   4  * cannot make any function calls as it may be executed all by itself by
   5  * the Blackfin's bootrom in LDR format.
   6  *
   7  * Copyright (c) 2004-2011 Analog Devices Inc.
   8  *
   9  * Licensed under the GPL-2 or later.
  10  */
  11
  12 #define BFIN_IN_INITCODE
  13
  14 #include <config.h>
  15 #include <asm/blackfin.h>
  16 #include <asm/mach-common/bits/watchdog.h>
  17 #include <asm/mach-common/bits/bootrom.h>
  18 #include <asm/mach-common/bits/core.h>
  19 #include <asm/serial.h>
  20
  21 #define BUG() while (1) asm volatile("emuexcpt;");
  22
  23 #ifndef __ADSPBF60x__
  24 #include <asm/mach-common/bits/ebiu.h>
  25 #include <asm/mach-common/bits/pll.h>
  26 #else /* __ADSPBF60x__ */
  27 #include <asm/mach-common/bits/cgu.h>
  28
  29 #define CONFIG_BFIN_GET_DCLK_M \
  30         ((CONFIG_CLKIN_HZ*CONFIG_VCO_MULT)/(CONFIG_DCLK_DIV*1000000))
  31
  32 #ifndef CONFIG_DMC_DDRCFG
  33 #if ((CONFIG_BFIN_GET_DCLK_M != 125) && \
  34         (CONFIG_BFIN_GET_DCLK_M != 133) && \
  35         (CONFIG_BFIN_GET_DCLK_M != 150) && \
  36         (CONFIG_BFIN_GET_DCLK_M != 166) && \
  37         (CONFIG_BFIN_GET_DCLK_M != 200) && \
  38         (CONFIG_BFIN_GET_DCLK_M != 225) && \
  39         (CONFIG_BFIN_GET_DCLK_M != 250))
  40 #error "DDR2 CLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
  41 #endif
  42 #endif
  43
  44 /* DMC control bits */
  45 #define SRREQ                   0x8
  46
  47 /* DMC status bits */
  48 #define IDLE                    0x1
  49 #define MEMINITDONE             0x4
  50 #define SRACK                   0x8
  51 #define PDACK                   0x10
  52 #define DPDACK                  0x20
  53 #define DLLCALDONE              0x2000
  54 #define PENDREF                 0xF0000
  55 #define PHYRDPHASE              0xF00000
  56 #define PHYRDPHASE_OFFSET       20
  57
  58 /* DMC DLL control bits */
  59 #define DLLCALRDCNT             0xFF
  60 #define DATACYC_OFFSET          8
  61
  62 struct ddr_config {
  63         u32 ddr_clk;
  64         u32 dmc_ddrctl;
  65         u32 dmc_ddrcfg;
  66         u32 dmc_ddrtr0;
  67         u32 dmc_ddrtr1;
  68         u32 dmc_ddrtr2;
  69         u32 dmc_ddrmr;
  70         u32 dmc_ddrmr1;
  71 };
  72
  73 static struct ddr_config ddr_config_table[] = {
  74         [0] = {
  75                 .ddr_clk    = 125,      /* 125MHz */
  76                 .dmc_ddrctl = 0x00000904,
  77                 .dmc_ddrcfg = 0x00000422,
  78                 .dmc_ddrtr0 = 0x20705212,
  79                 .dmc_ddrtr1 = 0x201003CF,
  80                 .dmc_ddrtr2 = 0x00320107,
  81                 .dmc_ddrmr  = 0x00000422,
  82                 .dmc_ddrmr1 = 0x4,
  83         },
  84         [1] = {
  85                 .ddr_clk    = 133,      /* 133MHz */
  86                 .dmc_ddrctl = 0x00000904,
  87                 .dmc_ddrcfg = 0x00000422,
  88                 .dmc_ddrtr0 = 0x20806313,
  89                 .dmc_ddrtr1 = 0x2013040D,
  90                 .dmc_ddrtr2 = 0x00320108,
  91                 .dmc_ddrmr  = 0x00000632,
  92                 .dmc_ddrmr1 = 0x4,
  93         },
  94         [2] = {
  95                 .ddr_clk    = 150,      /* 150MHz */
  96                 .dmc_ddrctl = 0x00000904,
  97                 .dmc_ddrcfg = 0x00000422,
  98                 .dmc_ddrtr0 = 0x20A07323,
  99                 .dmc_ddrtr1 = 0x20160492,
 100                 .dmc_ddrtr2 = 0x00320209,
 101                 .dmc_ddrmr  = 0x00000632,
 102                 .dmc_ddrmr1 = 0x4,
 103         },
 104         [3] = {
 105                 .ddr_clk    = 166,      /* 166MHz */
 106                 .dmc_ddrctl = 0x00000904,
 107                 .dmc_ddrcfg = 0x00000422,
 108                 .dmc_ddrtr0 = 0x20A07323,
 109                 .dmc_ddrtr1 = 0x2016050E,
 110                 .dmc_ddrtr2 = 0x00320209,
 111                 .dmc_ddrmr  = 0x00000632,
 112                 .dmc_ddrmr1 = 0x4,
 113         },
 114         [4] = {
 115                 .ddr_clk    = 200,      /* 200MHz */
 116                 .dmc_ddrctl = 0x00000904,
 117                 .dmc_ddrcfg = 0x00000422,
 118                 .dmc_ddrtr0 = 0x20a07323,
 119                 .dmc_ddrtr1 = 0x2016050f,
 120                 .dmc_ddrtr2 = 0x00320509,
 121                 .dmc_ddrmr  = 0x00000632,
 122                 .dmc_ddrmr1 = 0x4,
 123         },
 124         [5] = {
 125                 .ddr_clk    = 225,      /* 225MHz */
 126                 .dmc_ddrctl = 0x00000904,
 127                 .dmc_ddrcfg = 0x00000422,
 128                 .dmc_ddrtr0 = 0x20E0A424,
 129                 .dmc_ddrtr1 = 0x302006DB,
 130                 .dmc_ddrtr2 = 0x0032020D,
 131                 .dmc_ddrmr  = 0x00000842,
 132                 .dmc_ddrmr1 = 0x4,
 133         },
 134         [6] = {
 135                 .ddr_clk    = 250,      /* 250MHz */
 136                 .dmc_ddrctl = 0x00000904,
 137                 .dmc_ddrcfg = 0x00000422,
 138                 .dmc_ddrtr0 = 0x20E0A424,
 139                 .dmc_ddrtr1 = 0x3020079E,
 140                 .dmc_ddrtr2 = 0x0032050D,
 141                 .dmc_ddrmr  = 0x00000842,
 142                 .dmc_ddrmr1 = 0x4,
 143         },
 144 };
 145 #endif /* __ADSPBF60x__ */
 146
 147 __attribute__((always_inline))
 148 static inline void serial_init(void)
 149 {
 150         uint32_t uart_base = UART_BASE;
 151
 152 #if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
 153 # ifdef BFIN_BOOT_UART_USE_RTS
 154 #  define BFIN_UART_USE_RTS 1
 155 # else
 156 #  define BFIN_UART_USE_RTS 0
 157 # endif
 158         if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
 159                 size_t i;
 160
 161                 /* force RTS rather than relying on auto RTS */
 162 #if BFIN_UART_HW_VER < 4
 163                 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL);
 164 #else
 165                 bfin_write32(&pUART->control, bfin_read32(&pUART->control) |
 166                                 FCPOL);
 167 #endif
 168
 169                 /* Wait for the line to clear up.  We cannot rely on UART
 170                  * registers as none of them reflect the status of the RSR.
 171                  * Instead, we'll sleep for ~10 bit times at 9600 baud.
 172                  * We can precalc things here by assuming boot values for
 173                  * PLL rather than loading registers and calculating.
 174                  *      baud    = SCLK / (16 ^ (1 - EDBO) * Divisor)
 175                  *      EDB0    = 0
 176                  *      Divisor = (SCLK / baud) / 16
 177                  *      SCLK    = baud * 16 * Divisor
 178                  *      SCLK    = (0x14 * CONFIG_CLKIN_HZ) / 5
 179                  *      CCLK    = (16 * Divisor * 5) * (9600 / 10)
 180                  * In reality, this will probably be just about 1 second delay,
 181                  * so assuming 9600 baud is OK (both as a very low and too high
 182                  * speed as this will buffer things enough).
 183                  */
 184 #define _NUMBITS (10)                                   /* how many bits to delay */
 185 #define _LOWBAUD (9600)                                 /* low baud rate */
 186 #define _SCLK    ((0x14 * CONFIG_CLKIN_HZ) / 5)         /* SCLK based on PLL */
 187 #define _DIVISOR ((_SCLK / _LOWBAUD) / 16)              /* UART DLL/DLH */
 188 #define _NUMINS  (3)                                    /* how many instructions in loop */
 189 #define _CCLK    (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS)
 190                 i = _CCLK;
 191                 while (i--)
 192                         asm volatile("" : : : "memory");
 193         }
 194 #endif
 195
 196 #if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS
 197         if (BFIN_DEBUG_EARLY_SERIAL) {
 198                 serial_early_init(uart_base);
 199                 serial_early_set_baud(uart_base, CONFIG_BAUDRATE);
 200         }
 201 #endif
 202 }
 203
 204 __attribute__((always_inline))
 205 static inline void serial_deinit(void)
 206 {
 207 #if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
 208         uint32_t uart_base = UART_BASE;
 209
 210         if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
 211                 /* clear forced RTS rather than relying on auto RTS */
 212 #if BFIN_UART_HW_VER < 4
 213                 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL);
 214 #else
 215                 bfin_write32(&pUART->control, bfin_read32(&pUART->control) &
 216                                 ~FCPOL);
 217 #endif
 218         }
 219 #endif
 220 }
 221
 222 __attribute__((always_inline))
 223 static inline void serial_putc(char c)
 224 {
 225         uint32_t uart_base = UART_BASE;
 226
 227         if (!BFIN_DEBUG_EARLY_SERIAL)
 228                 return;
 229
 230         if (c == '\n')
 231                 serial_putc('\r');
 232
 233         bfin_write(&pUART->thr, c);
 234
 235         while (!(_lsr_read(pUART) & TEMT))
 236                 continue;
 237 }
 238
 239 #include "initcode.h"
 240
 241 __attribute__((always_inline)) static inline void
 242 program_nmi_handler(void)
 243 {
 244         u32 tmp1, tmp2;
 245
 246         /* Older bootroms don't create a dummy NMI handler,
 247          * so make one ourselves ASAP in case it fires.
 248          */
 249         if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS && !ANOMALY_05000219)
 250                 return;
 251
 252         asm volatile (
 253                 "%0 = RETS;" /* Save current RETS */
 254                 "CALL 1f;"   /* Figure out current PC */
 255                 "RTN;"       /* The simple NMI handler */
 256                 "1:"
 257                 "%1 = RETS;" /* Load addr of NMI handler */
 258                 "RETS = %0;" /* Restore RETS */
 259                 "[%2] = %1;" /* Write NMI handler */
 260                 : "=d"(tmp1), "=d"(tmp2)
 261                 : "ab"(EVT2)
 262         );
 263 }
 264
 265 /* Max SCLK can be 133MHz ... dividing that by (2*4) gives
 266  * us a freq of 16MHz for SPI which should generally be
 267  * slow enough for the slow reads the bootrom uses.
 268  */
 269 #if !defined(CONFIG_SPI_FLASH_SLOW_READ) && \
 270     ((defined(__ADSPBF52x__) && __SILICON_REVISION__ >= 2) || \
 271      (defined(__ADSPBF54x__) && __SILICON_REVISION__ >= 1))
 272 # define BOOTROM_SUPPORTS_SPI_FAST_READ 1
 273 #else
 274 # define BOOTROM_SUPPORTS_SPI_FAST_READ 0
 275 #endif
 276 #ifndef CONFIG_SPI_BAUD_INITBLOCK
 277 # define CONFIG_SPI_BAUD_INITBLOCK (BOOTROM_SUPPORTS_SPI_FAST_READ ? 2 : 4)
 278 #endif
 279 #ifdef SPI0_BAUD
 280 # define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD
 281 #endif
 282
 283 #ifdef __ADSPBF60x__
 284
 285 #ifndef CONFIG_CGU_CTL_VAL
 286 # define CONFIG_CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CONFIG_CLKIN_HALF)
 287 #endif
 288
 289 #ifndef CONFIG_CGU_DIV_VAL
 290 # define CONFIG_CGU_DIV_VAL \
 291         ((CONFIG_CCLK_DIV   << CSEL_P)   | \
 292          (CONFIG_SCLK0_DIV  << S0SEL_P)  | \
 293          (CONFIG_SCLK_DIV << SYSSEL_P) | \
 294          (CONFIG_SCLK1_DIV  << S1SEL_P)  | \
 295          (CONFIG_DCLK_DIV   << DSEL_P)   | \
 296          (CONFIG_OCLK_DIV   << OSEL_P))
 297 #endif
 298
 299 #else /* __ADSPBF60x__ */
 300
 301 /* PLL_DIV defines */
 302 #ifndef CONFIG_PLL_DIV_VAL
 303 # if (CONFIG_CCLK_DIV == 1)
 304 #  define CONFIG_CCLK_ACT_DIV CCLK_DIV1
 305 # elif (CONFIG_CCLK_DIV == 2)
 306 #  define CONFIG_CCLK_ACT_DIV CCLK_DIV2
 307 # elif (CONFIG_CCLK_DIV == 4)
 308 #  define CONFIG_CCLK_ACT_DIV CCLK_DIV4
 309 # elif (CONFIG_CCLK_DIV == 8)
 310 #  define CONFIG_CCLK_ACT_DIV CCLK_DIV8
 311 # else
 312 #  define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
 313 # endif
 314 # define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV)
 315 #endif
 316
 317 #ifndef CONFIG_PLL_LOCKCNT_VAL
 318 # define CONFIG_PLL_LOCKCNT_VAL 0x0300
 319 #endif
 320
 321 #ifndef CONFIG_PLL_CTL_VAL
 322 # define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF)
 323 #endif
 324
 325 /* Make sure our voltage value is sane so we don't blow up! */
 326 #ifndef CONFIG_VR_CTL_VAL
 327 # define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
 328 # if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__)
 329 #  define CCLK_VLEV_120 400000000
 330 #  define CCLK_VLEV_125 533000000
 331 # elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
 332 #  define CCLK_VLEV_120 401000000
 333 #  define CCLK_VLEV_125 401000000
 334 # elif defined(__ADSPBF561__)
 335 #  define CCLK_VLEV_120 300000000
 336 #  define CCLK_VLEV_125 501000000
 337 # endif
 338 # if BFIN_CCLK < CCLK_VLEV_120
 339 #  define CONFIG_VR_CTL_VLEV VLEV_120
 340 # elif BFIN_CCLK < CCLK_VLEV_125
 341 #  define CONFIG_VR_CTL_VLEV VLEV_125
 342 # else
 343 #  define CONFIG_VR_CTL_VLEV VLEV_130
 344 # endif
 345 # if defined(__ADSPBF52x__)     /* TBD; use default */
 346 #  undef CONFIG_VR_CTL_VLEV
 347 #  define CONFIG_VR_CTL_VLEV VLEV_110
 348 # elif defined(__ADSPBF54x__)   /* TBD; use default */
 349 #  undef CONFIG_VR_CTL_VLEV
 350 #  define CONFIG_VR_CTL_VLEV VLEV_120
 351 # elif defined(__ADSPBF538__) || defined(__ADSPBF539__) /* TBD; use default */
 352 #  undef CONFIG_VR_CTL_VLEV
 353 #  define CONFIG_VR_CTL_VLEV VLEV_125
 354 # endif
 355
 356 # ifdef CONFIG_BFIN_MAC
 357 #  define CONFIG_VR_CTL_CLKBUF CLKBUFOE
 358 # else
 359 #  define CONFIG_VR_CTL_CLKBUF 0
 360 # endif
 361
 362 # if defined(__ADSPBF52x__)
 363 #  define CONFIG_VR_CTL_FREQ FREQ_1000
 364 # else
 365 #  define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000)
 366 # endif
 367
 368 # define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
 369 #endif
 370
 371 /* some parts do not have an on-chip voltage regulator */
 372 #if defined(__ADSPBF51x__)
 373 # define CONFIG_HAS_VR 0
 374 # undef CONFIG_VR_CTL_VAL
 375 # define CONFIG_VR_CTL_VAL 0
 376 #else
 377 # define CONFIG_HAS_VR 1
 378 #endif
 379
 380 #if CONFIG_MEM_SIZE
 381 #ifndef EBIU_RSTCTL
 382 /* Blackfin with SDRAM */
 383 #ifndef CONFIG_EBIU_SDBCTL_VAL
 384 # if CONFIG_MEM_SIZE == 16
 385 #  define CONFIG_EBSZ_VAL EBSZ_16
 386 # elif CONFIG_MEM_SIZE == 32
 387 #  define CONFIG_EBSZ_VAL EBSZ_32
 388 # elif CONFIG_MEM_SIZE == 64
 389 #  define CONFIG_EBSZ_VAL EBSZ_64
 390 # elif CONFIG_MEM_SIZE == 128
 391 #  define CONFIG_EBSZ_VAL EBSZ_128
 392 # elif CONFIG_MEM_SIZE == 256
 393 #  define CONFIG_EBSZ_VAL EBSZ_256
 394 # elif CONFIG_MEM_SIZE == 512
 395 #  define CONFIG_EBSZ_VAL EBSZ_512
 396 # else
 397 #  error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_SIZE
 398 # endif
 399 # if CONFIG_MEM_ADD_WDTH == 8
 400 #  define CONFIG_EBCAW_VAL EBCAW_8
 401 # elif CONFIG_MEM_ADD_WDTH == 9
 402 #  define CONFIG_EBCAW_VAL EBCAW_9
 403 # elif CONFIG_MEM_ADD_WDTH == 10
 404 #  define CONFIG_EBCAW_VAL EBCAW_10
 405 # elif CONFIG_MEM_ADD_WDTH == 11
 406 #  define CONFIG_EBCAW_VAL EBCAW_11
 407 # else
 408 #  error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_ADD_WDTH
 409 # endif
 410 # define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE)
 411 #endif
 412 #endif
 413 #endif
 414
 415 /* Conflicting Column Address Widths Causes SDRAM Errors:
 416  * EB2CAW and EB3CAW must be the same
 417  */
 418 #if ANOMALY_05000362
 419 # if ((CONFIG_EBIU_SDBCTL_VAL & 0x30000000) >> 8) != (CONFIG_EBIU_SDBCTL_VAL & 0x00300000)
 420 #  error "Anomaly 05000362: EB2CAW and EB3CAW must be the same"
 421 # endif
 422 #endif
 423
 424 #endif /*  __ADSPBF60x__ */
 425
 426 __attribute__((always_inline)) static inline void
 427 program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
 428 {
 429         serial_putc('a');
 430
 431         /* Save the clock pieces that are used in baud rate calculation */
 432         if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
 433                 serial_putc('b');
 434 #ifdef __ADSPBF60x__
 435                 *sdivB = bfin_read_CGU_DIV();
 436                 *sdivB = ((*sdivB >> 8) & 0x1f) * ((*sdivB >> 5) & 0x7);
 437                 *vcoB = (bfin_read_CGU_CTL() >> 8) & 0x7f;
 438 #else
 439                 *sdivB = bfin_read_PLL_DIV() & 0xf;
 440                 *vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
 441 #endif
 442                 *divB = serial_early_get_div();
 443                 serial_putc('c');
 444         }
 445
 446         serial_putc('d');
 447
 448 #ifdef CONFIG_HW_WATCHDOG
 449 # ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
 450 #  define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
 451 # endif
 452         /* Program the watchdog with an initial timeout of ~20 seconds.
 453          * Hopefully that should be long enough to load the u-boot LDR
 454          * (from wherever) and then the common u-boot code can take over.
 455          * In bypass mode, the start.S would have already set a much lower
 456          * timeout, so don't clobber that.
 457          */
 458         if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
 459                 serial_putc('e');
 460 #ifdef __ADSPBF60x__
 461                 bfin_write_SEC_GCTL(0x2);
 462                 SSYNC();
 463                 bfin_write_SEC_FCTL(0xc1);
 464                 bfin_write_SEC_SCTL(2, bfin_read_SEC_SCTL(2) | 0x6);
 465
 466                 bfin_write_SEC_CCTL(0x2);
 467                 SSYNC();
 468                 bfin_write_SEC_GCTL(0x1);
 469                 bfin_write_SEC_CCTL(0x1);
 470 #endif
 471                 bfin_write_WDOG_CTL(WDDIS);
 472                 SSYNC();
 473                 bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
 474 #if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART
 475                 bfin_write_WDOG_CTL(WDEN);
 476 #endif
 477                 serial_putc('f');
 478         }
 479 #endif
 480
 481         serial_putc('g');
 482
 483         /* Blackfin bootroms use the SPI slow read opcode instead of the SPI
 484          * fast read, so we need to slow down the SPI clock a lot more during
 485          * boot.  Once we switch over to u-boot's SPI flash driver, we'll
 486          * increase the speed appropriately.
 487          */
 488 #ifdef SPI_BAUD
 489         if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
 490                 serial_putc('h');
 491                 if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4)
 492                         bs->dFlags |= BFLAG_FASTREAD;
 493                 bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
 494                 serial_putc('i');
 495         }
 496 #endif
 497
 498         serial_putc('j');
 499 }
 500
 501 __attribute__((always_inline)) static inline bool
 502 maybe_self_refresh(ADI_BOOT_DATA *bs)
 503 {
 504         serial_putc('a');
 505
 506         if (!CONFIG_MEM_SIZE)
 507                 return false;
 508
 509 #ifdef __ADSPBF60x__
 510         /* resume from hibernate, return false let ddr initialize */
 511         if ((bfin_read32(DPM0_STAT) & 0xF0) == 0x50) {
 512                 serial_putc('b');
 513                 return false;
 514         }
 515
 516 #else /* __ADSPBF60x__ */
 517
 518         /* If external memory is enabled, put it into self refresh first. */
 519 #if defined(EBIU_RSTCTL)
 520         if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
 521                 serial_putc('b');
 522                 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ);
 523                 return true;
 524         }
 525 #elif defined(EBIU_SDGCTL)
 526         if (bfin_read_EBIU_SDBCTL() & EBE) {
 527                 serial_putc('b');
 528                 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
 529                 return true;
 530         }
 531 #endif
 532
 533 #endif /* __ADSPBF60x__ */
 534         serial_putc('c');
 535
 536         return false;
 537 }
 538
 539 __attribute__((always_inline)) static inline u16
 540 program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
 541 {
 542         u16 vr_ctl;
 543
 544         serial_putc('a');
 545
 546 #ifdef __ADSPBF60x__
 547         if (bfin_read_DMC0_STAT() & MEMINITDONE) {
 548                 bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ);
 549                 SSYNC();
 550                 while (!(bfin_read_DMC0_STAT() & SRACK))
 551                         continue;
 552         }
 553
 554         /* Don't set the same value of MSEL and DF to CGU_CTL */
 555         if ((bfin_read_CGU_CTL() & (MSEL_MASK | DF_MASK))
 556                         != CONFIG_CGU_CTL_VAL) {
 557                 bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL);
 558                 bfin_write_CGU_CTL(CONFIG_CGU_CTL_VAL);
 559                 while ((bfin_read_CGU_STAT() & (CLKSALGN | PLLBP)) ||
 560                                 !(bfin_read_CGU_STAT() & PLLLK))
 561                         continue;
 562         }
 563
 564         bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL | UPDT);
 565         while (bfin_read_CGU_STAT() & CLKSALGN)
 566                 continue;
 567
 568         if (bfin_read_DMC0_STAT() & MEMINITDONE) {
 569                 bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ);
 570                 SSYNC();
 571                 while (bfin_read_DMC0_STAT() & SRACK)
 572                         continue;
 573         }
 574
 575 #else /* __ADSPBF60x__ */
 576
 577         vr_ctl = bfin_read_VR_CTL();
 578
 579         serial_putc('b');
 580
 581         /* If we're entering self refresh, make sure it has happened. */
 582         if (put_into_srfs)
 583 #if defined(EBIU_RSTCTL)
 584                 while (!(bfin_read_EBIU_RSTCTL() & SRACK))
 585                         continue;
 586 #elif defined(EBIU_SDGCTL)
 587                 while (!(bfin_read_EBIU_SDSTAT() & SDSRA))
 588                         continue;
 589 #else
 590                 ;
 591 #endif
 592
 593         serial_putc('c');
 594
 595         /* With newer bootroms, we use the helper function to set up
 596          * the memory controller.  Older bootroms lacks such helpers
 597          * so we do it ourselves.
 598          */
 599         if (!ANOMALY_05000386) {
 600                 serial_putc('d');
 601
 602                 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
 603                 ADI_SYSCTRL_VALUES memory_settings;
 604                 uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_LOCKCNT;
 605                 if (!ANOMALY_05000440)
 606                         actions |= SYSCTRL_PLLDIV;
 607                 if (CONFIG_HAS_VR) {
 608                         actions |= SYSCTRL_VRCTL;
 609                         if (CONFIG_VR_CTL_VAL & FREQ_MASK)
 610                                 actions |= SYSCTRL_INTVOLTAGE;
 611                         else
 612                                 actions |= SYSCTRL_EXTVOLTAGE;
 613                         memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
 614                 } else
 615                         actions |= SYSCTRL_EXTVOLTAGE;
 616                 memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
 617                 memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
 618                 memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
 619 #if ANOMALY_05000432
 620                 bfin_write_SIC_IWR1(0);
 621 #endif
 622                 serial_putc('e');
 623                 bfrom_SysControl(actions, &memory_settings, NULL);
 624                 serial_putc('f');
 625                 if (ANOMALY_05000440)
 626                         bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
 627 #if ANOMALY_05000432
 628                 bfin_write_SIC_IWR1(-1);
 629 #endif
 630 #if ANOMALY_05000171
 631                 bfin_write_SICA_IWR0(-1);
 632                 bfin_write_SICA_IWR1(-1);
 633 #endif
 634                 serial_putc('g');
 635         } else {
 636                 serial_putc('h');
 637
 638                 /* Disable all peripheral wakeups except for the PLL event. */
 639 #ifdef SIC_IWR0
 640                 bfin_write_SIC_IWR0(1);
 641                 bfin_write_SIC_IWR1(0);
 642 # ifdef SIC_IWR2
 643                 bfin_write_SIC_IWR2(0);
 644 # endif
 645 #elif defined(SICA_IWR0)
 646                 bfin_write_SICA_IWR0(1);
 647                 bfin_write_SICA_IWR1(0);
 648 #elif defined(SIC_IWR)
 649                 bfin_write_SIC_IWR(1);
 650 #endif
 651
 652                 serial_putc('i');
 653
 654                 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
 655                 bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
 656
 657                 serial_putc('j');
 658
 659                 /* Only reprogram when needed to avoid triggering unnecessary
 660                  * PLL relock sequences.
 661                  */
 662                 if (vr_ctl != CONFIG_VR_CTL_VAL) {
 663                         serial_putc('?');
 664                         bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
 665                         asm("idle;");
 666                         serial_putc('!');
 667                 }
 668
 669                 serial_putc('k');
 670
 671                 bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
 672
 673                 serial_putc('l');
 674
 675                 /* Only reprogram when needed to avoid triggering unnecessary
 676                  * PLL relock sequences.
 677                  */
 678                 if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
 679                         serial_putc('?');
 680                         bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
 681                         asm("idle;");
 682                         serial_putc('!');
 683                 }
 684
 685                 serial_putc('m');
 686
 687                 /* Restore all peripheral wakeups. */
 688 #ifdef SIC_IWR0
 689                 bfin_write_SIC_IWR0(-1);
 690                 bfin_write_SIC_IWR1(-1);
 691 # ifdef SIC_IWR2
 692                 bfin_write_SIC_IWR2(-1);
 693 # endif
 694 #elif defined(SICA_IWR0)
 695                 bfin_write_SICA_IWR0(-1);
 696                 bfin_write_SICA_IWR1(-1);
 697 #elif defined(SIC_IWR)
 698                 bfin_write_SIC_IWR(-1);
 699 #endif
 700
 701                 serial_putc('n');
 702         }
 703
 704 #endif /* __ADSPBF60x__ */
 705
 706         serial_putc('o');
 707
 708         return vr_ctl;
 709 }
 710
 711 __attribute__((always_inline)) static inline void
 712 update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
 713 {
 714         /* Since we've changed the SCLK above, we may need to update
 715          * the UART divisors (UART baud rates are based on SCLK).
 716          * Do the division by hand as there are no native instructions
 717          * for dividing which means we'd generate a libgcc reference.
 718          */
 719         unsigned int sdivR, vcoR;
 720         unsigned int dividend;
 721         unsigned int divisor;
 722         unsigned int quotient;
 723
 724         serial_putc('a');
 725
 726 #ifdef __ADSPBF60x__
 727         sdivR = bfin_read_CGU_DIV();
 728         sdivR = ((sdivR >> 8) & 0x1f) * ((sdivR >> 5) & 0x7);
 729         vcoR = (bfin_read_CGU_CTL() >> 8) & 0x7f;
 730 #else
 731         sdivR = bfin_read_PLL_DIV() & 0xf;
 732         vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
 733 #endif
 734
 735         dividend = sdivB * divB * vcoR;
 736         divisor = vcoB * sdivR;
 737         quotient = early_division(dividend, divisor);
 738         serial_early_put_div(quotient - ANOMALY_05000230);
 739         serial_putc('c');
 740 }
 741
 742 __attribute__((always_inline)) static inline void
 743 program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
 744 {
 745         serial_putc('a');
 746
 747         if (!CONFIG_MEM_SIZE)
 748                 return;
 749
 750         serial_putc('b');
 751
 752 #ifdef __ADSPBF60x__
 753         int dlldatacycle;
 754         int dll_ctl;
 755         int i = 0;
 756
 757         if (CONFIG_BFIN_GET_DCLK_M ==  125)
 758                 i = 0;
 759         else if (CONFIG_BFIN_GET_DCLK_M ==  133)
 760                 i = 1;
 761         else if (CONFIG_BFIN_GET_DCLK_M ==  150)
 762                 i = 2;
 763         else if (CONFIG_BFIN_GET_DCLK_M ==  166)
 764                 i = 3;
 765         else if (CONFIG_BFIN_GET_DCLK_M ==  200)
 766                 i = 4;
 767         else if (CONFIG_BFIN_GET_DCLK_M ==  225)
 768                 i = 5;
 769         else if (CONFIG_BFIN_GET_DCLK_M ==  250)
 770                 i = 6;
 771
 772 #if 0
 773         for (i = 0; i < ARRAY_SIZE(ddr_config_table); i++)
 774                 if (CONFIG_BFIN_GET_DCLK_M == ddr_config_table[i].ddr_clk)
 775                         break;
 776 #endif
 777
 778 #ifndef CONFIG_DMC_DDRCFG
 779         bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg);
 780 #else
 781         bfin_write_DMC0_CFG(CONFIG_DMC_DDRCFG);
 782 #endif
 783 #ifndef CONFIG_DMC_DDRTR0
 784         bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0);
 785 #else
 786         bfin_write_DMC0_TR0(CONFIG_DMC_DDRTR0);
 787 #endif
 788 #ifndef CONFIG_DMC_DDRTR1
 789         bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1);
 790 #else
 791         bfin_write_DMC0_TR1(CONFIG_DMC_DDRTR1);
 792 #endif
 793 #ifndef CONFIG_DMC_DDRTR2
 794         bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2);
 795 #else
 796         bfin_write_DMC0_TR2(CONFIG_DMC_DDRTR2);
 797 #endif
 798 #ifndef CONFIG_DMC_DDRMR
 799         bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr);
 800 #else
 801         bfin_write_DMC0_MR(CONFIG_DMC_DDRMR);
 802 #endif
 803 #ifndef CONFIG_DMC_DDREMR1
 804         bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1);
 805 #else
 806         bfin_write_DMC0_EMR1(CONFIG_DMC_DDREMR1);
 807 #endif
 808 #ifndef CONFIG_DMC_DDRCTL
 809         bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl);
 810 #else
 811         bfin_write_DMC0_CTL(CONFIG_DMC_DDRCTL);
 812 #endif
 813
 814         SSYNC();
 815         while (!(bfin_read_DMC0_STAT() & MEMINITDONE))
 816                 continue;
 817
 818         dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >>
 819                         PHYRDPHASE_OFFSET;
 820         dll_ctl = bfin_read_DMC0_DLLCTL();
 821         dll_ctl &= 0x0ff;
 822         bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET));
 823
 824         SSYNC();
 825         while (!(bfin_read_DMC0_STAT() & DLLCALDONE))
 826                 continue;
 827         serial_putc('!');
 828
 829 #else /* __ADSPBF60x__ */
 830
 831         /* Program the external memory controller before we come out of
 832          * self-refresh.  This only works with our SDRAM controller.
 833          */
 834 #ifdef EBIU_SDGCTL
 835 # ifdef CONFIG_EBIU_SDRRC_VAL
 836         bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
 837 # endif
 838 # ifdef CONFIG_EBIU_SDBCTL_VAL
 839         bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
 840 # endif
 841 # ifdef CONFIG_EBIU_SDGCTL_VAL
 842         bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
 843 # endif
 844 #endif
 845
 846         serial_putc('c');
 847
 848         /* Now that we've reprogrammed, take things out of self refresh. */
 849         if (put_into_srfs)
 850 #if defined(EBIU_RSTCTL)
 851                 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
 852 #elif defined(EBIU_SDGCTL)
 853                 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS));
 854 #endif
 855
 856         serial_putc('d');
 857
 858         /* Our DDR controller sucks and cannot be programmed while in
 859          * self-refresh.  So we have to pull it out before programming.
 860          */
 861 #ifdef EBIU_RSTCTL
 862 # ifdef CONFIG_EBIU_RSTCTL_VAL
 863         bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
 864 # endif
 865 # ifdef CONFIG_EBIU_DDRCTL0_VAL
 866         bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
 867 # endif
 868 # ifdef CONFIG_EBIU_DDRCTL1_VAL
 869         bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
 870 # endif
 871 # ifdef CONFIG_EBIU_DDRCTL2_VAL
 872         bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
 873 # endif
 874 # ifdef CONFIG_EBIU_DDRCTL3_VAL
 875         /* default is disable, so don't need to force this */
 876         bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
 877 # endif
 878 # ifdef CONFIG_EBIU_DDRQUE_VAL
 879         bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | CONFIG_EBIU_DDRQUE_VAL);
 880 # endif
 881 #endif
 882
 883 #endif /* __ADSPBF60x__ */
 884         serial_putc('e');
 885 }
 886
 887 __attribute__((always_inline)) static inline void
 888 check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs)
 889 {
 890         serial_putc('a');
 891
 892         if (!CONFIG_MEM_SIZE)
 893                 return;
 894
 895         serial_putc('b');
 896 #ifdef __ADSPBF60x__
 897         if (bfin_read32(DPM0_RESTORE0) != 0) {
 898                 uint32_t reg = bfin_read_DMC0_CTL();
 899                 reg &= ~0x8;
 900                 bfin_write_DMC0_CTL(reg);
 901
 902                 while ((bfin_read_DMC0_STAT() & 0x8))
 903                         continue;
 904                 while (!(bfin_read_DMC0_STAT() & 0x1))
 905                         continue;
 906
 907                 serial_putc('z');
 908                 uint32_t *hibernate_magic = bfin_read32(DPM0_RESTORE4);
 909                 SSYNC(); /* make sure memory controller is done */
 910                 if (hibernate_magic[0] == 0xDEADBEEF) {
 911                         serial_putc('c');
 912                         SSYNC();
 913                         bfin_write_EVT15(hibernate_magic[1]);
 914                         bfin_write_IMASK(EVT_IVG15);
 915                         __asm__ __volatile__ (
 916                                 /* load reti early to avoid anomaly 281 */
 917                                 "reti = %2;"
 918                                 /* clear hibernate magic */
 919                                 "[%0] = %1;"
 920                                 /* load stack pointer */
 921                                 "SP = [%0 + 8];"
 922                                 /* lower ourselves from reset ivg to ivg15 */
 923                                 "raise 15;"
 924                                 "nop;nop;nop;"
 925                                 "rti;"
 926                                 :
 927                                 : "p"(hibernate_magic),
 928                                 "d"(0x2000 /* jump.s 0 */),
 929                                 "d"(0xffa00000)
 930                         );
 931                 }
 932
 933
 934         }
 935 #else
 936         /* Are we coming out of hibernate (suspend to memory) ?
 937          * The memory layout is:
 938          * 0x0: hibernate magic for anomaly 307 (0xDEADBEEF)
 939          * 0x4: return address
 940          * 0x8: stack pointer
 941          *
 942          * SCKELOW is unreliable on older parts (anomaly 307)
 943          */
 944         if (ANOMALY_05000307 || vr_ctl & 0x8000) {
 945                 uint32_t *hibernate_magic = 0;
 946
 947                 SSYNC();
 948                 if (hibernate_magic[0] == 0xDEADBEEF) {
 949                         serial_putc('c');
 950                         bfin_write_EVT15(hibernate_magic[1]);
 951                         bfin_write_IMASK(EVT_IVG15);
 952                         __asm__ __volatile__ (
 953                                 /* load reti early to avoid anomaly 281 */
 954                                 "reti = %0;"
 955                                 /* clear hibernate magic */
 956                                 "[%0] = %1;"
 957                                 /* load stack pointer */
 958                                 "SP = [%0 + 8];"
 959                                 /* lower ourselves from reset ivg to ivg15 */
 960                                 "raise 15;"
 961                                 "rti;"
 962                                 :
 963                                 : "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */)
 964                         );
 965                 }
 966                 serial_putc('d');
 967         }
 968 #endif
 969
 970         serial_putc('e');
 971 }
 972
 973 BOOTROM_CALLED_FUNC_ATTR
 974 void initcode(ADI_BOOT_DATA *bs)
 975 {
 976         ADI_BOOT_DATA bootstruct_scratch;
 977
 978         /* Setup NMI handler before anything else */
 979         program_nmi_handler();
 980
 981         serial_init();
 982
 983         serial_putc('A');
 984
 985         /* If the bootstruct is NULL, then it's because we're loading
 986          * dynamically and not via LDR (bootrom).  So set the struct to
 987          * some scratch space.
 988          */
 989         if (!bs)
 990                 bs = &bootstruct_scratch;
 991
 992         serial_putc('B');
 993         bool put_into_srfs = maybe_self_refresh(bs);
 994
 995         serial_putc('C');
 996         uint sdivB, divB, vcoB;
 997         program_early_devices(bs, &sdivB, &divB, &vcoB);
 998
 999         serial_putc('D');
1000         u16 vr_ctl = program_clocks(bs, put_into_srfs);
1001
1002         serial_putc('E');
1003         update_serial_clocks(bs, sdivB, divB, vcoB);
1004
1005         serial_putc('F');
1006         program_memory_controller(bs, put_into_srfs);
1007
1008         serial_putc('G');
1009         check_hibernation(bs, vr_ctl, put_into_srfs);
1010
1011         serial_putc('H');
1012         program_async_controller(bs);
1013
1014 #ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
1015         serial_putc('I');
1016         /* Tell the bootrom where our entry point is so that it knows
1017          * where to jump to when finishing processing the LDR.  This
1018          * allows us to avoid small jump blocks in the LDR, and also
1019          * works around anomaly 05000389 (init address in external
1020          * memory causes bootrom to trigger external addressing IVHW).
1021          */
1022         if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
1023                 bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE);
1024 #endif
1025
1026         serial_putc('>');
1027         serial_putc('\n');
1028
1029         serial_deinit();
1030 }