11 config RWSEM_GENERIC_SPINLOCK
14 config RWSEM_XCHGADD_ALGORITHM
20 select HAVE_ARCH_TRACEHOOK
21 select HAVE_DYNAMIC_FTRACE
22 select HAVE_FTRACE_MCOUNT_RECORD
23 select HAVE_FUNCTION_GRAPH_TRACER
24 select HAVE_FUNCTION_TRACER
25 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
28 select HAVE_KERNEL_GZIP if RAMKERNEL
29 select HAVE_KERNEL_BZIP2 if RAMKERNEL
30 select HAVE_KERNEL_LZMA if RAMKERNEL
31 select HAVE_KERNEL_LZO if RAMKERNEL
33 select HAVE_PERF_EVENTS
34 select ARCH_HAVE_CUSTOM_GPIO_H
35 select ARCH_WANT_OPTIONAL_GPIOLIB
37 select ARCH_WANT_IPC_PARSE_VERSION
38 select HAVE_GENERIC_HARDIRQS
39 select GENERIC_ATOMIC64
40 select GENERIC_IRQ_PROBE
41 select IRQ_PER_CPU if SMP
42 select USE_GENERIC_SMP_HELPERS if SMP
43 select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
44 select GENERIC_SMP_IDLE_THREAD
45 select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
60 config FORCE_MAX_ZONEORDER
64 config GENERIC_CALIBRATE_DELAY
67 config LOCKDEP_SUPPORT
70 config STACKTRACE_SUPPORT
73 config TRACE_IRQFLAGS_SUPPORT
78 source "kernel/Kconfig.preempt"
80 source "kernel/Kconfig.freezer"
82 menu "Blackfin Processor Options"
84 comment "Processor and Board Settings"
93 BF512 Processor Support.
98 BF514 Processor Support.
103 BF516 Processor Support.
108 BF518 Processor Support.
113 BF522 Processor Support.
118 BF523 Processor Support.
123 BF524 Processor Support.
128 BF525 Processor Support.
133 BF526 Processor Support.
138 BF527 Processor Support.
143 BF531 Processor Support.
148 BF532 Processor Support.
153 BF533 Processor Support.
158 BF534 Processor Support.
163 BF536 Processor Support.
168 BF537 Processor Support.
173 BF538 Processor Support.
178 BF539 Processor Support.
183 BF542 Processor Support.
188 BF542 Processor Support.
193 BF544 Processor Support.
198 BF544 Processor Support.
203 BF547 Processor Support.
208 BF547 Processor Support.
213 BF548 Processor Support.
218 BF548 Processor Support.
223 BF549 Processor Support.
228 BF549 Processor Support.
233 BF561 Processor Support.
239 BF609 Processor Support.
245 select TICKSOURCE_CORETMR
246 bool "Symmetric multi-processing support"
248 This enables support for systems with more than one CPU,
249 like the dual core BF561. If you have a system with only one
250 CPU, say N. If you have a system with more than one CPU, say Y.
252 If you don't know what to do here, say N.
260 bool "Support for hot-pluggable CPUs"
261 depends on SMP && HOTPLUG
266 default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
267 default 2 if (BF537 || BF536 || BF534)
268 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
269 default 4 if (BF538 || BF539)
273 default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
274 default 3 if (BF537 || BF536 || BF534 || BF54xM)
275 default 5 if (BF561 || BF538 || BF539)
276 default 6 if (BF533 || BF532 || BF531)
280 default BF_REV_0_0 if (BF51x || BF52x || BF60x)
281 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
282 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
286 depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
290 depends on (BF51x || BF52x || (BF54x && !BF54xM))
294 depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
298 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
302 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x)
306 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
310 depends on (BF533 || BF532 || BF531)
322 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
325 config MEM_MT48LC64M4A2FB_7E
327 depends on (BFIN533_STAMP)
330 config MEM_MT48LC16M16A2TG_75
332 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
333 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
334 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
335 || BFIN527_BLUETECHNIX_CM)
338 config MEM_MT48LC32M8A2_75
340 depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
343 config MEM_MT48LC8M32B2B5_7
345 depends on (BFIN561_BLUETECHNIX_CM)
348 config MEM_MT48LC32M16A2TG_75
350 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
353 config MEM_MT48H32M16LFCJ_75
355 depends on (BFIN526_EZBRD)
358 config MEM_MT47H64M16
360 depends on (BFIN609_EZKIT)
363 source "arch/blackfin/mach-bf518/Kconfig"
364 source "arch/blackfin/mach-bf527/Kconfig"
365 source "arch/blackfin/mach-bf533/Kconfig"
366 source "arch/blackfin/mach-bf561/Kconfig"
367 source "arch/blackfin/mach-bf537/Kconfig"
368 source "arch/blackfin/mach-bf538/Kconfig"
369 source "arch/blackfin/mach-bf548/Kconfig"
370 source "arch/blackfin/mach-bf609/Kconfig"
372 menu "Board customizations"
375 bool "Default bootloader kernel arguments"
378 string "Initial kernel command string"
379 depends on CMDLINE_BOOL
380 default "console=ttyBF0,57600"
382 If you don't have a boot loader capable of passing a command line string
383 to the kernel, you may specify one here. As a minimum, you should specify
384 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
387 hex "Kernel load address for booting"
389 range 0x1000 0x20000000
391 This option allows you to set the load address of the kernel.
392 This can be useful if you are on a board which has a small amount
393 of memory or you wish to reserve some memory at the beginning of
396 Note that you need to keep this value above 4k (0x1000) as this
397 memory region is used to capture NULL pointer references as well
398 as some core kernel functions.
400 config PHY_RAM_BASE_ADDRESS
401 hex "Physical RAM Base"
404 set BF609 FPGA physical SRAM base address
407 hex "Kernel ROM Base"
410 range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
411 range 0x20000000 0x30000000 if (BF54x || BF561)
412 range 0xB0000000 0xC0000000 if (BF60x)
414 Make sure your ROM base does not include any file-header
415 information that is prepended to the kernel.
417 For example, the bootable U-Boot format (created with
418 mkimage) has a 64 byte header (0x40). So while the image
419 you write to flash might start at say 0x20080000, you have
420 to add 0x40 to get the kernel's ROM base as it will come
423 comment "Clock/PLL Setup"
426 int "Frequency of the crystal on the board in Hz"
427 default "10000000" if BFIN532_IP0X
428 default "11059200" if BFIN533_STAMP
429 default "24576000" if PNAV10
430 default "25000000" # most people use this
431 default "27000000" if BFIN533_EZKIT
432 default "30000000" if BFIN561_EZKIT
433 default "24000000" if BFIN527_AD7160EVAL
435 The frequency of CLKIN crystal oscillator on the board in Hz.
436 Warning: This value should match the crystal on the board. Otherwise,
437 peripherals won't work properly.
439 config BFIN_KERNEL_CLOCK
440 bool "Re-program Clocks while Kernel boots?"
443 This option decides if kernel clocks are re-programed from the
444 bootloader settings. If the clocks are not set, the SDRAM settings
445 are also not changed, and the Bootloader does 100% of the hardware
450 depends on BFIN_KERNEL_CLOCK && (!BF60x)
455 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
458 If this is set the clock will be divided by 2, before it goes to the PLL.
462 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
464 default "22" if BFIN533_EZKIT
465 default "45" if BFIN533_STAMP
466 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
467 default "22" if BFIN533_BLUETECHNIX_CM
468 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
469 default "20" if (BFIN561_EZKIT || BF609)
470 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
471 default "25" if BFIN527_AD7160EVAL
473 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
474 PLL Frequency = (Crystal Frequency) * (this setting)
477 prompt "Core Clock Divider"
478 depends on BFIN_KERNEL_CLOCK
481 This sets the frequency of the core. It can be 1, 2, 4 or 8
482 Core Frequency = (PLL frequency) / (this setting)
498 int "System Clock Divider"
499 depends on BFIN_KERNEL_CLOCK
503 This sets the frequency of the system clock (including SDRAM or DDR) on
504 !BF60x else it set the clock for system buses and provides the
505 source from which SCLK0 and SCLK1 are derived.
506 This can be between 1 and 15
507 System Clock = (PLL frequency) / (this setting)
510 int "System Clock0 Divider"
511 depends on BFIN_KERNEL_CLOCK && BF60x
515 This sets the frequency of the system clock0 for PVP and all other
516 peripherals not clocked by SCLK1.
517 This can be between 1 and 15
518 System Clock0 = (System Clock) / (this setting)
521 int "System Clock1 Divider"
522 depends on BFIN_KERNEL_CLOCK && BF60x
526 This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
527 This can be between 1 and 15
528 System Clock1 = (System Clock) / (this setting)
531 int "DDR Clock Divider"
532 depends on BFIN_KERNEL_CLOCK && BF60x
536 This sets the frequency of the DDR memory.
537 This can be between 1 and 15
538 DDR Clock = (PLL frequency) / (this setting)
541 prompt "DDR SDRAM Chip Type"
542 depends on BFIN_KERNEL_CLOCK
544 default MEM_MT46V32M16_5B
546 config MEM_MT46V32M16_6T
549 config MEM_MT46V32M16_5B
554 prompt "DDR/SDRAM Timing"
555 depends on BFIN_KERNEL_CLOCK && !BF60x
556 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
558 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
559 The calculated SDRAM timing parameters may not be 100%
560 accurate - This option is therefore marked experimental.
562 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
563 bool "Calculate Timings (EXPERIMENTAL)"
564 depends on EXPERIMENTAL
566 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
567 bool "Provide accurate Timings based on target SCLK"
569 Please consult the Blackfin Hardware Reference Manuals as well
570 as the memory device datasheet.
571 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
574 menu "Memory Init Control"
575 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
592 config MEM_EBIU_DDRQUE
609 # Max & Min Speeds for various Chips
613 default 400000000 if BF512
614 default 400000000 if BF514
615 default 400000000 if BF516
616 default 400000000 if BF518
617 default 400000000 if BF522
618 default 600000000 if BF523
619 default 400000000 if BF524
620 default 600000000 if BF525
621 default 400000000 if BF526
622 default 600000000 if BF527
623 default 400000000 if BF531
624 default 400000000 if BF532
625 default 750000000 if BF533
626 default 500000000 if BF534
627 default 400000000 if BF536
628 default 600000000 if BF537
629 default 533333333 if BF538
630 default 533333333 if BF539
631 default 600000000 if BF542
632 default 533333333 if BF544
633 default 600000000 if BF547
634 default 600000000 if BF548
635 default 533333333 if BF549
636 default 600000000 if BF561
637 default 800000000 if BF609
645 default 200000000 if BF609
652 comment "Kernel Timer/Scheduler"
654 source kernel/Kconfig.hz
656 config SET_GENERIC_CLOCKEVENTS
657 bool "Generic clock events"
659 select GENERIC_CLOCKEVENTS
661 menu "Clock event device"
662 depends on GENERIC_CLOCKEVENTS
663 config TICKSOURCE_GPTMR0
668 config TICKSOURCE_CORETMR
674 depends on GENERIC_CLOCKEVENTS
675 config CYCLES_CLOCKSOURCE
678 depends on !BFIN_SCRATCH_REG_CYCLES
681 If you say Y here, you will enable support for using the 'cycles'
682 registers as a clock source. Doing so means you will be unable to
683 safely write to the 'cycles' register during runtime. You will
684 still be able to read it (such as for performance monitoring), but
685 writing the registers will most likely crash the kernel.
687 config GPTMR0_CLOCKSOURCE
690 depends on !TICKSOURCE_GPTMR0
696 prompt "Blackfin Exception Scratch Register"
697 default BFIN_SCRATCH_REG_RETN
699 Select the resource to reserve for the Exception handler:
700 - RETN: Non-Maskable Interrupt (NMI)
701 - RETE: Exception Return (JTAG/ICE)
702 - CYCLES: Performance counter
704 If you are unsure, please select "RETN".
706 config BFIN_SCRATCH_REG_RETN
709 Use the RETN register in the Blackfin exception handler
710 as a stack scratch register. This means you cannot
711 safely use NMI on the Blackfin while running Linux, but
712 you can debug the system with a JTAG ICE and use the
713 CYCLES performance registers.
715 If you are unsure, please select "RETN".
717 config BFIN_SCRATCH_REG_RETE
720 Use the RETE register in the Blackfin exception handler
721 as a stack scratch register. This means you cannot
722 safely use a JTAG ICE while debugging a Blackfin board,
723 but you can safely use the CYCLES performance registers
726 If you are unsure, please select "RETN".
728 config BFIN_SCRATCH_REG_CYCLES
731 Use the CYCLES register in the Blackfin exception handler
732 as a stack scratch register. This means you cannot
733 safely use the CYCLES performance registers on a Blackfin
734 board at anytime, but you can debug the system with a JTAG
737 If you are unsure, please select "RETN".
744 menu "Blackfin Kernel Optimizations"
746 comment "Memory Optimizations"
749 bool "Locate interrupt entry code in L1 Memory"
753 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
754 into L1 instruction memory. (less latency)
756 config EXCPT_IRQ_SYSC_L1
757 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
761 If enabled, the entire ASM lowlevel exception and interrupt entry code
762 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
766 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
770 If enabled, the frequently called do_irq dispatcher function is linked
771 into L1 instruction memory. (less latency)
773 config CORE_TIMER_IRQ_L1
774 bool "Locate frequently called timer_interrupt() function in L1 Memory"
778 If enabled, the frequently called timer_interrupt() function is linked
779 into L1 instruction memory. (less latency)
782 bool "Locate frequently idle function in L1 Memory"
786 If enabled, the frequently called idle function is linked
787 into L1 instruction memory. (less latency)
790 bool "Locate kernel schedule function in L1 Memory"
794 If enabled, the frequently called kernel schedule is linked
795 into L1 instruction memory. (less latency)
797 config ARITHMETIC_OPS_L1
798 bool "Locate kernel owned arithmetic functions in L1 Memory"
802 If enabled, arithmetic functions are linked
803 into L1 instruction memory. (less latency)
806 bool "Locate access_ok function in L1 Memory"
810 If enabled, the access_ok function is linked
811 into L1 instruction memory. (less latency)
814 bool "Locate memset function in L1 Memory"
818 If enabled, the memset function is linked
819 into L1 instruction memory. (less latency)
822 bool "Locate memcpy function in L1 Memory"
826 If enabled, the memcpy function is linked
827 into L1 instruction memory. (less latency)
830 bool "locate strcmp function in L1 Memory"
834 If enabled, the strcmp function is linked
835 into L1 instruction memory (less latency).
838 bool "locate strncmp function in L1 Memory"
842 If enabled, the strncmp function is linked
843 into L1 instruction memory (less latency).
846 bool "locate strcpy function in L1 Memory"
850 If enabled, the strcpy function is linked
851 into L1 instruction memory (less latency).
854 bool "locate strncpy function in L1 Memory"
858 If enabled, the strncpy function is linked
859 into L1 instruction memory (less latency).
861 config SYS_BFIN_SPINLOCK_L1
862 bool "Locate sys_bfin_spinlock function in L1 Memory"
866 If enabled, sys_bfin_spinlock function is linked
867 into L1 instruction memory. (less latency)
869 config IP_CHECKSUM_L1
870 bool "Locate IP Checksum function in L1 Memory"
874 If enabled, the IP Checksum function is linked
875 into L1 instruction memory. (less latency)
877 config CACHELINE_ALIGNED_L1
878 bool "Locate cacheline_aligned data to L1 Data Memory"
881 depends on !SMP && !BF531 && !CRC32
883 If enabled, cacheline_aligned data is linked
884 into L1 data memory. (less latency)
886 config SYSCALL_TAB_L1
887 bool "Locate Syscall Table L1 Data Memory"
889 depends on !SMP && !BF531
891 If enabled, the Syscall LUT is linked
892 into L1 data memory. (less latency)
894 config CPLB_SWITCH_TAB_L1
895 bool "Locate CPLB Switch Tables L1 Data Memory"
897 depends on !SMP && !BF531
899 If enabled, the CPLB Switch Tables are linked
900 into L1 data memory. (less latency)
902 config ICACHE_FLUSH_L1
903 bool "Locate icache flush funcs in L1 Inst Memory"
906 If enabled, the Blackfin icache flushing functions are linked
907 into L1 instruction memory.
909 Note that this might be required to address anomalies, but
910 these functions are pretty small, so it shouldn't be too bad.
911 If you are using a processor affected by an anomaly, the build
912 system will double check for you and prevent it.
914 config DCACHE_FLUSH_L1
915 bool "Locate dcache flush funcs in L1 Inst Memory"
919 If enabled, the Blackfin dcache flushing functions are linked
920 into L1 instruction memory.
923 bool "Support locating application stack in L1 Scratch Memory"
927 If enabled the application stack can be located in L1
928 scratch memory (less latency).
930 Currently only works with FLAT binaries.
932 config EXCEPTION_L1_SCRATCH
933 bool "Locate exception stack in L1 Scratch Memory"
935 depends on !SMP && !APP_STACK_L1
937 Whenever an exception occurs, use the L1 Scratch memory for
938 stack storage. You cannot place the stacks of FLAT binaries
939 in L1 when using this option.
941 If you don't use L1 Scratch, then you should say Y here.
943 comment "Speed Optimizations"
944 config BFIN_INS_LOWOVERHEAD
945 bool "ins[bwl] low overhead, higher interrupt latency"
949 Reads on the Blackfin are speculative. In Blackfin terms, this means
950 they can be interrupted at any time (even after they have been issued
951 on to the external bus), and re-issued after the interrupt occurs.
952 For memory - this is not a big deal, since memory does not change if
955 If a FIFO is sitting on the end of the read, it will see two reads,
956 when the core only sees one since the FIFO receives both the read
957 which is cancelled (and not delivered to the core) and the one which
958 is re-issued (which is delivered to the core).
960 To solve this, interrupts are turned off before reads occur to
961 I/O space. This option controls which the overhead/latency of
962 controlling interrupts during this time
963 "n" turns interrupts off every read
964 (higher overhead, but lower interrupt latency)
965 "y" turns interrupts off every loop
966 (low overhead, but longer interrupt latency)
968 default behavior is to leave this set to on (type "Y"). If you are experiencing
969 interrupt latency issues, it is safe and OK to turn this off.
974 prompt "Kernel executes from"
976 Choose the memory type that the kernel will be running in.
981 The kernel will be resident in RAM when running.
986 The kernel will be resident in FLASH/ROM when running.
990 # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
999 tristate "Enable Blackfin General Purpose Timers API"
1002 Enable support for the General Purpose Timers API. If you
1005 To compile this driver as a module, choose M here: the module
1006 will be called gptimers.
1009 prompt "Uncached DMA region"
1010 default DMA_UNCACHED_1M
1011 config DMA_UNCACHED_32M
1012 bool "Enable 32M DMA region"
1013 config DMA_UNCACHED_16M
1014 bool "Enable 16M DMA region"
1015 config DMA_UNCACHED_8M
1016 bool "Enable 8M DMA region"
1017 config DMA_UNCACHED_4M
1018 bool "Enable 4M DMA region"
1019 config DMA_UNCACHED_2M
1020 bool "Enable 2M DMA region"
1021 config DMA_UNCACHED_1M
1022 bool "Enable 1M DMA region"
1023 config DMA_UNCACHED_512K
1024 bool "Enable 512K DMA region"
1025 config DMA_UNCACHED_256K
1026 bool "Enable 256K DMA region"
1027 config DMA_UNCACHED_128K
1028 bool "Enable 128K DMA region"
1029 config DMA_UNCACHED_NONE
1030 bool "Disable DMA region"
1034 comment "Cache Support"
1037 bool "Enable ICACHE"
1039 config BFIN_EXTMEM_ICACHEABLE
1040 bool "Enable ICACHE for external memory"
1041 depends on BFIN_ICACHE
1043 config BFIN_L2_ICACHEABLE
1044 bool "Enable ICACHE for L2 SRAM"
1045 depends on BFIN_ICACHE
1046 depends on (BF54x || BF561 || BF60x) && !SMP
1050 bool "Enable DCACHE"
1052 config BFIN_DCACHE_BANKA
1053 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
1054 depends on BFIN_DCACHE && !BF531
1056 config BFIN_EXTMEM_DCACHEABLE
1057 bool "Enable DCACHE for external memory"
1058 depends on BFIN_DCACHE
1061 prompt "External memory DCACHE policy"
1062 depends on BFIN_EXTMEM_DCACHEABLE
1063 default BFIN_EXTMEM_WRITEBACK if !SMP
1064 default BFIN_EXTMEM_WRITETHROUGH if SMP
1065 config BFIN_EXTMEM_WRITEBACK
1070 Cached data will be written back to SDRAM only when needed.
1071 This can give a nice increase in performance, but beware of
1072 broken drivers that do not properly invalidate/flush their
1075 Write Through Policy:
1076 Cached data will always be written back to SDRAM when the
1077 cache is updated. This is a completely safe setting, but
1078 performance is worse than Write Back.
1080 If you are unsure of the options and you want to be safe,
1081 then go with Write Through.
1083 config BFIN_EXTMEM_WRITETHROUGH
1084 bool "Write through"
1087 Cached data will be written back to SDRAM only when needed.
1088 This can give a nice increase in performance, but beware of
1089 broken drivers that do not properly invalidate/flush their
1092 Write Through Policy:
1093 Cached data will always be written back to SDRAM when the
1094 cache is updated. This is a completely safe setting, but
1095 performance is worse than Write Back.
1097 If you are unsure of the options and you want to be safe,
1098 then go with Write Through.
1102 config BFIN_L2_DCACHEABLE
1103 bool "Enable DCACHE for L2 SRAM"
1104 depends on BFIN_DCACHE
1105 depends on (BF54x || BF561 || BF60x) && !SMP
1108 prompt "L2 SRAM DCACHE policy"
1109 depends on BFIN_L2_DCACHEABLE
1110 default BFIN_L2_WRITEBACK
1111 config BFIN_L2_WRITEBACK
1114 config BFIN_L2_WRITETHROUGH
1115 bool "Write through"
1119 comment "Memory Protection Unit"
1121 bool "Enable the memory protection unit (EXPERIMENTAL)"
1124 Use the processor's MPU to protect applications from accessing
1125 memory they do not own. This comes at a performance penalty
1126 and is recommended only for debugging.
1128 comment "Asynchronous Memory Configuration"
1130 menu "EBIU_AMGCTL Global Control"
1133 bool "Enable CLKOUT"
1137 bool "DMA has priority over core for ext. accesses"
1142 bool "Bank 0 16 bit packing enable"
1147 bool "Bank 1 16 bit packing enable"
1152 bool "Bank 2 16 bit packing enable"
1157 bool "Bank 3 16 bit packing enable"
1161 prompt "Enable Asynchronous Memory Banks"
1165 bool "Disable All Banks"
1168 bool "Enable Bank 0"
1170 config C_AMBEN_B0_B1
1171 bool "Enable Bank 0 & 1"
1173 config C_AMBEN_B0_B1_B2
1174 bool "Enable Bank 0 & 1 & 2"
1177 bool "Enable All Banks"
1181 menu "EBIU_AMBCTL Control"
1184 hex "Bank 0 (AMBCTL0.L)"
1187 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1188 used to control the Asynchronous Memory Bank 0 settings.
1191 hex "Bank 1 (AMBCTL0.H)"
1193 default 0x5558 if BF54x
1195 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1196 used to control the Asynchronous Memory Bank 1 settings.
1199 hex "Bank 2 (AMBCTL1.L)"
1202 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1203 used to control the Asynchronous Memory Bank 2 settings.
1206 hex "Bank 3 (AMBCTL1.H)"
1209 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1210 used to control the Asynchronous Memory Bank 3 settings.
1214 config EBIU_MBSCTLVAL
1215 hex "EBIU Bank Select Control Register"
1220 hex "Flash Memory Mode Control Register"
1225 hex "Flash Memory Bank Control Register"
1230 #############################################################################
1231 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1237 Support for PCI bus.
1239 source "drivers/pci/Kconfig"
1241 source "drivers/pcmcia/Kconfig"
1243 source "drivers/pci/hotplug/Kconfig"
1247 menu "Executable file formats"
1249 source "fs/Kconfig.binfmt"
1253 menu "Power management options"
1255 source "kernel/power/Kconfig"
1257 config ARCH_SUSPEND_POSSIBLE
1261 prompt "Standby Power Saving Mode"
1262 depends on PM && !BF60x
1263 default PM_BFIN_SLEEP_DEEPER
1264 config PM_BFIN_SLEEP_DEEPER
1267 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1268 power dissipation by disabling the clock to the processor core (CCLK).
1269 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1270 to 0.85 V to provide the greatest power savings, while preserving the
1272 The PLL and system clock (SCLK) continue to operate at a very low
1273 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1274 the SDRAM is put into Self Refresh Mode. Typically an external event
1275 such as GPIO interrupt or RTC activity wakes up the processor.
1276 Various Peripherals such as UART, SPORT, PPI may not function as
1277 normal during Sleep Deeper, due to the reduced SCLK frequency.
1278 When in the sleep mode, system DMA access to L1 memory is not supported.
1280 If unsure, select "Sleep Deeper".
1282 config PM_BFIN_SLEEP
1285 Sleep Mode (High Power Savings) - The sleep mode reduces power
1286 dissipation by disabling the clock to the processor core (CCLK).
1287 The PLL and system clock (SCLK), however, continue to operate in
1288 this mode. Typically an external event or RTC activity will wake
1289 up the processor. When in the sleep mode, system DMA access to L1
1290 memory is not supported.
1292 If unsure, select "Sleep Deeper".
1295 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1298 config PM_BFIN_WAKE_PH6
1299 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1300 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1303 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1305 config PM_BFIN_WAKE_GP
1306 bool "Allow Wake-Up from GPIOs"
1307 depends on PM && BF54x
1310 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1311 (all processors, except ADSP-BF549). This option sets
1312 the general-purpose wake-up enable (GPWE) control bit to enable
1313 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1314 On ADSP-BF549 this option enables the same functionality on the
1315 /MRXON pin also PH7.
1317 config PM_BFIN_WAKE_PA15
1318 bool "Allow Wake-Up from PA15"
1319 depends on PM && BF60x
1324 config PM_BFIN_WAKE_PA15_POL
1325 int "Wake-up priority"
1326 depends on PM_BFIN_WAKE_PA15
1329 Wake-Up priority 0(low) 1(high)
1331 config PM_BFIN_WAKE_PB15
1332 bool "Allow Wake-Up from PB15"
1333 depends on PM && BF60x
1338 config PM_BFIN_WAKE_PB15_POL
1339 int "Wake-up priority"
1340 depends on PM_BFIN_WAKE_PB15
1343 Wake-Up priority 0(low) 1(high)
1345 config PM_BFIN_WAKE_PC15
1346 bool "Allow Wake-Up from PC15"
1347 depends on PM && BF60x
1352 config PM_BFIN_WAKE_PC15_POL
1353 int "Wake-up priority"
1354 depends on PM_BFIN_WAKE_PC15
1357 Wake-Up priority 0(low) 1(high)
1359 config PM_BFIN_WAKE_PD06
1360 bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
1361 depends on PM && BF60x
1364 Enable PD06(ETH0_PHYINT) Wake-up
1366 config PM_BFIN_WAKE_PD06_POL
1367 int "Wake-up priority"
1368 depends on PM_BFIN_WAKE_PD06
1371 Wake-Up priority 0(low) 1(high)
1373 config PM_BFIN_WAKE_PE12
1374 bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
1375 depends on PM && BF60x
1378 Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
1380 config PM_BFIN_WAKE_PE12_POL
1381 int "Wake-up priority"
1382 depends on PM_BFIN_WAKE_PE12
1385 Wake-Up priority 0(low) 1(high)
1387 config PM_BFIN_WAKE_PG04
1388 bool "Allow Wake-Up from PG04(CAN0_RX)"
1389 depends on PM && BF60x
1392 Enable PG04(CAN0_RX) Wake-up
1394 config PM_BFIN_WAKE_PG04_POL
1395 int "Wake-up priority"
1396 depends on PM_BFIN_WAKE_PG04
1399 Wake-Up priority 0(low) 1(high)
1401 config PM_BFIN_WAKE_PG13
1402 bool "Allow Wake-Up from PG13"
1403 depends on PM && BF60x
1408 config PM_BFIN_WAKE_PG13_POL
1409 int "Wake-up priority"
1410 depends on PM_BFIN_WAKE_PG13
1413 Wake-Up priority 0(low) 1(high)
1415 config PM_BFIN_WAKE_USB
1416 bool "Allow Wake-Up from (USB)"
1417 depends on PM && BF60x
1420 Enable (USB) Wake-up
1422 config PM_BFIN_WAKE_USB_POL
1423 int "Wake-up priority"
1424 depends on PM_BFIN_WAKE_USB
1427 Wake-Up priority 0(low) 1(high)
1431 menu "CPU Frequency scaling"
1433 source "drivers/cpufreq/Kconfig"
1435 config BFIN_CPU_FREQ
1438 select CPU_FREQ_TABLE
1442 bool "CPU Voltage scaling"
1443 depends on EXPERIMENTAL
1447 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1448 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1449 manuals. There is a theoretical risk that during VDDINT transitions
1454 source "net/Kconfig"
1456 source "drivers/Kconfig"
1458 source "drivers/firmware/Kconfig"
1462 source "arch/blackfin/Kconfig.debug"
1464 source "security/Kconfig"
1466 source "crypto/Kconfig"
1468 source "lib/Kconfig"