2 * Copyright (C) 2005-2006 Atmel Corporation
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/sections.h>
11 #include <asm/sysreg.h>
13 #include <asm/arch/clk.h>
14 #include <asm/arch/hardware.h>
19 #if (CONFIG_SYS_CLKDIV_CPU > CONFIG_SYS_CLKDIV_HSB) \
20 || (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBA) \
21 || (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBB)
22 # error Constraint fCPU >= fHSB >= fPB{A,B} violated
24 #if defined(CONFIG_PLL) && ((CONFIG_SYS_PLL0_MUL < 1) || (CONFIG_SYS_PLL0_DIV < 1))
25 # error Invalid PLL multiplier and/or divider
28 DECLARE_GLOBAL_DATA_PTR;
30 int arch_cpu_init(void)
32 extern void _evba(void);
34 gd->arch.cpu_hz = CONFIG_SYS_OSC0_HZ;
36 /* TODO: Move somewhere else, but needs to be run before we
37 * increase the clock frequency. */
38 hsmc3_writel(MODE0, 0x00031103);
39 hsmc3_writel(CYCLE0, 0x000c000d);
40 hsmc3_writel(PULSE0, 0x0b0a0906);
41 hsmc3_writel(SETUP0, 0x00010002);
45 /* Update the CPU speed according to the PLL configuration */
46 gd->arch.cpu_hz = get_cpu_clk_rate();
48 /* Set up the exception handler table and enable exceptions */
49 sysreg_write(EVBA, (unsigned long)&_evba);
50 asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET));
55 void prepare_to_boot(void)
57 /* Flush both caches and the write buffer */
58 asm volatile("cache %0[4], 010\n\t"
59 "cache %0[0], 000\n\t"
60 "sync 0" : : "r"(0) : "memory");
63 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
65 /* This will reset the CPU core, caches, MMU and all internal busses */
66 __builtin_mtdr(8, 1 << 13); /* set DC:DBE */
67 __builtin_mtdr(8, 1 << 30); /* set DC:RES */
69 /* Flush the pipeline before we declare it a failure */
70 asm volatile("sub pc, pc, -4");