1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Based on arch/arm/mm/proc.S
5 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * Copyright (C) 2012 ARM Ltd.
7 * Author: Catalin Marinas <catalin.marinas@arm.com>
10 #include <linux/init.h>
11 #include <linux/linkage.h>
12 #include <linux/pgtable.h>
13 #include <asm/assembler.h>
14 #include <asm/asm-offsets.h>
15 #include <asm/asm_pointer_auth.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/cpufeature.h>
19 #include <asm/alternative.h>
22 #ifdef CONFIG_ARM64_64K_PAGES
23 #define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K
24 #elif defined(CONFIG_ARM64_16K_PAGES)
25 #define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K
26 #else /* CONFIG_ARM64_4K_PAGES */
27 #define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K
30 #ifdef CONFIG_RANDOMIZE_BASE
31 #define TCR_KASLR_FLAGS TCR_NFD1
33 #define TCR_KASLR_FLAGS 0
36 #define TCR_SMP_FLAGS TCR_SHARED
38 /* PTWs cacheable, inner/outer WBWA */
39 #define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
41 #ifdef CONFIG_KASAN_SW_TAGS
42 #define TCR_KASAN_FLAGS TCR_TBI1
44 #define TCR_KASAN_FLAGS 0
47 /* Default MAIR_EL1 */
48 #define MAIR_EL1_SET \
49 (MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) | \
50 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) | \
51 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) | \
52 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) | \
53 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) | \
54 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT))
58 * cpu_do_suspend - save CPU registers context
60 * x0: virtual address of context pointer
62 * This must be kept in sync with struct cpu_suspend_ctx in <asm/suspend.h>.
64 SYM_FUNC_START(cpu_do_suspend)
67 mrs x4, contextidr_el1
75 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
85 stp x10, x11, [x0, #64]
86 stp x12, x13, [x0, #80]
88 * Save x18 as it may be used as a platform register, e.g. by shadow
93 SYM_FUNC_END(cpu_do_suspend)
96 * cpu_do_resume - restore CPU register context
98 * x0: Address of context pointer
100 .pushsection ".idmap.text", "awx"
101 SYM_FUNC_START(cpu_do_resume)
103 ldp x4, x5, [x0, #16]
104 ldp x6, x8, [x0, #32]
105 ldp x9, x10, [x0, #48]
106 ldp x11, x12, [x0, #64]
107 ldp x13, x14, [x0, #80]
109 * Restore x18, as it may be used as a platform register, and clear
110 * the buffer to minimize the risk of exposure when used for shadow
117 msr contextidr_el1, x4
120 /* Don't change t0sz here, mask those bits when restoring */
122 bfi x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
128 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
129 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
130 * exception. Mask them until local_daif_restore() in cpu_suspend()
137 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
144 * Restore oslsr_el1 by writing oslar_el1
147 ubfx x11, x11, #1, #1
149 reset_pmuserenr_el0 x0 // Disable PMU access from EL0
150 reset_amuserenr_el0 x0 // Disable AMU access from EL0
152 alternative_if ARM64_HAS_RAS_EXTN
153 msr_s SYS_DISR_EL1, xzr
154 alternative_else_nop_endif
156 ptrauth_keys_install_kernel_nosync x14, x1, x2, x3
159 SYM_FUNC_END(cpu_do_resume)
163 .pushsection ".idmap.text", "awx"
165 .macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
166 adrp \tmp1, empty_zero_page
167 phys_to_ttbr \tmp2, \tmp1
168 offset_ttbr1 \tmp2, \tmp1
177 * void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1)
179 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
180 * called by anything else. It can only be executed from a TTBR0 mapping.
182 SYM_FUNC_START(idmap_cpu_replace_ttbr1)
183 save_and_disable_daif flags=x2
185 __idmap_cpu_set_reserved_ttbr1 x1, x3
194 SYM_FUNC_END(idmap_cpu_replace_ttbr1)
197 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
198 .pushsection ".idmap.text", "awx"
200 .macro __idmap_kpti_get_pgtable_ent, type
201 dc cvac, cur_\()\type\()p // Ensure any existing dirty
202 dmb sy // lines are written back before
203 ldr \type, [cur_\()\type\()p] // loading the entry
204 tbz \type, #0, skip_\()\type // Skip invalid and
205 tbnz \type, #11, skip_\()\type // non-global entries
208 .macro __idmap_kpti_put_pgtable_ent_ng, type
209 orr \type, \type, #PTE_NG // Same bit for blocks and pages
210 str \type, [cur_\()\type\()p] // Update the entry and ensure
211 dmb sy // that it is visible to all
212 dc civac, cur_\()\type\()p // CPUs.
216 * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
218 * Called exactly once from stop_machine context by each CPU found during boot.
222 SYM_FUNC_START(idmap_kpti_install_ng_mappings)
241 mrs swapper_ttb, ttbr1_el1
242 restore_ttbr1 swapper_ttb
243 adr flag_ptr, __idmap_kpti_flag
245 cbnz cpu, __idmap_kpti_secondary
247 /* We're the boot CPU. Wait for the others to catch up */
250 ldaxr w17, [flag_ptr]
251 eor w17, w17, num_cpus
254 /* We need to walk swapper, so turn off the MMU. */
255 pre_disable_mmu_workaround
257 bic x17, x17, #SCTLR_ELx_M
261 /* Everybody is enjoying the idmap, so we can rewrite swapper. */
263 mov cur_pgdp, swapper_pa
264 add end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
265 do_pgd: __idmap_kpti_get_pgtable_ent pgd
266 tbnz pgd, #1, walk_puds
268 __idmap_kpti_put_pgtable_ent_ng pgd
270 add cur_pgdp, cur_pgdp, #8
271 cmp cur_pgdp, end_pgdp
274 /* Publish the updated tables and nuke all the TLBs */
280 /* We're done: fire up the MMU again */
282 orr x17, x17, #SCTLR_ELx_M
287 * Invalidate the local I-cache so that any instructions fetched
288 * speculatively from the PoC are discarded, since they may have
289 * been dynamically patched at the PoU.
295 /* Set the flag to zero to indicate that we're all done */
301 .if CONFIG_PGTABLE_LEVELS > 3
302 pte_to_phys cur_pudp, pgd
303 add end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
304 do_pud: __idmap_kpti_get_pgtable_ent pud
305 tbnz pud, #1, walk_pmds
307 __idmap_kpti_put_pgtable_ent_ng pud
309 add cur_pudp, cur_pudp, 8
310 cmp cur_pudp, end_pudp
313 .else /* CONFIG_PGTABLE_LEVELS <= 3 */
322 .if CONFIG_PGTABLE_LEVELS > 2
323 pte_to_phys cur_pmdp, pud
324 add end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
325 do_pmd: __idmap_kpti_get_pgtable_ent pmd
326 tbnz pmd, #1, walk_ptes
328 __idmap_kpti_put_pgtable_ent_ng pmd
330 add cur_pmdp, cur_pmdp, #8
331 cmp cur_pmdp, end_pmdp
334 .else /* CONFIG_PGTABLE_LEVELS <= 2 */
343 pte_to_phys cur_ptep, pmd
344 add end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
345 do_pte: __idmap_kpti_get_pgtable_ent pte
346 __idmap_kpti_put_pgtable_ent_ng pte
348 add cur_ptep, cur_ptep, #8
349 cmp cur_ptep, end_ptep
369 /* Secondary CPUs end up here */
370 __idmap_kpti_secondary:
371 /* Uninstall swapper before surgery begins */
372 __idmap_cpu_set_reserved_ttbr1 x16, x17
374 /* Increment the flag to let the boot CPU we're ready */
375 1: ldxr w16, [flag_ptr]
377 stxr w17, w16, [flag_ptr]
380 /* Wait for the boot CPU to finish messing around with swapper */
386 /* All done, act like nothing happened */
387 offset_ttbr1 swapper_ttb, x16
388 msr ttbr1_el1, swapper_ttb
394 SYM_FUNC_END(idmap_kpti_install_ng_mappings)
401 * Initialise the processor for turning the MMU on.
404 * Return in x0 the value of the SCTLR_EL1 register.
406 .pushsection ".idmap.text", "awx"
407 SYM_FUNC_START(__cpu_setup)
408 tlbi vmalle1 // Invalidate local TLB
412 msr cpacr_el1, x1 // Enable FP/ASIMD
413 mov x1, #1 << 12 // Reset mdscr_el1 and disable
414 msr mdscr_el1, x1 // access to the DCC from EL0
415 isb // Unmask debug exceptions now,
416 enable_dbg // since this is per-cpu
417 reset_pmuserenr_el0 x1 // Disable PMU access from EL0
418 reset_amuserenr_el0 x1 // Disable AMU access from EL0
421 * Memory region attributes
423 mov_q x5, MAIR_EL1_SET
426 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
427 * both user and kernel.
429 mov_q x10, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
430 TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
431 TCR_TBI0 | TCR_A1 | TCR_KASAN_FLAGS
432 tcr_clear_errata_bits x10, x9, x5
434 #ifdef CONFIG_ARM64_VA_BITS_52
435 ldr_l x9, vabits_actual
445 * Set the IPS bits in TCR_EL1.
447 tcr_compute_pa_size x10, #TCR_IPS_SHIFT, x5, x6
448 #ifdef CONFIG_ARM64_HW_AFDBM
450 * Enable hardware update of the Access Flags bit.
451 * Hardware dirty bit management is enabled later,
454 mrs x9, ID_AA64MMFR1_EL1
457 orr x10, x10, #TCR_HA // hardware Access flag update
459 #endif /* CONFIG_ARM64_HW_AFDBM */
464 mov_q x0, SCTLR_EL1_SET
465 ret // return to head.S
466 SYM_FUNC_END(__cpu_setup)