1 // SPDX-License-Identifier: GPL-2.0-only
3 * Based on arch/arm/mm/fault.c
5 * Copyright (C) 1995 Linus Torvalds
6 * Copyright (C) 1995-2004 Russell King
7 * Copyright (C) 2012 ARM Ltd.
10 #include <linux/acpi.h>
11 #include <linux/bitfield.h>
12 #include <linux/extable.h>
13 #include <linux/signal.h>
15 #include <linux/hardirq.h>
16 #include <linux/init.h>
17 #include <linux/kasan.h>
18 #include <linux/kprobes.h>
19 #include <linux/uaccess.h>
20 #include <linux/page-flags.h>
21 #include <linux/sched/signal.h>
22 #include <linux/sched/debug.h>
23 #include <linux/highmem.h>
24 #include <linux/perf_event.h>
25 #include <linux/preempt.h>
26 #include <linux/hugetlb.h>
30 #include <asm/cmpxchg.h>
31 #include <asm/cpufeature.h>
32 #include <asm/exception.h>
33 #include <asm/daifflags.h>
34 #include <asm/debug-monitors.h>
36 #include <asm/kprobes.h>
38 #include <asm/processor.h>
39 #include <asm/sysreg.h>
40 #include <asm/system_misc.h>
41 #include <asm/tlbflush.h>
42 #include <asm/traps.h>
45 int (*fn)(unsigned long far, unsigned int esr,
46 struct pt_regs *regs);
52 static const struct fault_info fault_info[];
53 static struct fault_info debug_fault_info[];
55 static inline const struct fault_info *esr_to_fault_info(unsigned int esr)
57 return fault_info + (esr & ESR_ELx_FSC);
60 static inline const struct fault_info *esr_to_debug_fault_info(unsigned int esr)
62 return debug_fault_info + DBG_ESR_EVT(esr);
65 static void data_abort_decode(unsigned int esr)
67 pr_alert("Data abort info:\n");
69 if (esr & ESR_ELx_ISV) {
70 pr_alert(" Access size = %u byte(s)\n",
71 1U << ((esr & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT));
72 pr_alert(" SSE = %lu, SRT = %lu\n",
73 (esr & ESR_ELx_SSE) >> ESR_ELx_SSE_SHIFT,
74 (esr & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT);
75 pr_alert(" SF = %lu, AR = %lu\n",
76 (esr & ESR_ELx_SF) >> ESR_ELx_SF_SHIFT,
77 (esr & ESR_ELx_AR) >> ESR_ELx_AR_SHIFT);
79 pr_alert(" ISV = 0, ISS = 0x%08lx\n", esr & ESR_ELx_ISS_MASK);
82 pr_alert(" CM = %lu, WnR = %lu\n",
83 (esr & ESR_ELx_CM) >> ESR_ELx_CM_SHIFT,
84 (esr & ESR_ELx_WNR) >> ESR_ELx_WNR_SHIFT);
87 static void mem_abort_decode(unsigned int esr)
89 pr_alert("Mem abort info:\n");
91 pr_alert(" ESR = 0x%08x\n", esr);
92 pr_alert(" EC = 0x%02lx: %s, IL = %u bits\n",
93 ESR_ELx_EC(esr), esr_get_class_string(esr),
94 (esr & ESR_ELx_IL) ? 32 : 16);
95 pr_alert(" SET = %lu, FnV = %lu\n",
96 (esr & ESR_ELx_SET_MASK) >> ESR_ELx_SET_SHIFT,
97 (esr & ESR_ELx_FnV) >> ESR_ELx_FnV_SHIFT);
98 pr_alert(" EA = %lu, S1PTW = %lu\n",
99 (esr & ESR_ELx_EA) >> ESR_ELx_EA_SHIFT,
100 (esr & ESR_ELx_S1PTW) >> ESR_ELx_S1PTW_SHIFT);
102 if (esr_is_data_abort(esr))
103 data_abort_decode(esr);
106 static inline unsigned long mm_to_pgd_phys(struct mm_struct *mm)
108 /* Either init_pg_dir or swapper_pg_dir */
110 return __pa_symbol(mm->pgd);
112 return (unsigned long)virt_to_phys(mm->pgd);
116 * Dump out the page tables associated with 'addr' in the currently active mm.
118 static void show_pte(unsigned long addr)
120 struct mm_struct *mm;
124 if (is_ttbr0_addr(addr)) {
126 mm = current->active_mm;
127 if (mm == &init_mm) {
128 pr_alert("[%016lx] user address but active_mm is swapper\n",
132 } else if (is_ttbr1_addr(addr)) {
136 pr_alert("[%016lx] address between user and kernel address ranges\n",
141 pr_alert("%s pgtable: %luk pages, %llu-bit VAs, pgdp=%016lx\n",
142 mm == &init_mm ? "swapper" : "user", PAGE_SIZE / SZ_1K,
143 vabits_actual, mm_to_pgd_phys(mm));
144 pgdp = pgd_offset(mm, addr);
145 pgd = READ_ONCE(*pgdp);
146 pr_alert("[%016lx] pgd=%016llx", addr, pgd_val(pgd));
154 if (pgd_none(pgd) || pgd_bad(pgd))
157 p4dp = p4d_offset(pgdp, addr);
158 p4d = READ_ONCE(*p4dp);
159 pr_cont(", p4d=%016llx", p4d_val(p4d));
160 if (p4d_none(p4d) || p4d_bad(p4d))
163 pudp = pud_offset(p4dp, addr);
164 pud = READ_ONCE(*pudp);
165 pr_cont(", pud=%016llx", pud_val(pud));
166 if (pud_none(pud) || pud_bad(pud))
169 pmdp = pmd_offset(pudp, addr);
170 pmd = READ_ONCE(*pmdp);
171 pr_cont(", pmd=%016llx", pmd_val(pmd));
172 if (pmd_none(pmd) || pmd_bad(pmd))
175 ptep = pte_offset_map(pmdp, addr);
176 pte = READ_ONCE(*ptep);
177 pr_cont(", pte=%016llx", pte_val(pte));
185 * This function sets the access flags (dirty, accessed), as well as write
186 * permission, and only to a more permissive setting.
188 * It needs to cope with hardware update of the accessed/dirty state by other
189 * agents in the system and can safely skip the __sync_icache_dcache() call as,
190 * like set_pte_at(), the PTE is never changed from no-exec to exec here.
192 * Returns whether or not the PTE actually changed.
194 int ptep_set_access_flags(struct vm_area_struct *vma,
195 unsigned long address, pte_t *ptep,
196 pte_t entry, int dirty)
198 pteval_t old_pteval, pteval;
199 pte_t pte = READ_ONCE(*ptep);
201 if (pte_same(pte, entry))
204 /* only preserve the access flags and write permission */
205 pte_val(entry) &= PTE_RDONLY | PTE_AF | PTE_WRITE | PTE_DIRTY;
208 * Setting the flags must be done atomically to avoid racing with the
209 * hardware update of the access/dirty state. The PTE_RDONLY bit must
210 * be set to the most permissive (lowest value) of *ptep and entry
211 * (calculated as: a & b == ~(~a | ~b)).
213 pte_val(entry) ^= PTE_RDONLY;
214 pteval = pte_val(pte);
217 pteval ^= PTE_RDONLY;
218 pteval |= pte_val(entry);
219 pteval ^= PTE_RDONLY;
220 pteval = cmpxchg_relaxed(&pte_val(*ptep), old_pteval, pteval);
221 } while (pteval != old_pteval);
223 /* Invalidate a stale read-only entry */
225 flush_tlb_page(vma, address);
229 static bool is_el1_instruction_abort(unsigned int esr)
231 return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_CUR;
234 static inline bool is_el1_permission_fault(unsigned long addr, unsigned int esr,
235 struct pt_regs *regs)
237 unsigned int ec = ESR_ELx_EC(esr);
238 unsigned int fsc_type = esr & ESR_ELx_FSC_TYPE;
240 if (ec != ESR_ELx_EC_DABT_CUR && ec != ESR_ELx_EC_IABT_CUR)
243 if (fsc_type == ESR_ELx_FSC_PERM)
246 if (is_ttbr0_addr(addr) && system_uses_ttbr0_pan())
247 return fsc_type == ESR_ELx_FSC_FAULT &&
248 (regs->pstate & PSR_PAN_BIT);
253 static bool __kprobes is_spurious_el1_translation_fault(unsigned long addr,
255 struct pt_regs *regs)
260 if (ESR_ELx_EC(esr) != ESR_ELx_EC_DABT_CUR ||
261 (esr & ESR_ELx_FSC_TYPE) != ESR_ELx_FSC_FAULT)
264 local_irq_save(flags);
265 asm volatile("at s1e1r, %0" :: "r" (addr));
267 par = read_sysreg_par();
268 local_irq_restore(flags);
271 * If we now have a valid translation, treat the translation fault as
274 if (!(par & SYS_PAR_EL1_F))
278 * If we got a different type of fault from the AT instruction,
279 * treat the translation fault as spurious.
281 dfsc = FIELD_GET(SYS_PAR_EL1_FST, par);
282 return (dfsc & ESR_ELx_FSC_TYPE) != ESR_ELx_FSC_FAULT;
285 static void die_kernel_fault(const char *msg, unsigned long addr,
286 unsigned int esr, struct pt_regs *regs)
290 pr_alert("Unable to handle kernel %s at virtual address %016lx\n", msg,
293 mem_abort_decode(esr);
296 die("Oops", regs, esr);
301 #ifdef CONFIG_KASAN_HW_TAGS
302 static void report_tag_fault(unsigned long addr, unsigned int esr,
303 struct pt_regs *regs)
305 bool is_write = ((esr & ESR_ELx_WNR) >> ESR_ELx_WNR_SHIFT) != 0;
308 * SAS bits aren't set for all faults reported in EL1, so we can't
309 * find out access size.
311 kasan_report(addr, 0, is_write, regs->pc);
314 /* Tag faults aren't enabled without CONFIG_KASAN_HW_TAGS. */
315 static inline void report_tag_fault(unsigned long addr, unsigned int esr,
316 struct pt_regs *regs) { }
319 static void do_tag_recovery(unsigned long addr, unsigned int esr,
320 struct pt_regs *regs)
322 static bool reported;
324 if (!READ_ONCE(reported)) {
325 report_tag_fault(addr, esr, regs);
326 WRITE_ONCE(reported, true);
330 * Disable MTE Tag Checking on the local CPU for the current EL.
331 * It will be done lazily on the other CPUs when they will hit a
334 sysreg_clear_set(sctlr_el1, SCTLR_ELx_TCF_MASK, SCTLR_ELx_TCF_NONE);
338 static bool is_el1_mte_sync_tag_check_fault(unsigned int esr)
340 unsigned int ec = ESR_ELx_EC(esr);
341 unsigned int fsc = esr & ESR_ELx_FSC;
343 if (ec != ESR_ELx_EC_DABT_CUR)
346 if (fsc == ESR_ELx_FSC_MTE)
352 static void __do_kernel_fault(unsigned long addr, unsigned int esr,
353 struct pt_regs *regs)
358 * Are we prepared to handle this kernel fault?
359 * We are almost certainly not prepared to handle instruction faults.
361 if (!is_el1_instruction_abort(esr) && fixup_exception(regs))
364 if (WARN_RATELIMIT(is_spurious_el1_translation_fault(addr, esr, regs),
365 "Ignoring spurious kernel translation fault at virtual address %016lx\n", addr))
368 if (is_el1_mte_sync_tag_check_fault(esr)) {
369 do_tag_recovery(addr, esr, regs);
374 if (is_el1_permission_fault(addr, esr, regs)) {
375 if (esr & ESR_ELx_WNR)
376 msg = "write to read-only memory";
377 else if (is_el1_instruction_abort(esr))
378 msg = "execute from non-executable memory";
380 msg = "read from unreadable memory";
381 } else if (addr < PAGE_SIZE) {
382 msg = "NULL pointer dereference";
384 msg = "paging request";
387 die_kernel_fault(msg, addr, esr, regs);
390 static void set_thread_esr(unsigned long address, unsigned int esr)
392 current->thread.fault_address = address;
395 * If the faulting address is in the kernel, we must sanitize the ESR.
396 * From userspace's point of view, kernel-only mappings don't exist
397 * at all, so we report them as level 0 translation faults.
398 * (This is not quite the way that "no mapping there at all" behaves:
399 * an alignment fault not caused by the memory type would take
400 * precedence over translation fault for a real access to empty
401 * space. Unfortunately we can't easily distinguish "alignment fault
402 * not caused by memory type" from "alignment fault caused by memory
403 * type", so we ignore this wrinkle and just return the translation
406 if (!is_ttbr0_addr(current->thread.fault_address)) {
407 switch (ESR_ELx_EC(esr)) {
408 case ESR_ELx_EC_DABT_LOW:
410 * These bits provide only information about the
411 * faulting instruction, which userspace knows already.
412 * We explicitly clear bits which are architecturally
413 * RES0 in case they are given meanings in future.
414 * We always report the ESR as if the fault was taken
415 * to EL1 and so ISV and the bits in ISS[23:14] are
416 * clear. (In fact it always will be a fault to EL1.)
418 esr &= ESR_ELx_EC_MASK | ESR_ELx_IL |
419 ESR_ELx_CM | ESR_ELx_WNR;
420 esr |= ESR_ELx_FSC_FAULT;
422 case ESR_ELx_EC_IABT_LOW:
424 * Claim a level 0 translation fault.
425 * All other bits are architecturally RES0 for faults
426 * reported with that DFSC value, so we clear them.
428 esr &= ESR_ELx_EC_MASK | ESR_ELx_IL;
429 esr |= ESR_ELx_FSC_FAULT;
433 * This should never happen (entry.S only brings us
434 * into this code for insn and data aborts from a lower
435 * exception level). Fail safe by not providing an ESR
436 * context record at all.
438 WARN(1, "ESR 0x%x is not DABT or IABT from EL0\n", esr);
444 current->thread.fault_code = esr;
447 static void do_bad_area(unsigned long far, unsigned int esr,
448 struct pt_regs *regs)
450 unsigned long addr = untagged_addr(far);
453 * If we are in kernel mode at this point, we have no context to
454 * handle this fault with.
456 if (user_mode(regs)) {
457 const struct fault_info *inf = esr_to_fault_info(esr);
459 set_thread_esr(addr, esr);
460 arm64_force_sig_fault(inf->sig, inf->code, far, inf->name);
462 __do_kernel_fault(addr, esr, regs);
466 #define VM_FAULT_BADMAP 0x010000
467 #define VM_FAULT_BADACCESS 0x020000
469 static vm_fault_t __do_page_fault(struct mm_struct *mm, unsigned long addr,
470 unsigned int mm_flags, unsigned long vm_flags,
471 struct pt_regs *regs)
473 struct vm_area_struct *vma = find_vma(mm, addr);
476 return VM_FAULT_BADMAP;
479 * Ok, we have a good vm_area for this memory access, so we can handle
482 if (unlikely(vma->vm_start > addr)) {
483 if (!(vma->vm_flags & VM_GROWSDOWN))
484 return VM_FAULT_BADMAP;
485 if (expand_stack(vma, addr))
486 return VM_FAULT_BADMAP;
490 * Check that the permissions on the VMA allow for the fault which
493 if (!(vma->vm_flags & vm_flags))
494 return VM_FAULT_BADACCESS;
495 return handle_mm_fault(vma, addr & PAGE_MASK, mm_flags, regs);
498 static bool is_el0_instruction_abort(unsigned int esr)
500 return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_LOW;
504 * Note: not valid for EL1 DC IVAC, but we never use that such that it
505 * should fault. EL0 cannot issue DC IVAC (undef).
507 static bool is_write_abort(unsigned int esr)
509 return (esr & ESR_ELx_WNR) && !(esr & ESR_ELx_CM);
512 static int __kprobes do_page_fault(unsigned long far, unsigned int esr,
513 struct pt_regs *regs)
515 const struct fault_info *inf;
516 struct mm_struct *mm = current->mm;
518 unsigned long vm_flags = VM_ACCESS_FLAGS;
519 unsigned int mm_flags = FAULT_FLAG_DEFAULT;
520 unsigned long addr = untagged_addr(far);
522 if (kprobe_page_fault(regs, esr))
526 * If we're in an interrupt or have no user context, we must not take
529 if (faulthandler_disabled() || !mm)
533 mm_flags |= FAULT_FLAG_USER;
535 if (is_el0_instruction_abort(esr)) {
537 mm_flags |= FAULT_FLAG_INSTRUCTION;
538 } else if (is_write_abort(esr)) {
540 mm_flags |= FAULT_FLAG_WRITE;
543 if (is_ttbr0_addr(addr) && is_el1_permission_fault(addr, esr, regs)) {
544 if (is_el1_instruction_abort(esr))
545 die_kernel_fault("execution of user memory",
548 if (!search_exception_tables(regs->pc))
549 die_kernel_fault("access to user memory outside uaccess routines",
553 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr);
556 * As per x86, we may deadlock here. However, since the kernel only
557 * validly references user space from well defined areas of the code,
558 * we can bug out early if this is from code which shouldn't.
560 if (!mmap_read_trylock(mm)) {
561 if (!user_mode(regs) && !search_exception_tables(regs->pc))
567 * The above mmap_read_trylock() might have succeeded in which
568 * case, we'll have missed the might_sleep() from down_read().
571 #ifdef CONFIG_DEBUG_VM
572 if (!user_mode(regs) && !search_exception_tables(regs->pc)) {
573 mmap_read_unlock(mm);
579 fault = __do_page_fault(mm, addr, mm_flags, vm_flags, regs);
581 /* Quick path to respond to signals */
582 if (fault_signal_pending(fault, regs)) {
583 if (!user_mode(regs))
588 if (fault & VM_FAULT_RETRY) {
589 if (mm_flags & FAULT_FLAG_ALLOW_RETRY) {
590 mm_flags |= FAULT_FLAG_TRIED;
594 mmap_read_unlock(mm);
597 * Handle the "normal" (no error) case first.
599 if (likely(!(fault & (VM_FAULT_ERROR | VM_FAULT_BADMAP |
600 VM_FAULT_BADACCESS))))
604 * If we are in kernel mode at this point, we have no context to
605 * handle this fault with.
607 if (!user_mode(regs))
610 if (fault & VM_FAULT_OOM) {
612 * We ran out of memory, call the OOM killer, and return to
613 * userspace (which will retry the fault, or kill us if we got
616 pagefault_out_of_memory();
620 inf = esr_to_fault_info(esr);
621 set_thread_esr(addr, esr);
622 if (fault & VM_FAULT_SIGBUS) {
624 * We had some memory, but were unable to successfully fix up
627 arm64_force_sig_fault(SIGBUS, BUS_ADRERR, far, inf->name);
628 } else if (fault & (VM_FAULT_HWPOISON_LARGE | VM_FAULT_HWPOISON)) {
632 if (fault & VM_FAULT_HWPOISON_LARGE)
633 lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault));
635 arm64_force_sig_mceerr(BUS_MCEERR_AR, far, lsb, inf->name);
638 * Something tried to access memory that isn't in our memory
641 arm64_force_sig_fault(SIGSEGV,
642 fault == VM_FAULT_BADACCESS ? SEGV_ACCERR : SEGV_MAPERR,
649 __do_kernel_fault(addr, esr, regs);
653 static int __kprobes do_translation_fault(unsigned long far,
655 struct pt_regs *regs)
657 unsigned long addr = untagged_addr(far);
659 if (is_ttbr0_addr(addr))
660 return do_page_fault(far, esr, regs);
662 do_bad_area(far, esr, regs);
666 static int do_alignment_fault(unsigned long far, unsigned int esr,
667 struct pt_regs *regs)
669 do_bad_area(far, esr, regs);
673 static int do_bad(unsigned long far, unsigned int esr, struct pt_regs *regs)
675 return 1; /* "fault" */
678 static int do_sea(unsigned long far, unsigned int esr, struct pt_regs *regs)
680 const struct fault_info *inf;
681 unsigned long siaddr;
683 inf = esr_to_fault_info(esr);
685 if (user_mode(regs) && apei_claim_sea(regs) == 0) {
687 * APEI claimed this as a firmware-first notification.
688 * Some processing deferred to task_work before ret_to_user().
693 if (esr & ESR_ELx_FnV) {
697 * The architecture specifies that the tag bits of FAR_EL1 are
698 * UNKNOWN for synchronous external aborts. Mask them out now
699 * so that userspace doesn't see them.
701 siaddr = untagged_addr(far);
703 arm64_notify_die(inf->name, regs, inf->sig, inf->code, siaddr, esr);
708 static int do_tag_check_fault(unsigned long far, unsigned int esr,
709 struct pt_regs *regs)
712 * The architecture specifies that bits 63:60 of FAR_EL1 are UNKNOWN
713 * for tag check faults. Set them to corresponding bits in the untagged
716 far = (__untagged_addr(far) & ~MTE_TAG_MASK) | (far & MTE_TAG_MASK);
717 do_bad_area(far, esr, regs);
721 static const struct fault_info fault_info[] = {
722 { do_bad, SIGKILL, SI_KERNEL, "ttbr address size fault" },
723 { do_bad, SIGKILL, SI_KERNEL, "level 1 address size fault" },
724 { do_bad, SIGKILL, SI_KERNEL, "level 2 address size fault" },
725 { do_bad, SIGKILL, SI_KERNEL, "level 3 address size fault" },
726 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 0 translation fault" },
727 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" },
728 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" },
729 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" },
730 { do_bad, SIGKILL, SI_KERNEL, "unknown 8" },
731 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 access flag fault" },
732 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 access flag fault" },
733 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 access flag fault" },
734 { do_bad, SIGKILL, SI_KERNEL, "unknown 12" },
735 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 permission fault" },
736 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 permission fault" },
737 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 permission fault" },
738 { do_sea, SIGBUS, BUS_OBJERR, "synchronous external abort" },
739 { do_tag_check_fault, SIGSEGV, SEGV_MTESERR, "synchronous tag check fault" },
740 { do_bad, SIGKILL, SI_KERNEL, "unknown 18" },
741 { do_bad, SIGKILL, SI_KERNEL, "unknown 19" },
742 { do_sea, SIGKILL, SI_KERNEL, "level 0 (translation table walk)" },
743 { do_sea, SIGKILL, SI_KERNEL, "level 1 (translation table walk)" },
744 { do_sea, SIGKILL, SI_KERNEL, "level 2 (translation table walk)" },
745 { do_sea, SIGKILL, SI_KERNEL, "level 3 (translation table walk)" },
746 { do_sea, SIGBUS, BUS_OBJERR, "synchronous parity or ECC error" }, // Reserved when RAS is implemented
747 { do_bad, SIGKILL, SI_KERNEL, "unknown 25" },
748 { do_bad, SIGKILL, SI_KERNEL, "unknown 26" },
749 { do_bad, SIGKILL, SI_KERNEL, "unknown 27" },
750 { do_sea, SIGKILL, SI_KERNEL, "level 0 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented
751 { do_sea, SIGKILL, SI_KERNEL, "level 1 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented
752 { do_sea, SIGKILL, SI_KERNEL, "level 2 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented
753 { do_sea, SIGKILL, SI_KERNEL, "level 3 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented
754 { do_bad, SIGKILL, SI_KERNEL, "unknown 32" },
755 { do_alignment_fault, SIGBUS, BUS_ADRALN, "alignment fault" },
756 { do_bad, SIGKILL, SI_KERNEL, "unknown 34" },
757 { do_bad, SIGKILL, SI_KERNEL, "unknown 35" },
758 { do_bad, SIGKILL, SI_KERNEL, "unknown 36" },
759 { do_bad, SIGKILL, SI_KERNEL, "unknown 37" },
760 { do_bad, SIGKILL, SI_KERNEL, "unknown 38" },
761 { do_bad, SIGKILL, SI_KERNEL, "unknown 39" },
762 { do_bad, SIGKILL, SI_KERNEL, "unknown 40" },
763 { do_bad, SIGKILL, SI_KERNEL, "unknown 41" },
764 { do_bad, SIGKILL, SI_KERNEL, "unknown 42" },
765 { do_bad, SIGKILL, SI_KERNEL, "unknown 43" },
766 { do_bad, SIGKILL, SI_KERNEL, "unknown 44" },
767 { do_bad, SIGKILL, SI_KERNEL, "unknown 45" },
768 { do_bad, SIGKILL, SI_KERNEL, "unknown 46" },
769 { do_bad, SIGKILL, SI_KERNEL, "unknown 47" },
770 { do_bad, SIGKILL, SI_KERNEL, "TLB conflict abort" },
771 { do_bad, SIGKILL, SI_KERNEL, "Unsupported atomic hardware update fault" },
772 { do_bad, SIGKILL, SI_KERNEL, "unknown 50" },
773 { do_bad, SIGKILL, SI_KERNEL, "unknown 51" },
774 { do_bad, SIGKILL, SI_KERNEL, "implementation fault (lockdown abort)" },
775 { do_bad, SIGBUS, BUS_OBJERR, "implementation fault (unsupported exclusive)" },
776 { do_bad, SIGKILL, SI_KERNEL, "unknown 54" },
777 { do_bad, SIGKILL, SI_KERNEL, "unknown 55" },
778 { do_bad, SIGKILL, SI_KERNEL, "unknown 56" },
779 { do_bad, SIGKILL, SI_KERNEL, "unknown 57" },
780 { do_bad, SIGKILL, SI_KERNEL, "unknown 58" },
781 { do_bad, SIGKILL, SI_KERNEL, "unknown 59" },
782 { do_bad, SIGKILL, SI_KERNEL, "unknown 60" },
783 { do_bad, SIGKILL, SI_KERNEL, "section domain fault" },
784 { do_bad, SIGKILL, SI_KERNEL, "page domain fault" },
785 { do_bad, SIGKILL, SI_KERNEL, "unknown 63" },
788 void do_mem_abort(unsigned long far, unsigned int esr, struct pt_regs *regs)
790 const struct fault_info *inf = esr_to_fault_info(esr);
791 unsigned long addr = untagged_addr(far);
793 if (!inf->fn(far, esr, regs))
796 if (!user_mode(regs)) {
797 pr_alert("Unhandled fault at 0x%016lx\n", addr);
798 mem_abort_decode(esr);
803 * At this point we have an unrecognized fault type whose tag bits may
804 * have been defined as UNKNOWN. Therefore we only expose the untagged
805 * address to the signal handler.
807 arm64_notify_die(inf->name, regs, inf->sig, inf->code, addr, esr);
809 NOKPROBE_SYMBOL(do_mem_abort);
811 void do_el0_irq_bp_hardening(void)
813 /* PC has already been checked in entry.S */
814 arm64_apply_bp_hardening();
816 NOKPROBE_SYMBOL(do_el0_irq_bp_hardening);
818 void do_sp_pc_abort(unsigned long addr, unsigned int esr, struct pt_regs *regs)
820 arm64_notify_die("SP/PC alignment exception", regs, SIGBUS, BUS_ADRALN,
823 NOKPROBE_SYMBOL(do_sp_pc_abort);
825 int __init early_brk64(unsigned long addr, unsigned int esr,
826 struct pt_regs *regs);
829 * __refdata because early_brk64 is __init, but the reference to it is
830 * clobbered at arch_initcall time.
831 * See traps.c and debug-monitors.c:debug_traps_init().
833 static struct fault_info __refdata debug_fault_info[] = {
834 { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware breakpoint" },
835 { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware single-step" },
836 { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware watchpoint" },
837 { do_bad, SIGKILL, SI_KERNEL, "unknown 3" },
838 { do_bad, SIGTRAP, TRAP_BRKPT, "aarch32 BKPT" },
839 { do_bad, SIGKILL, SI_KERNEL, "aarch32 vector catch" },
840 { early_brk64, SIGTRAP, TRAP_BRKPT, "aarch64 BRK" },
841 { do_bad, SIGKILL, SI_KERNEL, "unknown 7" },
844 void __init hook_debug_fault_code(int nr,
845 int (*fn)(unsigned long, unsigned int, struct pt_regs *),
846 int sig, int code, const char *name)
848 BUG_ON(nr < 0 || nr >= ARRAY_SIZE(debug_fault_info));
850 debug_fault_info[nr].fn = fn;
851 debug_fault_info[nr].sig = sig;
852 debug_fault_info[nr].code = code;
853 debug_fault_info[nr].name = name;
857 * In debug exception context, we explicitly disable preemption despite
858 * having interrupts disabled.
859 * This serves two purposes: it makes it much less likely that we would
860 * accidentally schedule in exception context and it will force a warning
861 * if we somehow manage to schedule by accident.
863 static void debug_exception_enter(struct pt_regs *regs)
867 /* This code is a bit fragile. Test it. */
868 RCU_LOCKDEP_WARN(!rcu_is_watching(), "exception_enter didn't work");
870 NOKPROBE_SYMBOL(debug_exception_enter);
872 static void debug_exception_exit(struct pt_regs *regs)
874 preempt_enable_no_resched();
876 NOKPROBE_SYMBOL(debug_exception_exit);
878 void do_debug_exception(unsigned long addr_if_watchpoint, unsigned int esr,
879 struct pt_regs *regs)
881 const struct fault_info *inf = esr_to_debug_fault_info(esr);
882 unsigned long pc = instruction_pointer(regs);
884 debug_exception_enter(regs);
886 if (user_mode(regs) && !is_ttbr0_addr(pc))
887 arm64_apply_bp_hardening();
889 if (inf->fn(addr_if_watchpoint, esr, regs)) {
890 arm64_notify_die(inf->name, regs, inf->sig, inf->code, pc, esr);
893 debug_exception_exit(regs);
895 NOKPROBE_SYMBOL(do_debug_exception);