1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2015 ARM Ltd.
6 * Author: Marc Zyngier <marc.zyngier@arm.com>
8 #include <linux/kvm_host.h>
9 #include <kvm/arm_vgic.h>
10 #include <linux/uaccess.h>
11 #include <asm/kvm_mmu.h>
12 #include <asm/cputype.h>
17 int vgic_check_iorange(struct kvm *kvm, phys_addr_t ioaddr,
18 phys_addr_t addr, phys_addr_t alignment,
21 if (!IS_VGIC_ADDR_UNDEF(ioaddr))
24 if (!IS_ALIGNED(addr, alignment) || !IS_ALIGNED(size, alignment))
27 if (addr + size < addr)
30 if (addr & ~kvm_phys_mask(kvm) || addr + size > kvm_phys_size(kvm))
36 static int vgic_check_type(struct kvm *kvm, int type_needed)
38 if (kvm->arch.vgic.vgic_model != type_needed)
44 int kvm_set_legacy_vgic_v2_addr(struct kvm *kvm, struct kvm_arm_device_addr *dev_addr)
46 struct vgic_dist *vgic = &kvm->arch.vgic;
49 mutex_lock(&kvm->arch.config_lock);
50 switch (FIELD_GET(KVM_ARM_DEVICE_TYPE_MASK, dev_addr->id)) {
51 case KVM_VGIC_V2_ADDR_TYPE_DIST:
52 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V2);
54 r = vgic_check_iorange(kvm, vgic->vgic_dist_base, dev_addr->addr,
55 SZ_4K, KVM_VGIC_V2_DIST_SIZE);
57 vgic->vgic_dist_base = dev_addr->addr;
59 case KVM_VGIC_V2_ADDR_TYPE_CPU:
60 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V2);
62 r = vgic_check_iorange(kvm, vgic->vgic_cpu_base, dev_addr->addr,
63 SZ_4K, KVM_VGIC_V2_CPU_SIZE);
65 vgic->vgic_cpu_base = dev_addr->addr;
71 mutex_unlock(&kvm->arch.config_lock);
77 * kvm_vgic_addr - set or get vgic VM base addresses
78 * @kvm: pointer to the vm struct
79 * @attr: pointer to the attribute being retrieved/updated
80 * @write: if true set the address in the VM address space, if false read the
83 * Set or get the vgic base addresses for the distributor and the virtual CPU
84 * interface in the VM physical address space. These addresses are properties
85 * of the emulated core/SoC and therefore user space initially knows this
87 * Check them for sanity (alignment, double assignment). We can't check for
88 * overlapping regions in case of a virtual GICv3 here, since we don't know
89 * the number of VCPUs yet, so we defer this check to map_resources().
91 static int kvm_vgic_addr(struct kvm *kvm, struct kvm_device_attr *attr, bool write)
93 u64 __user *uaddr = (u64 __user *)attr->addr;
94 struct vgic_dist *vgic = &kvm->arch.vgic;
95 phys_addr_t *addr_ptr, alignment, size;
96 u64 undef_value = VGIC_ADDR_UNDEF;
100 /* Reading a redistributor region addr implies getting the index */
101 if (write || attr->attr == KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION)
102 if (get_user(addr, uaddr))
105 mutex_lock(&kvm->arch.config_lock);
106 switch (attr->attr) {
107 case KVM_VGIC_V2_ADDR_TYPE_DIST:
108 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V2);
109 addr_ptr = &vgic->vgic_dist_base;
111 size = KVM_VGIC_V2_DIST_SIZE;
113 case KVM_VGIC_V2_ADDR_TYPE_CPU:
114 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V2);
115 addr_ptr = &vgic->vgic_cpu_base;
117 size = KVM_VGIC_V2_CPU_SIZE;
119 case KVM_VGIC_V3_ADDR_TYPE_DIST:
120 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V3);
121 addr_ptr = &vgic->vgic_dist_base;
123 size = KVM_VGIC_V3_DIST_SIZE;
125 case KVM_VGIC_V3_ADDR_TYPE_REDIST: {
126 struct vgic_redist_region *rdreg;
128 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V3);
132 r = vgic_v3_set_redist_base(kvm, 0, addr, 0);
135 rdreg = list_first_entry_or_null(&vgic->rd_regions,
136 struct vgic_redist_region, list);
138 addr_ptr = &undef_value;
140 addr_ptr = &rdreg->base;
143 case KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION:
145 struct vgic_redist_region *rdreg;
148 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V3);
152 index = addr & KVM_VGIC_V3_RDIST_INDEX_MASK;
155 gpa_t base = addr & KVM_VGIC_V3_RDIST_BASE_MASK;
156 u32 count = FIELD_GET(KVM_VGIC_V3_RDIST_COUNT_MASK, addr);
157 u8 flags = FIELD_GET(KVM_VGIC_V3_RDIST_FLAGS_MASK, addr);
162 r = vgic_v3_set_redist_base(kvm, index,
167 rdreg = vgic_v3_rdist_region_from_index(kvm, index);
175 addr |= (u64)rdreg->count << KVM_VGIC_V3_RDIST_COUNT_SHIFT;
186 r = vgic_check_iorange(kvm, *addr_ptr, addr, alignment, size);
194 mutex_unlock(&kvm->arch.config_lock);
197 r = put_user(addr, uaddr);
202 static int vgic_set_common_attr(struct kvm_device *dev,
203 struct kvm_device_attr *attr)
207 switch (attr->group) {
208 case KVM_DEV_ARM_VGIC_GRP_ADDR:
209 r = kvm_vgic_addr(dev->kvm, attr, true);
210 return (r == -ENODEV) ? -ENXIO : r;
211 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: {
212 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
216 if (get_user(val, uaddr))
221 * - at least 32 SPIs on top of the 16 SGIs and 16 PPIs
222 * - at most 1024 interrupts
223 * - a multiple of 32 interrupts
225 if (val < (VGIC_NR_PRIVATE_IRQS + 32) ||
226 val > VGIC_MAX_RESERVED ||
230 mutex_lock(&dev->kvm->arch.config_lock);
232 if (vgic_ready(dev->kvm) || dev->kvm->arch.vgic.nr_spis)
235 dev->kvm->arch.vgic.nr_spis =
236 val - VGIC_NR_PRIVATE_IRQS;
238 mutex_unlock(&dev->kvm->arch.config_lock);
242 case KVM_DEV_ARM_VGIC_GRP_CTRL: {
243 switch (attr->attr) {
244 case KVM_DEV_ARM_VGIC_CTRL_INIT:
245 mutex_lock(&dev->kvm->arch.config_lock);
246 r = vgic_init(dev->kvm);
247 mutex_unlock(&dev->kvm->arch.config_lock);
249 case KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES:
251 * OK, this one isn't common at all, but we
252 * want to handle all control group attributes
255 if (vgic_check_type(dev->kvm, KVM_DEV_TYPE_ARM_VGIC_V3))
257 mutex_lock(&dev->kvm->lock);
259 if (!lock_all_vcpus(dev->kvm)) {
260 mutex_unlock(&dev->kvm->lock);
264 mutex_lock(&dev->kvm->arch.config_lock);
265 r = vgic_v3_save_pending_tables(dev->kvm);
266 mutex_unlock(&dev->kvm->arch.config_lock);
267 unlock_all_vcpus(dev->kvm);
268 mutex_unlock(&dev->kvm->lock);
278 static int vgic_get_common_attr(struct kvm_device *dev,
279 struct kvm_device_attr *attr)
283 switch (attr->group) {
284 case KVM_DEV_ARM_VGIC_GRP_ADDR:
285 r = kvm_vgic_addr(dev->kvm, attr, false);
286 return (r == -ENODEV) ? -ENXIO : r;
287 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: {
288 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
290 r = put_user(dev->kvm->arch.vgic.nr_spis +
291 VGIC_NR_PRIVATE_IRQS, uaddr);
299 static int vgic_create(struct kvm_device *dev, u32 type)
301 return kvm_vgic_create(dev->kvm, type);
304 static void vgic_destroy(struct kvm_device *dev)
309 int kvm_register_vgic_device(unsigned long type)
314 case KVM_DEV_TYPE_ARM_VGIC_V2:
315 ret = kvm_register_device_ops(&kvm_arm_vgic_v2_ops,
316 KVM_DEV_TYPE_ARM_VGIC_V2);
318 case KVM_DEV_TYPE_ARM_VGIC_V3:
319 ret = kvm_register_device_ops(&kvm_arm_vgic_v3_ops,
320 KVM_DEV_TYPE_ARM_VGIC_V3);
324 ret = kvm_vgic_register_its_device();
331 int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
332 struct vgic_reg_attr *reg_attr)
336 cpuid = (attr->attr & KVM_DEV_ARM_VGIC_CPUID_MASK) >>
337 KVM_DEV_ARM_VGIC_CPUID_SHIFT;
339 if (cpuid >= atomic_read(&dev->kvm->online_vcpus))
342 reg_attr->vcpu = kvm_get_vcpu(dev->kvm, cpuid);
343 reg_attr->addr = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
349 * vgic_v2_attr_regs_access - allows user space to access VGIC v2 state
351 * @dev: kvm device handle
352 * @attr: kvm device attribute
353 * @is_write: true if userspace is writing a register
355 static int vgic_v2_attr_regs_access(struct kvm_device *dev,
356 struct kvm_device_attr *attr,
359 u32 __user *uaddr = (u32 __user *)(unsigned long)attr->addr;
360 struct vgic_reg_attr reg_attr;
362 struct kvm_vcpu *vcpu;
366 ret = vgic_v2_parse_attr(dev, attr, ®_attr);
370 vcpu = reg_attr.vcpu;
371 addr = reg_attr.addr;
374 if (get_user(val, uaddr))
377 mutex_lock(&dev->kvm->lock);
379 if (!lock_all_vcpus(dev->kvm)) {
380 mutex_unlock(&dev->kvm->lock);
384 mutex_lock(&dev->kvm->arch.config_lock);
386 ret = vgic_init(dev->kvm);
390 switch (attr->group) {
391 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
392 ret = vgic_v2_cpuif_uaccess(vcpu, is_write, addr, &val);
394 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
395 ret = vgic_v2_dist_uaccess(vcpu, is_write, addr, &val);
403 mutex_unlock(&dev->kvm->arch.config_lock);
404 unlock_all_vcpus(dev->kvm);
405 mutex_unlock(&dev->kvm->lock);
407 if (!ret && !is_write)
408 ret = put_user(val, uaddr);
413 static int vgic_v2_set_attr(struct kvm_device *dev,
414 struct kvm_device_attr *attr)
416 switch (attr->group) {
417 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
418 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
419 return vgic_v2_attr_regs_access(dev, attr, true);
421 return vgic_set_common_attr(dev, attr);
425 static int vgic_v2_get_attr(struct kvm_device *dev,
426 struct kvm_device_attr *attr)
428 switch (attr->group) {
429 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
430 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
431 return vgic_v2_attr_regs_access(dev, attr, false);
433 return vgic_get_common_attr(dev, attr);
437 static int vgic_v2_has_attr(struct kvm_device *dev,
438 struct kvm_device_attr *attr)
440 switch (attr->group) {
441 case KVM_DEV_ARM_VGIC_GRP_ADDR:
442 switch (attr->attr) {
443 case KVM_VGIC_V2_ADDR_TYPE_DIST:
444 case KVM_VGIC_V2_ADDR_TYPE_CPU:
448 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
449 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
450 return vgic_v2_has_attr_regs(dev, attr);
451 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS:
453 case KVM_DEV_ARM_VGIC_GRP_CTRL:
454 switch (attr->attr) {
455 case KVM_DEV_ARM_VGIC_CTRL_INIT:
462 struct kvm_device_ops kvm_arm_vgic_v2_ops = {
463 .name = "kvm-arm-vgic-v2",
464 .create = vgic_create,
465 .destroy = vgic_destroy,
466 .set_attr = vgic_v2_set_attr,
467 .get_attr = vgic_v2_get_attr,
468 .has_attr = vgic_v2_has_attr,
471 int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
472 struct vgic_reg_attr *reg_attr)
474 unsigned long vgic_mpidr, mpidr_reg;
477 * For KVM_DEV_ARM_VGIC_GRP_DIST_REGS group,
478 * attr might not hold MPIDR. Hence assume vcpu0.
480 if (attr->group != KVM_DEV_ARM_VGIC_GRP_DIST_REGS) {
481 vgic_mpidr = (attr->attr & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) >>
482 KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT;
484 mpidr_reg = VGIC_TO_MPIDR(vgic_mpidr);
485 reg_attr->vcpu = kvm_mpidr_to_vcpu(dev->kvm, mpidr_reg);
487 reg_attr->vcpu = kvm_get_vcpu(dev->kvm, 0);
493 reg_attr->addr = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
499 * vgic_v3_attr_regs_access - allows user space to access VGIC v3 state
501 * @dev: kvm device handle
502 * @attr: kvm device attribute
503 * @is_write: true if userspace is writing a register
505 static int vgic_v3_attr_regs_access(struct kvm_device *dev,
506 struct kvm_device_attr *attr,
509 struct vgic_reg_attr reg_attr;
511 struct kvm_vcpu *vcpu;
516 ret = vgic_v3_parse_attr(dev, attr, ®_attr);
520 vcpu = reg_attr.vcpu;
521 addr = reg_attr.addr;
523 switch (attr->group) {
524 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS:
525 /* Sysregs uaccess is performed by the sysreg handling code */
532 if (uaccess && is_write) {
533 u32 __user *uaddr = (u32 __user *)(unsigned long)attr->addr;
534 if (get_user(val, uaddr))
538 mutex_lock(&dev->kvm->lock);
540 if (!lock_all_vcpus(dev->kvm)) {
541 mutex_unlock(&dev->kvm->lock);
545 mutex_lock(&dev->kvm->arch.config_lock);
547 if (unlikely(!vgic_initialized(dev->kvm))) {
552 switch (attr->group) {
553 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
554 ret = vgic_v3_dist_uaccess(vcpu, is_write, addr, &val);
556 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:
557 ret = vgic_v3_redist_uaccess(vcpu, is_write, addr, &val);
559 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS:
560 ret = vgic_v3_cpu_sysregs_uaccess(vcpu, attr, is_write);
562 case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
563 unsigned int info, intid;
565 info = (attr->attr & KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK) >>
566 KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT;
567 if (info == VGIC_LEVEL_INFO_LINE_LEVEL) {
569 KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK;
570 ret = vgic_v3_line_level_info_uaccess(vcpu, is_write,
583 mutex_unlock(&dev->kvm->arch.config_lock);
584 unlock_all_vcpus(dev->kvm);
585 mutex_unlock(&dev->kvm->lock);
587 if (!ret && uaccess && !is_write) {
588 u32 __user *uaddr = (u32 __user *)(unsigned long)attr->addr;
589 ret = put_user(val, uaddr);
595 static int vgic_v3_set_attr(struct kvm_device *dev,
596 struct kvm_device_attr *attr)
598 switch (attr->group) {
599 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
600 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:
601 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS:
602 case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO:
603 return vgic_v3_attr_regs_access(dev, attr, true);
605 return vgic_set_common_attr(dev, attr);
609 static int vgic_v3_get_attr(struct kvm_device *dev,
610 struct kvm_device_attr *attr)
612 switch (attr->group) {
613 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
614 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:
615 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS:
616 case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO:
617 return vgic_v3_attr_regs_access(dev, attr, false);
619 return vgic_get_common_attr(dev, attr);
623 static int vgic_v3_has_attr(struct kvm_device *dev,
624 struct kvm_device_attr *attr)
626 switch (attr->group) {
627 case KVM_DEV_ARM_VGIC_GRP_ADDR:
628 switch (attr->attr) {
629 case KVM_VGIC_V3_ADDR_TYPE_DIST:
630 case KVM_VGIC_V3_ADDR_TYPE_REDIST:
631 case KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION:
635 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
636 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:
637 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS:
638 return vgic_v3_has_attr_regs(dev, attr);
639 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS:
641 case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
642 if (((attr->attr & KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK) >>
643 KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) ==
644 VGIC_LEVEL_INFO_LINE_LEVEL)
648 case KVM_DEV_ARM_VGIC_GRP_CTRL:
649 switch (attr->attr) {
650 case KVM_DEV_ARM_VGIC_CTRL_INIT:
652 case KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES:
659 struct kvm_device_ops kvm_arm_vgic_v3_ops = {
660 .name = "kvm-arm-vgic-v3",
661 .create = vgic_create,
662 .destroy = vgic_destroy,
663 .set_attr = vgic_v3_set_attr,
664 .get_attr = vgic_v3_get_attr,
665 .has_attr = vgic_v3_has_attr,