1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2015,2016 ARM Ltd.
6 * Author: Andre Przywara <andre.przywara@arm.com>
10 #include <linux/kvm.h>
11 #include <linux/kvm_host.h>
12 #include <linux/interrupt.h>
13 #include <linux/list.h>
14 #include <linux/uaccess.h>
15 #include <linux/list_sort.h>
17 #include <linux/irqchip/arm-gic-v3.h>
19 #include <asm/kvm_emulate.h>
20 #include <asm/kvm_arm.h>
21 #include <asm/kvm_mmu.h>
24 #include "vgic-mmio.h"
26 static int vgic_its_save_tables_v0(struct vgic_its *its);
27 static int vgic_its_restore_tables_v0(struct vgic_its *its);
28 static int vgic_its_commit_v0(struct vgic_its *its);
29 static int update_lpi_config(struct kvm *kvm, struct vgic_irq *irq,
30 struct kvm_vcpu *filter_vcpu, bool needs_inv);
33 * Creates a new (reference to a) struct vgic_irq for a given LPI.
34 * If this LPI is already mapped on another ITS, we increase its refcount
35 * and return a pointer to the existing structure.
36 * If this is a "new" LPI, we allocate and initialize a new struct vgic_irq.
37 * This function returns a pointer to the _unlocked_ structure.
39 static struct vgic_irq *vgic_add_lpi(struct kvm *kvm, u32 intid,
40 struct kvm_vcpu *vcpu)
42 struct vgic_dist *dist = &kvm->arch.vgic;
43 struct vgic_irq *irq = vgic_get_irq(kvm, NULL, intid), *oldirq;
47 /* In this case there is no put, since we keep the reference. */
51 irq = kzalloc(sizeof(struct vgic_irq), GFP_KERNEL_ACCOUNT);
53 return ERR_PTR(-ENOMEM);
55 INIT_LIST_HEAD(&irq->lpi_list);
56 INIT_LIST_HEAD(&irq->ap_list);
57 raw_spin_lock_init(&irq->irq_lock);
59 irq->config = VGIC_CONFIG_EDGE;
60 kref_init(&irq->refcount);
62 irq->target_vcpu = vcpu;
65 raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
68 * There could be a race with another vgic_add_lpi(), so we need to
69 * check that we don't add a second list entry with the same LPI.
71 list_for_each_entry(oldirq, &dist->lpi_list_head, lpi_list) {
72 if (oldirq->intid != intid)
75 /* Someone was faster with adding this LPI, lets use that. */
80 * This increases the refcount, the caller is expected to
81 * call vgic_put_irq() on the returned pointer once it's
82 * finished with the IRQ.
84 vgic_get_irq_kref(irq);
89 list_add_tail(&irq->lpi_list, &dist->lpi_list_head);
90 dist->lpi_list_count++;
93 raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
96 * We "cache" the configuration table entries in our struct vgic_irq's.
97 * However we only have those structs for mapped IRQs, so we read in
98 * the respective config data from memory here upon mapping the LPI.
100 * Should any of these fail, behave as if we couldn't create the LPI
101 * by dropping the refcount and returning the error.
103 ret = update_lpi_config(kvm, irq, NULL, false);
105 vgic_put_irq(kvm, irq);
109 ret = vgic_v3_lpi_sync_pending_status(kvm, irq);
111 vgic_put_irq(kvm, irq);
119 struct list_head dev_list;
121 /* the head for the list of ITTEs */
122 struct list_head itt_head;
123 u32 num_eventid_bits;
128 #define COLLECTION_NOT_MAPPED ((u32)~0)
130 struct its_collection {
131 struct list_head coll_list;
137 #define its_is_collection_mapped(coll) ((coll) && \
138 ((coll)->target_addr != COLLECTION_NOT_MAPPED))
141 struct list_head ite_list;
143 struct vgic_irq *irq;
144 struct its_collection *collection;
148 struct vgic_translation_cache_entry {
149 struct list_head entry;
153 struct vgic_irq *irq;
157 * struct vgic_its_abi - ITS abi ops and settings
158 * @cte_esz: collection table entry size
159 * @dte_esz: device table entry size
160 * @ite_esz: interrupt translation table entry size
161 * @save tables: save the ITS tables into guest RAM
162 * @restore_tables: restore the ITS internal structs from tables
163 * stored in guest RAM
164 * @commit: initialize the registers which expose the ABI settings,
165 * especially the entry sizes
167 struct vgic_its_abi {
171 int (*save_tables)(struct vgic_its *its);
172 int (*restore_tables)(struct vgic_its *its);
173 int (*commit)(struct vgic_its *its);
177 #define ESZ_MAX ABI_0_ESZ
179 static const struct vgic_its_abi its_table_abi_versions[] = {
181 .cte_esz = ABI_0_ESZ,
182 .dte_esz = ABI_0_ESZ,
183 .ite_esz = ABI_0_ESZ,
184 .save_tables = vgic_its_save_tables_v0,
185 .restore_tables = vgic_its_restore_tables_v0,
186 .commit = vgic_its_commit_v0,
190 #define NR_ITS_ABIS ARRAY_SIZE(its_table_abi_versions)
192 inline const struct vgic_its_abi *vgic_its_get_abi(struct vgic_its *its)
194 return &its_table_abi_versions[its->abi_rev];
197 static int vgic_its_set_abi(struct vgic_its *its, u32 rev)
199 const struct vgic_its_abi *abi;
202 abi = vgic_its_get_abi(its);
203 return abi->commit(its);
207 * Find and returns a device in the device table for an ITS.
208 * Must be called with the its_lock mutex held.
210 static struct its_device *find_its_device(struct vgic_its *its, u32 device_id)
212 struct its_device *device;
214 list_for_each_entry(device, &its->device_list, dev_list)
215 if (device_id == device->device_id)
222 * Find and returns an interrupt translation table entry (ITTE) for a given
223 * Device ID/Event ID pair on an ITS.
224 * Must be called with the its_lock mutex held.
226 static struct its_ite *find_ite(struct vgic_its *its, u32 device_id,
229 struct its_device *device;
232 device = find_its_device(its, device_id);
236 list_for_each_entry(ite, &device->itt_head, ite_list)
237 if (ite->event_id == event_id)
243 /* To be used as an iterator this macro misses the enclosing parentheses */
244 #define for_each_lpi_its(dev, ite, its) \
245 list_for_each_entry(dev, &(its)->device_list, dev_list) \
246 list_for_each_entry(ite, &(dev)->itt_head, ite_list)
248 #define GIC_LPI_OFFSET 8192
250 #define VITS_TYPER_IDBITS 16
251 #define VITS_TYPER_DEVBITS 16
252 #define VITS_DTE_MAX_DEVID_OFFSET (BIT(14) - 1)
253 #define VITS_ITE_MAX_EVENTID_OFFSET (BIT(16) - 1)
256 * Finds and returns a collection in the ITS collection table.
257 * Must be called with the its_lock mutex held.
259 static struct its_collection *find_collection(struct vgic_its *its, int coll_id)
261 struct its_collection *collection;
263 list_for_each_entry(collection, &its->collection_list, coll_list) {
264 if (coll_id == collection->collection_id)
271 #define LPI_PROP_ENABLE_BIT(p) ((p) & LPI_PROP_ENABLED)
272 #define LPI_PROP_PRIORITY(p) ((p) & 0xfc)
275 * Reads the configuration data for a given LPI from guest memory and
276 * updates the fields in struct vgic_irq.
277 * If filter_vcpu is not NULL, applies only if the IRQ is targeting this
278 * VCPU. Unconditionally applies if filter_vcpu is NULL.
280 static int update_lpi_config(struct kvm *kvm, struct vgic_irq *irq,
281 struct kvm_vcpu *filter_vcpu, bool needs_inv)
283 u64 propbase = GICR_PROPBASER_ADDRESS(kvm->arch.vgic.propbaser);
288 ret = kvm_read_guest_lock(kvm, propbase + irq->intid - GIC_LPI_OFFSET,
294 raw_spin_lock_irqsave(&irq->irq_lock, flags);
296 if (!filter_vcpu || filter_vcpu == irq->target_vcpu) {
297 irq->priority = LPI_PROP_PRIORITY(prop);
298 irq->enabled = LPI_PROP_ENABLE_BIT(prop);
301 vgic_queue_irq_unlock(kvm, irq, flags);
306 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
309 return its_prop_update_vlpi(irq->host_irq, prop, needs_inv);
315 * Create a snapshot of the current LPIs targeting @vcpu, so that we can
316 * enumerate those LPIs without holding any lock.
317 * Returns their number and puts the kmalloc'ed array into intid_ptr.
319 int vgic_copy_lpi_list(struct kvm *kvm, struct kvm_vcpu *vcpu, u32 **intid_ptr)
321 struct vgic_dist *dist = &kvm->arch.vgic;
322 struct vgic_irq *irq;
325 int irq_count, i = 0;
328 * There is an obvious race between allocating the array and LPIs
329 * being mapped/unmapped. If we ended up here as a result of a
330 * command, we're safe (locks are held, preventing another
331 * command). If coming from another path (such as enabling LPIs),
332 * we must be careful not to overrun the array.
334 irq_count = READ_ONCE(dist->lpi_list_count);
335 intids = kmalloc_array(irq_count, sizeof(intids[0]), GFP_KERNEL_ACCOUNT);
339 raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
340 list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
343 /* We don't need to "get" the IRQ, as we hold the list lock. */
344 if (vcpu && irq->target_vcpu != vcpu)
346 intids[i++] = irq->intid;
348 raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
354 static int update_affinity(struct vgic_irq *irq, struct kvm_vcpu *vcpu)
359 raw_spin_lock_irqsave(&irq->irq_lock, flags);
360 irq->target_vcpu = vcpu;
361 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
364 struct its_vlpi_map map;
366 ret = its_get_vlpi(irq->host_irq, &map);
371 atomic_dec(&map.vpe->vlpi_count);
372 map.vpe = &vcpu->arch.vgic_cpu.vgic_v3.its_vpe;
373 atomic_inc(&map.vpe->vlpi_count);
375 ret = its_map_vlpi(irq->host_irq, &map);
382 * Promotes the ITS view of affinity of an ITTE (which redistributor this LPI
383 * is targeting) to the VGIC's view, which deals with target VCPUs.
384 * Needs to be called whenever either the collection for a LPIs has
385 * changed or the collection itself got retargeted.
387 static void update_affinity_ite(struct kvm *kvm, struct its_ite *ite)
389 struct kvm_vcpu *vcpu;
391 if (!its_is_collection_mapped(ite->collection))
394 vcpu = kvm_get_vcpu(kvm, ite->collection->target_addr);
395 update_affinity(ite->irq, vcpu);
399 * Updates the target VCPU for every LPI targeting this collection.
400 * Must be called with the its_lock mutex held.
402 static void update_affinity_collection(struct kvm *kvm, struct vgic_its *its,
403 struct its_collection *coll)
405 struct its_device *device;
408 for_each_lpi_its(device, ite, its) {
409 if (ite->collection != coll)
412 update_affinity_ite(kvm, ite);
416 static u32 max_lpis_propbaser(u64 propbaser)
418 int nr_idbits = (propbaser & 0x1f) + 1;
420 return 1U << min(nr_idbits, INTERRUPT_ID_BITS_ITS);
424 * Sync the pending table pending bit of LPIs targeting @vcpu
425 * with our own data structures. This relies on the LPI being
428 static int its_sync_lpi_pending_table(struct kvm_vcpu *vcpu)
430 gpa_t pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
431 struct vgic_irq *irq;
432 int last_byte_offset = -1;
439 nr_irqs = vgic_copy_lpi_list(vcpu->kvm, vcpu, &intids);
443 for (i = 0; i < nr_irqs; i++) {
444 int byte_offset, bit_nr;
446 byte_offset = intids[i] / BITS_PER_BYTE;
447 bit_nr = intids[i] % BITS_PER_BYTE;
450 * For contiguously allocated LPIs chances are we just read
451 * this very same byte in the last iteration. Reuse that.
453 if (byte_offset != last_byte_offset) {
454 ret = kvm_read_guest_lock(vcpu->kvm,
455 pendbase + byte_offset,
461 last_byte_offset = byte_offset;
464 irq = vgic_get_irq(vcpu->kvm, NULL, intids[i]);
465 raw_spin_lock_irqsave(&irq->irq_lock, flags);
466 irq->pending_latch = pendmask & (1U << bit_nr);
467 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
468 vgic_put_irq(vcpu->kvm, irq);
476 static unsigned long vgic_mmio_read_its_typer(struct kvm *kvm,
477 struct vgic_its *its,
478 gpa_t addr, unsigned int len)
480 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
481 u64 reg = GITS_TYPER_PLPIS;
484 * We use linear CPU numbers for redistributor addressing,
485 * so GITS_TYPER.PTA is 0.
486 * Also we force all PROPBASER registers to be the same, so
487 * CommonLPIAff is 0 as well.
488 * To avoid memory waste in the guest, we keep the number of IDBits and
489 * DevBits low - as least for the time being.
491 reg |= GIC_ENCODE_SZ(VITS_TYPER_DEVBITS, 5) << GITS_TYPER_DEVBITS_SHIFT;
492 reg |= GIC_ENCODE_SZ(VITS_TYPER_IDBITS, 5) << GITS_TYPER_IDBITS_SHIFT;
493 reg |= GIC_ENCODE_SZ(abi->ite_esz, 4) << GITS_TYPER_ITT_ENTRY_SIZE_SHIFT;
495 return extract_bytes(reg, addr & 7, len);
498 static unsigned long vgic_mmio_read_its_iidr(struct kvm *kvm,
499 struct vgic_its *its,
500 gpa_t addr, unsigned int len)
504 val = (its->abi_rev << GITS_IIDR_REV_SHIFT) & GITS_IIDR_REV_MASK;
505 val |= (PRODUCT_ID_KVM << GITS_IIDR_PRODUCTID_SHIFT) | IMPLEMENTER_ARM;
509 static int vgic_mmio_uaccess_write_its_iidr(struct kvm *kvm,
510 struct vgic_its *its,
511 gpa_t addr, unsigned int len,
514 u32 rev = GITS_IIDR_REV(val);
516 if (rev >= NR_ITS_ABIS)
518 return vgic_its_set_abi(its, rev);
521 static unsigned long vgic_mmio_read_its_idregs(struct kvm *kvm,
522 struct vgic_its *its,
523 gpa_t addr, unsigned int len)
525 switch (addr & 0xffff) {
527 return 0x92; /* part number, bits[7:0] */
529 return 0xb4; /* part number, bits[11:8] */
531 return GIC_PIDR2_ARCH_GICv3 | 0x0b;
533 return 0x40; /* This is a 64K software visible page */
534 /* The following are the ID registers for (any) GIC. */
548 static struct vgic_irq *__vgic_its_check_cache(struct vgic_dist *dist,
550 u32 devid, u32 eventid)
552 struct vgic_translation_cache_entry *cte;
554 list_for_each_entry(cte, &dist->lpi_translation_cache, entry) {
556 * If we hit a NULL entry, there is nothing after this
562 if (cte->db != db || cte->devid != devid ||
563 cte->eventid != eventid)
567 * Move this entry to the head, as it is the most
570 if (!list_is_first(&cte->entry, &dist->lpi_translation_cache))
571 list_move(&cte->entry, &dist->lpi_translation_cache);
579 static struct vgic_irq *vgic_its_check_cache(struct kvm *kvm, phys_addr_t db,
580 u32 devid, u32 eventid)
582 struct vgic_dist *dist = &kvm->arch.vgic;
583 struct vgic_irq *irq;
586 raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
587 irq = __vgic_its_check_cache(dist, db, devid, eventid);
588 raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
593 static void vgic_its_cache_translation(struct kvm *kvm, struct vgic_its *its,
594 u32 devid, u32 eventid,
595 struct vgic_irq *irq)
597 struct vgic_dist *dist = &kvm->arch.vgic;
598 struct vgic_translation_cache_entry *cte;
602 /* Do not cache a directly injected interrupt */
606 raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
608 if (unlikely(list_empty(&dist->lpi_translation_cache)))
612 * We could have raced with another CPU caching the same
613 * translation behind our back, so let's check it is not in
616 db = its->vgic_its_base + GITS_TRANSLATER;
617 if (__vgic_its_check_cache(dist, db, devid, eventid))
620 /* Always reuse the last entry (LRU policy) */
621 cte = list_last_entry(&dist->lpi_translation_cache,
622 typeof(*cte), entry);
625 * Caching the translation implies having an extra reference
626 * to the interrupt, so drop the potential reference on what
627 * was in the cache, and increment it on the new interrupt.
630 __vgic_put_lpi_locked(kvm, cte->irq);
632 vgic_get_irq_kref(irq);
636 cte->eventid = eventid;
639 /* Move the new translation to the head of the list */
640 list_move(&cte->entry, &dist->lpi_translation_cache);
643 raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
646 void vgic_its_invalidate_cache(struct kvm *kvm)
648 struct vgic_dist *dist = &kvm->arch.vgic;
649 struct vgic_translation_cache_entry *cte;
652 raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
654 list_for_each_entry(cte, &dist->lpi_translation_cache, entry) {
656 * If we hit a NULL entry, there is nothing after this
662 __vgic_put_lpi_locked(kvm, cte->irq);
666 raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
669 int vgic_its_resolve_lpi(struct kvm *kvm, struct vgic_its *its,
670 u32 devid, u32 eventid, struct vgic_irq **irq)
672 struct kvm_vcpu *vcpu;
678 ite = find_ite(its, devid, eventid);
679 if (!ite || !its_is_collection_mapped(ite->collection))
680 return E_ITS_INT_UNMAPPED_INTERRUPT;
682 vcpu = kvm_get_vcpu(kvm, ite->collection->target_addr);
684 return E_ITS_INT_UNMAPPED_INTERRUPT;
686 if (!vgic_lpis_enabled(vcpu))
689 vgic_its_cache_translation(kvm, its, devid, eventid, ite->irq);
695 struct vgic_its *vgic_msi_to_its(struct kvm *kvm, struct kvm_msi *msi)
698 struct kvm_io_device *kvm_io_dev;
699 struct vgic_io_device *iodev;
701 if (!vgic_has_its(kvm))
702 return ERR_PTR(-ENODEV);
704 if (!(msi->flags & KVM_MSI_VALID_DEVID))
705 return ERR_PTR(-EINVAL);
707 address = (u64)msi->address_hi << 32 | msi->address_lo;
709 kvm_io_dev = kvm_io_bus_get_dev(kvm, KVM_MMIO_BUS, address);
711 return ERR_PTR(-EINVAL);
713 if (kvm_io_dev->ops != &kvm_io_gic_ops)
714 return ERR_PTR(-EINVAL);
716 iodev = container_of(kvm_io_dev, struct vgic_io_device, dev);
717 if (iodev->iodev_type != IODEV_ITS)
718 return ERR_PTR(-EINVAL);
724 * Find the target VCPU and the LPI number for a given devid/eventid pair
725 * and make this IRQ pending, possibly injecting it.
726 * Must be called with the its_lock mutex held.
727 * Returns 0 on success, a positive error value for any ITS mapping
728 * related errors and negative error values for generic errors.
730 static int vgic_its_trigger_msi(struct kvm *kvm, struct vgic_its *its,
731 u32 devid, u32 eventid)
733 struct vgic_irq *irq = NULL;
737 err = vgic_its_resolve_lpi(kvm, its, devid, eventid, &irq);
742 return irq_set_irqchip_state(irq->host_irq,
743 IRQCHIP_STATE_PENDING, true);
745 raw_spin_lock_irqsave(&irq->irq_lock, flags);
746 irq->pending_latch = true;
747 vgic_queue_irq_unlock(kvm, irq, flags);
752 int vgic_its_inject_cached_translation(struct kvm *kvm, struct kvm_msi *msi)
754 struct vgic_irq *irq;
758 db = (u64)msi->address_hi << 32 | msi->address_lo;
759 irq = vgic_its_check_cache(kvm, db, msi->devid, msi->data);
763 raw_spin_lock_irqsave(&irq->irq_lock, flags);
764 irq->pending_latch = true;
765 vgic_queue_irq_unlock(kvm, irq, flags);
771 * Queries the KVM IO bus framework to get the ITS pointer from the given
773 * We then call vgic_its_trigger_msi() with the decoded data.
774 * According to the KVM_SIGNAL_MSI API description returns 1 on success.
776 int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi)
778 struct vgic_its *its;
781 if (!vgic_its_inject_cached_translation(kvm, msi))
784 its = vgic_msi_to_its(kvm, msi);
788 mutex_lock(&its->its_lock);
789 ret = vgic_its_trigger_msi(kvm, its, msi->devid, msi->data);
790 mutex_unlock(&its->its_lock);
796 * KVM_SIGNAL_MSI demands a return value > 0 for success and 0
797 * if the guest has blocked the MSI. So we map any LPI mapping
798 * related error to that.
806 /* Requires the its_lock to be held. */
807 static void its_free_ite(struct kvm *kvm, struct its_ite *ite)
809 list_del(&ite->ite_list);
811 /* This put matches the get in vgic_add_lpi. */
814 WARN_ON(its_unmap_vlpi(ite->irq->host_irq));
816 vgic_put_irq(kvm, ite->irq);
822 static u64 its_cmd_mask_field(u64 *its_cmd, int word, int shift, int size)
824 return (le64_to_cpu(its_cmd[word]) >> shift) & (BIT_ULL(size) - 1);
827 #define its_cmd_get_command(cmd) its_cmd_mask_field(cmd, 0, 0, 8)
828 #define its_cmd_get_deviceid(cmd) its_cmd_mask_field(cmd, 0, 32, 32)
829 #define its_cmd_get_size(cmd) (its_cmd_mask_field(cmd, 1, 0, 5) + 1)
830 #define its_cmd_get_id(cmd) its_cmd_mask_field(cmd, 1, 0, 32)
831 #define its_cmd_get_physical_id(cmd) its_cmd_mask_field(cmd, 1, 32, 32)
832 #define its_cmd_get_collection(cmd) its_cmd_mask_field(cmd, 2, 0, 16)
833 #define its_cmd_get_ittaddr(cmd) (its_cmd_mask_field(cmd, 2, 8, 44) << 8)
834 #define its_cmd_get_target_addr(cmd) its_cmd_mask_field(cmd, 2, 16, 32)
835 #define its_cmd_get_validbit(cmd) its_cmd_mask_field(cmd, 2, 63, 1)
838 * The DISCARD command frees an Interrupt Translation Table Entry (ITTE).
839 * Must be called with the its_lock mutex held.
841 static int vgic_its_cmd_handle_discard(struct kvm *kvm, struct vgic_its *its,
844 u32 device_id = its_cmd_get_deviceid(its_cmd);
845 u32 event_id = its_cmd_get_id(its_cmd);
848 ite = find_ite(its, device_id, event_id);
849 if (ite && its_is_collection_mapped(ite->collection)) {
851 * Though the spec talks about removing the pending state, we
852 * don't bother here since we clear the ITTE anyway and the
853 * pending state is a property of the ITTE struct.
855 vgic_its_invalidate_cache(kvm);
857 its_free_ite(kvm, ite);
861 return E_ITS_DISCARD_UNMAPPED_INTERRUPT;
865 * The MOVI command moves an ITTE to a different collection.
866 * Must be called with the its_lock mutex held.
868 static int vgic_its_cmd_handle_movi(struct kvm *kvm, struct vgic_its *its,
871 u32 device_id = its_cmd_get_deviceid(its_cmd);
872 u32 event_id = its_cmd_get_id(its_cmd);
873 u32 coll_id = its_cmd_get_collection(its_cmd);
874 struct kvm_vcpu *vcpu;
876 struct its_collection *collection;
878 ite = find_ite(its, device_id, event_id);
880 return E_ITS_MOVI_UNMAPPED_INTERRUPT;
882 if (!its_is_collection_mapped(ite->collection))
883 return E_ITS_MOVI_UNMAPPED_COLLECTION;
885 collection = find_collection(its, coll_id);
886 if (!its_is_collection_mapped(collection))
887 return E_ITS_MOVI_UNMAPPED_COLLECTION;
889 ite->collection = collection;
890 vcpu = kvm_get_vcpu(kvm, collection->target_addr);
892 vgic_its_invalidate_cache(kvm);
894 return update_affinity(ite->irq, vcpu);
897 static bool __is_visible_gfn_locked(struct vgic_its *its, gpa_t gpa)
899 gfn_t gfn = gpa >> PAGE_SHIFT;
903 idx = srcu_read_lock(&its->dev->kvm->srcu);
904 ret = kvm_is_visible_gfn(its->dev->kvm, gfn);
905 srcu_read_unlock(&its->dev->kvm->srcu, idx);
910 * Check whether an ID can be stored into the corresponding guest table.
911 * For a direct table this is pretty easy, but gets a bit nasty for
912 * indirect tables. We check whether the resulting guest physical address
913 * is actually valid (covered by a memslot and guest accessible).
914 * For this we have to read the respective first level entry.
916 static bool vgic_its_check_id(struct vgic_its *its, u64 baser, u32 id,
919 int l1_tbl_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
920 u64 indirect_ptr, type = GITS_BASER_TYPE(baser);
921 phys_addr_t base = GITS_BASER_ADDR_48_to_52(baser);
922 int esz = GITS_BASER_ENTRY_SIZE(baser);
926 case GITS_BASER_TYPE_DEVICE:
927 if (id >= BIT_ULL(VITS_TYPER_DEVBITS))
930 case GITS_BASER_TYPE_COLLECTION:
931 /* as GITS_TYPER.CIL == 0, ITS supports 16-bit collection ID */
932 if (id >= BIT_ULL(16))
939 if (!(baser & GITS_BASER_INDIRECT)) {
942 if (id >= (l1_tbl_size / esz))
945 addr = base + id * esz;
950 return __is_visible_gfn_locked(its, addr);
953 /* calculate and check the index into the 1st level */
954 index = id / (SZ_64K / esz);
955 if (index >= (l1_tbl_size / sizeof(u64)))
958 /* Each 1st level entry is represented by a 64-bit value. */
959 if (kvm_read_guest_lock(its->dev->kvm,
960 base + index * sizeof(indirect_ptr),
961 &indirect_ptr, sizeof(indirect_ptr)))
964 indirect_ptr = le64_to_cpu(indirect_ptr);
966 /* check the valid bit of the first level entry */
967 if (!(indirect_ptr & BIT_ULL(63)))
970 /* Mask the guest physical address and calculate the frame number. */
971 indirect_ptr &= GENMASK_ULL(51, 16);
973 /* Find the address of the actual entry */
974 index = id % (SZ_64K / esz);
975 indirect_ptr += index * esz;
978 *eaddr = indirect_ptr;
980 return __is_visible_gfn_locked(its, indirect_ptr);
984 * Check whether an event ID can be stored in the corresponding Interrupt
985 * Translation Table, which starts at device->itt_addr.
987 static bool vgic_its_check_event_id(struct vgic_its *its, struct its_device *device,
990 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
991 int ite_esz = abi->ite_esz;
994 /* max table size is: BIT_ULL(device->num_eventid_bits) * ite_esz */
995 if (event_id >= BIT_ULL(device->num_eventid_bits))
998 gpa = device->itt_addr + event_id * ite_esz;
999 return __is_visible_gfn_locked(its, gpa);
1003 * Add a new collection into the ITS collection table.
1004 * Returns 0 on success, and a negative error value for generic errors.
1006 static int vgic_its_alloc_collection(struct vgic_its *its,
1007 struct its_collection **colp,
1010 struct its_collection *collection;
1012 collection = kzalloc(sizeof(*collection), GFP_KERNEL_ACCOUNT);
1016 collection->collection_id = coll_id;
1017 collection->target_addr = COLLECTION_NOT_MAPPED;
1019 list_add_tail(&collection->coll_list, &its->collection_list);
1025 static void vgic_its_free_collection(struct vgic_its *its, u32 coll_id)
1027 struct its_collection *collection;
1028 struct its_device *device;
1029 struct its_ite *ite;
1032 * Clearing the mapping for that collection ID removes the
1033 * entry from the list. If there wasn't any before, we can
1036 collection = find_collection(its, coll_id);
1040 for_each_lpi_its(device, ite, its)
1041 if (ite->collection &&
1042 ite->collection->collection_id == coll_id)
1043 ite->collection = NULL;
1045 list_del(&collection->coll_list);
1049 /* Must be called with its_lock mutex held */
1050 static struct its_ite *vgic_its_alloc_ite(struct its_device *device,
1051 struct its_collection *collection,
1054 struct its_ite *ite;
1056 ite = kzalloc(sizeof(*ite), GFP_KERNEL_ACCOUNT);
1058 return ERR_PTR(-ENOMEM);
1060 ite->event_id = event_id;
1061 ite->collection = collection;
1063 list_add_tail(&ite->ite_list, &device->itt_head);
1068 * The MAPTI and MAPI commands map LPIs to ITTEs.
1069 * Must be called with its_lock mutex held.
1071 static int vgic_its_cmd_handle_mapi(struct kvm *kvm, struct vgic_its *its,
1074 u32 device_id = its_cmd_get_deviceid(its_cmd);
1075 u32 event_id = its_cmd_get_id(its_cmd);
1076 u32 coll_id = its_cmd_get_collection(its_cmd);
1077 struct its_ite *ite;
1078 struct kvm_vcpu *vcpu = NULL;
1079 struct its_device *device;
1080 struct its_collection *collection, *new_coll = NULL;
1081 struct vgic_irq *irq;
1084 device = find_its_device(its, device_id);
1086 return E_ITS_MAPTI_UNMAPPED_DEVICE;
1088 if (!vgic_its_check_event_id(its, device, event_id))
1089 return E_ITS_MAPTI_ID_OOR;
1091 if (its_cmd_get_command(its_cmd) == GITS_CMD_MAPTI)
1092 lpi_nr = its_cmd_get_physical_id(its_cmd);
1095 if (lpi_nr < GIC_LPI_OFFSET ||
1096 lpi_nr >= max_lpis_propbaser(kvm->arch.vgic.propbaser))
1097 return E_ITS_MAPTI_PHYSICALID_OOR;
1099 /* If there is an existing mapping, behavior is UNPREDICTABLE. */
1100 if (find_ite(its, device_id, event_id))
1103 collection = find_collection(its, coll_id);
1107 if (!vgic_its_check_id(its, its->baser_coll_table, coll_id, NULL))
1108 return E_ITS_MAPC_COLLECTION_OOR;
1110 ret = vgic_its_alloc_collection(its, &collection, coll_id);
1113 new_coll = collection;
1116 ite = vgic_its_alloc_ite(device, collection, event_id);
1119 vgic_its_free_collection(its, coll_id);
1120 return PTR_ERR(ite);
1123 if (its_is_collection_mapped(collection))
1124 vcpu = kvm_get_vcpu(kvm, collection->target_addr);
1126 irq = vgic_add_lpi(kvm, lpi_nr, vcpu);
1129 vgic_its_free_collection(its, coll_id);
1130 its_free_ite(kvm, ite);
1131 return PTR_ERR(irq);
1138 /* Requires the its_lock to be held. */
1139 static void vgic_its_free_device(struct kvm *kvm, struct its_device *device)
1141 struct its_ite *ite, *temp;
1144 * The spec says that unmapping a device with still valid
1145 * ITTEs associated is UNPREDICTABLE. We remove all ITTEs,
1146 * since we cannot leave the memory unreferenced.
1148 list_for_each_entry_safe(ite, temp, &device->itt_head, ite_list)
1149 its_free_ite(kvm, ite);
1151 vgic_its_invalidate_cache(kvm);
1153 list_del(&device->dev_list);
1157 /* its lock must be held */
1158 static void vgic_its_free_device_list(struct kvm *kvm, struct vgic_its *its)
1160 struct its_device *cur, *temp;
1162 list_for_each_entry_safe(cur, temp, &its->device_list, dev_list)
1163 vgic_its_free_device(kvm, cur);
1166 /* its lock must be held */
1167 static void vgic_its_free_collection_list(struct kvm *kvm, struct vgic_its *its)
1169 struct its_collection *cur, *temp;
1171 list_for_each_entry_safe(cur, temp, &its->collection_list, coll_list)
1172 vgic_its_free_collection(its, cur->collection_id);
1175 /* Must be called with its_lock mutex held */
1176 static struct its_device *vgic_its_alloc_device(struct vgic_its *its,
1177 u32 device_id, gpa_t itt_addr,
1178 u8 num_eventid_bits)
1180 struct its_device *device;
1182 device = kzalloc(sizeof(*device), GFP_KERNEL_ACCOUNT);
1184 return ERR_PTR(-ENOMEM);
1186 device->device_id = device_id;
1187 device->itt_addr = itt_addr;
1188 device->num_eventid_bits = num_eventid_bits;
1189 INIT_LIST_HEAD(&device->itt_head);
1191 list_add_tail(&device->dev_list, &its->device_list);
1196 * MAPD maps or unmaps a device ID to Interrupt Translation Tables (ITTs).
1197 * Must be called with the its_lock mutex held.
1199 static int vgic_its_cmd_handle_mapd(struct kvm *kvm, struct vgic_its *its,
1202 u32 device_id = its_cmd_get_deviceid(its_cmd);
1203 bool valid = its_cmd_get_validbit(its_cmd);
1204 u8 num_eventid_bits = its_cmd_get_size(its_cmd);
1205 gpa_t itt_addr = its_cmd_get_ittaddr(its_cmd);
1206 struct its_device *device;
1208 if (!vgic_its_check_id(its, its->baser_device_table, device_id, NULL))
1209 return E_ITS_MAPD_DEVICE_OOR;
1211 if (valid && num_eventid_bits > VITS_TYPER_IDBITS)
1212 return E_ITS_MAPD_ITTSIZE_OOR;
1214 device = find_its_device(its, device_id);
1217 * The spec says that calling MAPD on an already mapped device
1218 * invalidates all cached data for this device. We implement this
1219 * by removing the mapping and re-establishing it.
1222 vgic_its_free_device(kvm, device);
1225 * The spec does not say whether unmapping a not-mapped device
1226 * is an error, so we are done in any case.
1231 device = vgic_its_alloc_device(its, device_id, itt_addr,
1234 return PTR_ERR_OR_ZERO(device);
1238 * The MAPC command maps collection IDs to redistributors.
1239 * Must be called with the its_lock mutex held.
1241 static int vgic_its_cmd_handle_mapc(struct kvm *kvm, struct vgic_its *its,
1246 struct its_collection *collection;
1249 valid = its_cmd_get_validbit(its_cmd);
1250 coll_id = its_cmd_get_collection(its_cmd);
1251 target_addr = its_cmd_get_target_addr(its_cmd);
1253 if (target_addr >= atomic_read(&kvm->online_vcpus))
1254 return E_ITS_MAPC_PROCNUM_OOR;
1257 vgic_its_free_collection(its, coll_id);
1258 vgic_its_invalidate_cache(kvm);
1260 collection = find_collection(its, coll_id);
1265 if (!vgic_its_check_id(its, its->baser_coll_table,
1267 return E_ITS_MAPC_COLLECTION_OOR;
1269 ret = vgic_its_alloc_collection(its, &collection,
1273 collection->target_addr = target_addr;
1275 collection->target_addr = target_addr;
1276 update_affinity_collection(kvm, its, collection);
1284 * The CLEAR command removes the pending state for a particular LPI.
1285 * Must be called with the its_lock mutex held.
1287 static int vgic_its_cmd_handle_clear(struct kvm *kvm, struct vgic_its *its,
1290 u32 device_id = its_cmd_get_deviceid(its_cmd);
1291 u32 event_id = its_cmd_get_id(its_cmd);
1292 struct its_ite *ite;
1295 ite = find_ite(its, device_id, event_id);
1297 return E_ITS_CLEAR_UNMAPPED_INTERRUPT;
1299 ite->irq->pending_latch = false;
1302 return irq_set_irqchip_state(ite->irq->host_irq,
1303 IRQCHIP_STATE_PENDING, false);
1308 int vgic_its_inv_lpi(struct kvm *kvm, struct vgic_irq *irq)
1310 return update_lpi_config(kvm, irq, NULL, true);
1314 * The INV command syncs the configuration bits from the memory table.
1315 * Must be called with the its_lock mutex held.
1317 static int vgic_its_cmd_handle_inv(struct kvm *kvm, struct vgic_its *its,
1320 u32 device_id = its_cmd_get_deviceid(its_cmd);
1321 u32 event_id = its_cmd_get_id(its_cmd);
1322 struct its_ite *ite;
1325 ite = find_ite(its, device_id, event_id);
1327 return E_ITS_INV_UNMAPPED_INTERRUPT;
1329 return vgic_its_inv_lpi(kvm, ite->irq);
1333 * vgic_its_invall - invalidate all LPIs targetting a given vcpu
1334 * @vcpu: the vcpu for which the RD is targetted by an invalidation
1336 * Contrary to the INVALL command, this targets a RD instead of a
1337 * collection, and we don't need to hold the its_lock, since no ITS is
1340 int vgic_its_invall(struct kvm_vcpu *vcpu)
1342 struct kvm *kvm = vcpu->kvm;
1343 int irq_count, i = 0;
1346 irq_count = vgic_copy_lpi_list(kvm, vcpu, &intids);
1350 for (i = 0; i < irq_count; i++) {
1351 struct vgic_irq *irq = vgic_get_irq(kvm, NULL, intids[i]);
1354 update_lpi_config(kvm, irq, vcpu, false);
1355 vgic_put_irq(kvm, irq);
1360 if (vcpu->arch.vgic_cpu.vgic_v3.its_vpe.its_vm)
1361 its_invall_vpe(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe);
1367 * The INVALL command requests flushing of all IRQ data in this collection.
1368 * Find the VCPU mapped to that collection, then iterate over the VM's list
1369 * of mapped LPIs and update the configuration for each IRQ which targets
1370 * the specified vcpu. The configuration will be read from the in-memory
1371 * configuration table.
1372 * Must be called with the its_lock mutex held.
1374 static int vgic_its_cmd_handle_invall(struct kvm *kvm, struct vgic_its *its,
1377 u32 coll_id = its_cmd_get_collection(its_cmd);
1378 struct its_collection *collection;
1379 struct kvm_vcpu *vcpu;
1381 collection = find_collection(its, coll_id);
1382 if (!its_is_collection_mapped(collection))
1383 return E_ITS_INVALL_UNMAPPED_COLLECTION;
1385 vcpu = kvm_get_vcpu(kvm, collection->target_addr);
1386 vgic_its_invall(vcpu);
1392 * The MOVALL command moves the pending state of all IRQs targeting one
1393 * redistributor to another. We don't hold the pending state in the VCPUs,
1394 * but in the IRQs instead, so there is really not much to do for us here.
1395 * However the spec says that no IRQ must target the old redistributor
1396 * afterwards, so we make sure that no LPI is using the associated target_vcpu.
1397 * This command affects all LPIs in the system that target that redistributor.
1399 static int vgic_its_cmd_handle_movall(struct kvm *kvm, struct vgic_its *its,
1402 u32 target1_addr = its_cmd_get_target_addr(its_cmd);
1403 u32 target2_addr = its_cmd_mask_field(its_cmd, 3, 16, 32);
1404 struct kvm_vcpu *vcpu1, *vcpu2;
1405 struct vgic_irq *irq;
1409 if (target1_addr >= atomic_read(&kvm->online_vcpus) ||
1410 target2_addr >= atomic_read(&kvm->online_vcpus))
1411 return E_ITS_MOVALL_PROCNUM_OOR;
1413 if (target1_addr == target2_addr)
1416 vcpu1 = kvm_get_vcpu(kvm, target1_addr);
1417 vcpu2 = kvm_get_vcpu(kvm, target2_addr);
1419 irq_count = vgic_copy_lpi_list(kvm, vcpu1, &intids);
1423 for (i = 0; i < irq_count; i++) {
1424 irq = vgic_get_irq(kvm, NULL, intids[i]);
1426 update_affinity(irq, vcpu2);
1428 vgic_put_irq(kvm, irq);
1431 vgic_its_invalidate_cache(kvm);
1438 * The INT command injects the LPI associated with that DevID/EvID pair.
1439 * Must be called with the its_lock mutex held.
1441 static int vgic_its_cmd_handle_int(struct kvm *kvm, struct vgic_its *its,
1444 u32 msi_data = its_cmd_get_id(its_cmd);
1445 u64 msi_devid = its_cmd_get_deviceid(its_cmd);
1447 return vgic_its_trigger_msi(kvm, its, msi_devid, msi_data);
1451 * This function is called with the its_cmd lock held, but the ITS data
1452 * structure lock dropped.
1454 static int vgic_its_handle_command(struct kvm *kvm, struct vgic_its *its,
1459 mutex_lock(&its->its_lock);
1460 switch (its_cmd_get_command(its_cmd)) {
1462 ret = vgic_its_cmd_handle_mapd(kvm, its, its_cmd);
1465 ret = vgic_its_cmd_handle_mapc(kvm, its, its_cmd);
1468 ret = vgic_its_cmd_handle_mapi(kvm, its, its_cmd);
1470 case GITS_CMD_MAPTI:
1471 ret = vgic_its_cmd_handle_mapi(kvm, its, its_cmd);
1474 ret = vgic_its_cmd_handle_movi(kvm, its, its_cmd);
1476 case GITS_CMD_DISCARD:
1477 ret = vgic_its_cmd_handle_discard(kvm, its, its_cmd);
1479 case GITS_CMD_CLEAR:
1480 ret = vgic_its_cmd_handle_clear(kvm, its, its_cmd);
1482 case GITS_CMD_MOVALL:
1483 ret = vgic_its_cmd_handle_movall(kvm, its, its_cmd);
1486 ret = vgic_its_cmd_handle_int(kvm, its, its_cmd);
1489 ret = vgic_its_cmd_handle_inv(kvm, its, its_cmd);
1491 case GITS_CMD_INVALL:
1492 ret = vgic_its_cmd_handle_invall(kvm, its, its_cmd);
1495 /* we ignore this command: we are in sync all of the time */
1499 mutex_unlock(&its->its_lock);
1504 static u64 vgic_sanitise_its_baser(u64 reg)
1506 reg = vgic_sanitise_field(reg, GITS_BASER_SHAREABILITY_MASK,
1507 GITS_BASER_SHAREABILITY_SHIFT,
1508 vgic_sanitise_shareability);
1509 reg = vgic_sanitise_field(reg, GITS_BASER_INNER_CACHEABILITY_MASK,
1510 GITS_BASER_INNER_CACHEABILITY_SHIFT,
1511 vgic_sanitise_inner_cacheability);
1512 reg = vgic_sanitise_field(reg, GITS_BASER_OUTER_CACHEABILITY_MASK,
1513 GITS_BASER_OUTER_CACHEABILITY_SHIFT,
1514 vgic_sanitise_outer_cacheability);
1516 /* We support only one (ITS) page size: 64K */
1517 reg = (reg & ~GITS_BASER_PAGE_SIZE_MASK) | GITS_BASER_PAGE_SIZE_64K;
1522 static u64 vgic_sanitise_its_cbaser(u64 reg)
1524 reg = vgic_sanitise_field(reg, GITS_CBASER_SHAREABILITY_MASK,
1525 GITS_CBASER_SHAREABILITY_SHIFT,
1526 vgic_sanitise_shareability);
1527 reg = vgic_sanitise_field(reg, GITS_CBASER_INNER_CACHEABILITY_MASK,
1528 GITS_CBASER_INNER_CACHEABILITY_SHIFT,
1529 vgic_sanitise_inner_cacheability);
1530 reg = vgic_sanitise_field(reg, GITS_CBASER_OUTER_CACHEABILITY_MASK,
1531 GITS_CBASER_OUTER_CACHEABILITY_SHIFT,
1532 vgic_sanitise_outer_cacheability);
1534 /* Sanitise the physical address to be 64k aligned. */
1535 reg &= ~GENMASK_ULL(15, 12);
1540 static unsigned long vgic_mmio_read_its_cbaser(struct kvm *kvm,
1541 struct vgic_its *its,
1542 gpa_t addr, unsigned int len)
1544 return extract_bytes(its->cbaser, addr & 7, len);
1547 static void vgic_mmio_write_its_cbaser(struct kvm *kvm, struct vgic_its *its,
1548 gpa_t addr, unsigned int len,
1551 /* When GITS_CTLR.Enable is 1, this register is RO. */
1555 mutex_lock(&its->cmd_lock);
1556 its->cbaser = update_64bit_reg(its->cbaser, addr & 7, len, val);
1557 its->cbaser = vgic_sanitise_its_cbaser(its->cbaser);
1560 * CWRITER is architecturally UNKNOWN on reset, but we need to reset
1561 * it to CREADR to make sure we start with an empty command buffer.
1563 its->cwriter = its->creadr;
1564 mutex_unlock(&its->cmd_lock);
1567 #define ITS_CMD_BUFFER_SIZE(baser) ((((baser) & 0xff) + 1) << 12)
1568 #define ITS_CMD_SIZE 32
1569 #define ITS_CMD_OFFSET(reg) ((reg) & GENMASK(19, 5))
1571 /* Must be called with the cmd_lock held. */
1572 static void vgic_its_process_commands(struct kvm *kvm, struct vgic_its *its)
1577 /* Commands are only processed when the ITS is enabled. */
1581 cbaser = GITS_CBASER_ADDRESS(its->cbaser);
1583 while (its->cwriter != its->creadr) {
1584 int ret = kvm_read_guest_lock(kvm, cbaser + its->creadr,
1585 cmd_buf, ITS_CMD_SIZE);
1587 * If kvm_read_guest() fails, this could be due to the guest
1588 * programming a bogus value in CBASER or something else going
1589 * wrong from which we cannot easily recover.
1590 * According to section 6.3.2 in the GICv3 spec we can just
1591 * ignore that command then.
1594 vgic_its_handle_command(kvm, its, cmd_buf);
1596 its->creadr += ITS_CMD_SIZE;
1597 if (its->creadr == ITS_CMD_BUFFER_SIZE(its->cbaser))
1603 * By writing to CWRITER the guest announces new commands to be processed.
1604 * To avoid any races in the first place, we take the its_cmd lock, which
1605 * protects our ring buffer variables, so that there is only one user
1606 * per ITS handling commands at a given time.
1608 static void vgic_mmio_write_its_cwriter(struct kvm *kvm, struct vgic_its *its,
1609 gpa_t addr, unsigned int len,
1617 mutex_lock(&its->cmd_lock);
1619 reg = update_64bit_reg(its->cwriter, addr & 7, len, val);
1620 reg = ITS_CMD_OFFSET(reg);
1621 if (reg >= ITS_CMD_BUFFER_SIZE(its->cbaser)) {
1622 mutex_unlock(&its->cmd_lock);
1627 vgic_its_process_commands(kvm, its);
1629 mutex_unlock(&its->cmd_lock);
1632 static unsigned long vgic_mmio_read_its_cwriter(struct kvm *kvm,
1633 struct vgic_its *its,
1634 gpa_t addr, unsigned int len)
1636 return extract_bytes(its->cwriter, addr & 0x7, len);
1639 static unsigned long vgic_mmio_read_its_creadr(struct kvm *kvm,
1640 struct vgic_its *its,
1641 gpa_t addr, unsigned int len)
1643 return extract_bytes(its->creadr, addr & 0x7, len);
1646 static int vgic_mmio_uaccess_write_its_creadr(struct kvm *kvm,
1647 struct vgic_its *its,
1648 gpa_t addr, unsigned int len,
1654 mutex_lock(&its->cmd_lock);
1661 cmd_offset = ITS_CMD_OFFSET(val);
1662 if (cmd_offset >= ITS_CMD_BUFFER_SIZE(its->cbaser)) {
1667 its->creadr = cmd_offset;
1669 mutex_unlock(&its->cmd_lock);
1673 #define BASER_INDEX(addr) (((addr) / sizeof(u64)) & 0x7)
1674 static unsigned long vgic_mmio_read_its_baser(struct kvm *kvm,
1675 struct vgic_its *its,
1676 gpa_t addr, unsigned int len)
1680 switch (BASER_INDEX(addr)) {
1682 reg = its->baser_device_table;
1685 reg = its->baser_coll_table;
1692 return extract_bytes(reg, addr & 7, len);
1695 #define GITS_BASER_RO_MASK (GENMASK_ULL(52, 48) | GENMASK_ULL(58, 56))
1696 static void vgic_mmio_write_its_baser(struct kvm *kvm,
1697 struct vgic_its *its,
1698 gpa_t addr, unsigned int len,
1701 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
1702 u64 entry_size, table_type;
1703 u64 reg, *regptr, clearbits = 0;
1705 /* When GITS_CTLR.Enable is 1, we ignore write accesses. */
1709 switch (BASER_INDEX(addr)) {
1711 regptr = &its->baser_device_table;
1712 entry_size = abi->dte_esz;
1713 table_type = GITS_BASER_TYPE_DEVICE;
1716 regptr = &its->baser_coll_table;
1717 entry_size = abi->cte_esz;
1718 table_type = GITS_BASER_TYPE_COLLECTION;
1719 clearbits = GITS_BASER_INDIRECT;
1725 reg = update_64bit_reg(*regptr, addr & 7, len, val);
1726 reg &= ~GITS_BASER_RO_MASK;
1729 reg |= (entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT;
1730 reg |= table_type << GITS_BASER_TYPE_SHIFT;
1731 reg = vgic_sanitise_its_baser(reg);
1735 if (!(reg & GITS_BASER_VALID)) {
1736 /* Take the its_lock to prevent a race with a save/restore */
1737 mutex_lock(&its->its_lock);
1738 switch (table_type) {
1739 case GITS_BASER_TYPE_DEVICE:
1740 vgic_its_free_device_list(kvm, its);
1742 case GITS_BASER_TYPE_COLLECTION:
1743 vgic_its_free_collection_list(kvm, its);
1746 mutex_unlock(&its->its_lock);
1750 static unsigned long vgic_mmio_read_its_ctlr(struct kvm *vcpu,
1751 struct vgic_its *its,
1752 gpa_t addr, unsigned int len)
1756 mutex_lock(&its->cmd_lock);
1757 if (its->creadr == its->cwriter)
1758 reg |= GITS_CTLR_QUIESCENT;
1760 reg |= GITS_CTLR_ENABLE;
1761 mutex_unlock(&its->cmd_lock);
1766 static void vgic_mmio_write_its_ctlr(struct kvm *kvm, struct vgic_its *its,
1767 gpa_t addr, unsigned int len,
1770 mutex_lock(&its->cmd_lock);
1773 * It is UNPREDICTABLE to enable the ITS if any of the CBASER or
1774 * device/collection BASER are invalid
1776 if (!its->enabled && (val & GITS_CTLR_ENABLE) &&
1777 (!(its->baser_device_table & GITS_BASER_VALID) ||
1778 !(its->baser_coll_table & GITS_BASER_VALID) ||
1779 !(its->cbaser & GITS_CBASER_VALID)))
1782 its->enabled = !!(val & GITS_CTLR_ENABLE);
1784 vgic_its_invalidate_cache(kvm);
1787 * Try to process any pending commands. This function bails out early
1788 * if the ITS is disabled or no commands have been queued.
1790 vgic_its_process_commands(kvm, its);
1793 mutex_unlock(&its->cmd_lock);
1796 #define REGISTER_ITS_DESC(off, rd, wr, length, acc) \
1798 .reg_offset = off, \
1800 .access_flags = acc, \
1805 #define REGISTER_ITS_DESC_UACCESS(off, rd, wr, uwr, length, acc)\
1807 .reg_offset = off, \
1809 .access_flags = acc, \
1812 .uaccess_its_write = uwr, \
1815 static void its_mmio_write_wi(struct kvm *kvm, struct vgic_its *its,
1816 gpa_t addr, unsigned int len, unsigned long val)
1821 static struct vgic_register_region its_registers[] = {
1822 REGISTER_ITS_DESC(GITS_CTLR,
1823 vgic_mmio_read_its_ctlr, vgic_mmio_write_its_ctlr, 4,
1825 REGISTER_ITS_DESC_UACCESS(GITS_IIDR,
1826 vgic_mmio_read_its_iidr, its_mmio_write_wi,
1827 vgic_mmio_uaccess_write_its_iidr, 4,
1829 REGISTER_ITS_DESC(GITS_TYPER,
1830 vgic_mmio_read_its_typer, its_mmio_write_wi, 8,
1831 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
1832 REGISTER_ITS_DESC(GITS_CBASER,
1833 vgic_mmio_read_its_cbaser, vgic_mmio_write_its_cbaser, 8,
1834 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
1835 REGISTER_ITS_DESC(GITS_CWRITER,
1836 vgic_mmio_read_its_cwriter, vgic_mmio_write_its_cwriter, 8,
1837 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
1838 REGISTER_ITS_DESC_UACCESS(GITS_CREADR,
1839 vgic_mmio_read_its_creadr, its_mmio_write_wi,
1840 vgic_mmio_uaccess_write_its_creadr, 8,
1841 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
1842 REGISTER_ITS_DESC(GITS_BASER,
1843 vgic_mmio_read_its_baser, vgic_mmio_write_its_baser, 0x40,
1844 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
1845 REGISTER_ITS_DESC(GITS_IDREGS_BASE,
1846 vgic_mmio_read_its_idregs, its_mmio_write_wi, 0x30,
1850 /* This is called on setting the LPI enable bit in the redistributor. */
1851 void vgic_enable_lpis(struct kvm_vcpu *vcpu)
1853 if (!(vcpu->arch.vgic_cpu.pendbaser & GICR_PENDBASER_PTZ))
1854 its_sync_lpi_pending_table(vcpu);
1857 static int vgic_register_its_iodev(struct kvm *kvm, struct vgic_its *its,
1860 struct vgic_io_device *iodev = &its->iodev;
1863 mutex_lock(&kvm->slots_lock);
1864 if (!IS_VGIC_ADDR_UNDEF(its->vgic_its_base)) {
1869 its->vgic_its_base = addr;
1870 iodev->regions = its_registers;
1871 iodev->nr_regions = ARRAY_SIZE(its_registers);
1872 kvm_iodevice_init(&iodev->dev, &kvm_io_gic_ops);
1874 iodev->base_addr = its->vgic_its_base;
1875 iodev->iodev_type = IODEV_ITS;
1877 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, iodev->base_addr,
1878 KVM_VGIC_V3_ITS_SIZE, &iodev->dev);
1880 mutex_unlock(&kvm->slots_lock);
1885 /* Default is 16 cached LPIs per vcpu */
1886 #define LPI_DEFAULT_PCPU_CACHE_SIZE 16
1888 void vgic_lpi_translation_cache_init(struct kvm *kvm)
1890 struct vgic_dist *dist = &kvm->arch.vgic;
1894 if (!list_empty(&dist->lpi_translation_cache))
1897 sz = atomic_read(&kvm->online_vcpus) * LPI_DEFAULT_PCPU_CACHE_SIZE;
1899 for (i = 0; i < sz; i++) {
1900 struct vgic_translation_cache_entry *cte;
1902 /* An allocation failure is not fatal */
1903 cte = kzalloc(sizeof(*cte), GFP_KERNEL_ACCOUNT);
1907 INIT_LIST_HEAD(&cte->entry);
1908 list_add(&cte->entry, &dist->lpi_translation_cache);
1912 void vgic_lpi_translation_cache_destroy(struct kvm *kvm)
1914 struct vgic_dist *dist = &kvm->arch.vgic;
1915 struct vgic_translation_cache_entry *cte, *tmp;
1917 vgic_its_invalidate_cache(kvm);
1919 list_for_each_entry_safe(cte, tmp,
1920 &dist->lpi_translation_cache, entry) {
1921 list_del(&cte->entry);
1926 #define INITIAL_BASER_VALUE \
1927 (GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWb) | \
1928 GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, SameAsInner) | \
1929 GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable) | \
1930 GITS_BASER_PAGE_SIZE_64K)
1932 #define INITIAL_PROPBASER_VALUE \
1933 (GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWb) | \
1934 GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, SameAsInner) | \
1935 GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable))
1937 static int vgic_its_create(struct kvm_device *dev, u32 type)
1939 struct vgic_its *its;
1941 if (type != KVM_DEV_TYPE_ARM_VGIC_ITS)
1944 its = kzalloc(sizeof(struct vgic_its), GFP_KERNEL_ACCOUNT);
1948 if (vgic_initialized(dev->kvm)) {
1949 int ret = vgic_v4_init(dev->kvm);
1955 vgic_lpi_translation_cache_init(dev->kvm);
1958 mutex_init(&its->its_lock);
1959 mutex_init(&its->cmd_lock);
1961 /* Yep, even more trickery for lock ordering... */
1962 #ifdef CONFIG_LOCKDEP
1963 mutex_lock(&dev->kvm->arch.config_lock);
1964 mutex_lock(&its->cmd_lock);
1965 mutex_lock(&its->its_lock);
1966 mutex_unlock(&its->its_lock);
1967 mutex_unlock(&its->cmd_lock);
1968 mutex_unlock(&dev->kvm->arch.config_lock);
1971 its->vgic_its_base = VGIC_ADDR_UNDEF;
1973 INIT_LIST_HEAD(&its->device_list);
1974 INIT_LIST_HEAD(&its->collection_list);
1976 dev->kvm->arch.vgic.msis_require_devid = true;
1977 dev->kvm->arch.vgic.has_its = true;
1978 its->enabled = false;
1981 its->baser_device_table = INITIAL_BASER_VALUE |
1982 ((u64)GITS_BASER_TYPE_DEVICE << GITS_BASER_TYPE_SHIFT);
1983 its->baser_coll_table = INITIAL_BASER_VALUE |
1984 ((u64)GITS_BASER_TYPE_COLLECTION << GITS_BASER_TYPE_SHIFT);
1985 dev->kvm->arch.vgic.propbaser = INITIAL_PROPBASER_VALUE;
1989 return vgic_its_set_abi(its, NR_ITS_ABIS - 1);
1992 static void vgic_its_destroy(struct kvm_device *kvm_dev)
1994 struct kvm *kvm = kvm_dev->kvm;
1995 struct vgic_its *its = kvm_dev->private;
1997 mutex_lock(&its->its_lock);
1999 vgic_its_free_device_list(kvm, its);
2000 vgic_its_free_collection_list(kvm, its);
2002 mutex_unlock(&its->its_lock);
2004 kfree(kvm_dev);/* alloc by kvm_ioctl_create_device, free by .destroy */
2007 static int vgic_its_has_attr_regs(struct kvm_device *dev,
2008 struct kvm_device_attr *attr)
2010 const struct vgic_register_region *region;
2011 gpa_t offset = attr->attr;
2014 align = (offset < GITS_TYPER) || (offset >= GITS_PIDR4) ? 0x3 : 0x7;
2019 region = vgic_find_mmio_region(its_registers,
2020 ARRAY_SIZE(its_registers),
2028 static int vgic_its_attr_regs_access(struct kvm_device *dev,
2029 struct kvm_device_attr *attr,
2030 u64 *reg, bool is_write)
2032 const struct vgic_register_region *region;
2033 struct vgic_its *its;
2039 offset = attr->attr;
2042 * Although the spec supports upper/lower 32-bit accesses to
2043 * 64-bit ITS registers, the userspace ABI requires 64-bit
2044 * accesses to all 64-bit wide registers. We therefore only
2045 * support 32-bit accesses to GITS_CTLR, GITS_IIDR and GITS ID
2048 if ((offset < GITS_TYPER) || (offset >= GITS_PIDR4))
2056 mutex_lock(&dev->kvm->lock);
2058 if (!lock_all_vcpus(dev->kvm)) {
2059 mutex_unlock(&dev->kvm->lock);
2063 mutex_lock(&dev->kvm->arch.config_lock);
2065 if (IS_VGIC_ADDR_UNDEF(its->vgic_its_base)) {
2070 region = vgic_find_mmio_region(its_registers,
2071 ARRAY_SIZE(its_registers),
2078 addr = its->vgic_its_base + offset;
2080 len = region->access_flags & VGIC_ACCESS_64bit ? 8 : 4;
2083 if (region->uaccess_its_write)
2084 ret = region->uaccess_its_write(dev->kvm, its, addr,
2087 region->its_write(dev->kvm, its, addr, len, *reg);
2089 *reg = region->its_read(dev->kvm, its, addr, len);
2092 mutex_unlock(&dev->kvm->arch.config_lock);
2093 unlock_all_vcpus(dev->kvm);
2094 mutex_unlock(&dev->kvm->lock);
2098 static u32 compute_next_devid_offset(struct list_head *h,
2099 struct its_device *dev)
2101 struct its_device *next;
2104 if (list_is_last(&dev->dev_list, h))
2106 next = list_next_entry(dev, dev_list);
2107 next_offset = next->device_id - dev->device_id;
2109 return min_t(u32, next_offset, VITS_DTE_MAX_DEVID_OFFSET);
2112 static u32 compute_next_eventid_offset(struct list_head *h, struct its_ite *ite)
2114 struct its_ite *next;
2117 if (list_is_last(&ite->ite_list, h))
2119 next = list_next_entry(ite, ite_list);
2120 next_offset = next->event_id - ite->event_id;
2122 return min_t(u32, next_offset, VITS_ITE_MAX_EVENTID_OFFSET);
2126 * entry_fn_t - Callback called on a table entry restore path
2128 * @id: id of the entry
2129 * @entry: pointer to the entry
2130 * @opaque: pointer to an opaque data
2132 * Return: < 0 on error, 0 if last element was identified, id offset to next
2135 typedef int (*entry_fn_t)(struct vgic_its *its, u32 id, void *entry,
2139 * scan_its_table - Scan a contiguous table in guest RAM and applies a function
2143 * @base: base gpa of the table
2144 * @size: size of the table in bytes
2145 * @esz: entry size in bytes
2146 * @start_id: the ID of the first entry in the table
2147 * (non zero for 2d level tables)
2148 * @fn: function to apply on each entry
2150 * Return: < 0 on error, 0 if last element was identified, 1 otherwise
2151 * (the last element may not be found on second level tables)
2153 static int scan_its_table(struct vgic_its *its, gpa_t base, int size, u32 esz,
2154 int start_id, entry_fn_t fn, void *opaque)
2156 struct kvm *kvm = its->dev->kvm;
2157 unsigned long len = size;
2160 char entry[ESZ_MAX];
2163 memset(entry, 0, esz);
2169 ret = kvm_read_guest_lock(kvm, gpa, entry, esz);
2173 next_offset = fn(its, id, entry, opaque);
2174 if (next_offset <= 0)
2177 byte_offset = next_offset * esz;
2178 if (byte_offset >= len)
2189 * vgic_its_save_ite - Save an interrupt translation entry at @gpa
2191 static int vgic_its_save_ite(struct vgic_its *its, struct its_device *dev,
2192 struct its_ite *ite, gpa_t gpa, int ite_esz)
2194 struct kvm *kvm = its->dev->kvm;
2198 next_offset = compute_next_eventid_offset(&dev->itt_head, ite);
2199 val = ((u64)next_offset << KVM_ITS_ITE_NEXT_SHIFT) |
2200 ((u64)ite->irq->intid << KVM_ITS_ITE_PINTID_SHIFT) |
2201 ite->collection->collection_id;
2202 val = cpu_to_le64(val);
2203 return vgic_write_guest_lock(kvm, gpa, &val, ite_esz);
2207 * vgic_its_restore_ite - restore an interrupt translation entry
2208 * @event_id: id used for indexing
2209 * @ptr: pointer to the ITE entry
2210 * @opaque: pointer to the its_device
2212 static int vgic_its_restore_ite(struct vgic_its *its, u32 event_id,
2213 void *ptr, void *opaque)
2215 struct its_device *dev = opaque;
2216 struct its_collection *collection;
2217 struct kvm *kvm = its->dev->kvm;
2218 struct kvm_vcpu *vcpu = NULL;
2220 u64 *p = (u64 *)ptr;
2221 struct vgic_irq *irq;
2222 u32 coll_id, lpi_id;
2223 struct its_ite *ite;
2228 val = le64_to_cpu(val);
2230 coll_id = val & KVM_ITS_ITE_ICID_MASK;
2231 lpi_id = (val & KVM_ITS_ITE_PINTID_MASK) >> KVM_ITS_ITE_PINTID_SHIFT;
2234 return 1; /* invalid entry, no choice but to scan next entry */
2236 if (lpi_id < VGIC_MIN_LPI)
2239 offset = val >> KVM_ITS_ITE_NEXT_SHIFT;
2240 if (event_id + offset >= BIT_ULL(dev->num_eventid_bits))
2243 collection = find_collection(its, coll_id);
2247 if (!vgic_its_check_event_id(its, dev, event_id))
2250 ite = vgic_its_alloc_ite(dev, collection, event_id);
2252 return PTR_ERR(ite);
2254 if (its_is_collection_mapped(collection))
2255 vcpu = kvm_get_vcpu(kvm, collection->target_addr);
2257 irq = vgic_add_lpi(kvm, lpi_id, vcpu);
2259 its_free_ite(kvm, ite);
2260 return PTR_ERR(irq);
2267 static int vgic_its_ite_cmp(void *priv, const struct list_head *a,
2268 const struct list_head *b)
2270 struct its_ite *itea = container_of(a, struct its_ite, ite_list);
2271 struct its_ite *iteb = container_of(b, struct its_ite, ite_list);
2273 if (itea->event_id < iteb->event_id)
2279 static int vgic_its_save_itt(struct vgic_its *its, struct its_device *device)
2281 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2282 gpa_t base = device->itt_addr;
2283 struct its_ite *ite;
2285 int ite_esz = abi->ite_esz;
2287 list_sort(NULL, &device->itt_head, vgic_its_ite_cmp);
2289 list_for_each_entry(ite, &device->itt_head, ite_list) {
2290 gpa_t gpa = base + ite->event_id * ite_esz;
2293 * If an LPI carries the HW bit, this means that this
2294 * interrupt is controlled by GICv4, and we do not
2295 * have direct access to that state without GICv4.1.
2296 * Let's simply fail the save operation...
2298 if (ite->irq->hw && !kvm_vgic_global_state.has_gicv4_1)
2301 ret = vgic_its_save_ite(its, device, ite, gpa, ite_esz);
2309 * vgic_its_restore_itt - restore the ITT of a device
2312 * @dev: device handle
2314 * Return 0 on success, < 0 on error
2316 static int vgic_its_restore_itt(struct vgic_its *its, struct its_device *dev)
2318 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2319 gpa_t base = dev->itt_addr;
2321 int ite_esz = abi->ite_esz;
2322 size_t max_size = BIT_ULL(dev->num_eventid_bits) * ite_esz;
2324 ret = scan_its_table(its, base, max_size, ite_esz, 0,
2325 vgic_its_restore_ite, dev);
2327 /* scan_its_table returns +1 if all ITEs are invalid */
2335 * vgic_its_save_dte - Save a device table entry at a given GPA
2341 static int vgic_its_save_dte(struct vgic_its *its, struct its_device *dev,
2342 gpa_t ptr, int dte_esz)
2344 struct kvm *kvm = its->dev->kvm;
2345 u64 val, itt_addr_field;
2348 itt_addr_field = dev->itt_addr >> 8;
2349 next_offset = compute_next_devid_offset(&its->device_list, dev);
2350 val = (1ULL << KVM_ITS_DTE_VALID_SHIFT |
2351 ((u64)next_offset << KVM_ITS_DTE_NEXT_SHIFT) |
2352 (itt_addr_field << KVM_ITS_DTE_ITTADDR_SHIFT) |
2353 (dev->num_eventid_bits - 1));
2354 val = cpu_to_le64(val);
2355 return vgic_write_guest_lock(kvm, ptr, &val, dte_esz);
2359 * vgic_its_restore_dte - restore a device table entry
2362 * @id: device id the DTE corresponds to
2363 * @ptr: kernel VA where the 8 byte DTE is located
2366 * Return: < 0 on error, 0 if the dte is the last one, id offset to the
2367 * next dte otherwise
2369 static int vgic_its_restore_dte(struct vgic_its *its, u32 id,
2370 void *ptr, void *opaque)
2372 struct its_device *dev;
2373 u64 baser = its->baser_device_table;
2375 u8 num_eventid_bits;
2376 u64 entry = *(u64 *)ptr;
2381 entry = le64_to_cpu(entry);
2383 valid = entry >> KVM_ITS_DTE_VALID_SHIFT;
2384 num_eventid_bits = (entry & KVM_ITS_DTE_SIZE_MASK) + 1;
2385 itt_addr = ((entry & KVM_ITS_DTE_ITTADDR_MASK)
2386 >> KVM_ITS_DTE_ITTADDR_SHIFT) << 8;
2391 /* dte entry is valid */
2392 offset = (entry & KVM_ITS_DTE_NEXT_MASK) >> KVM_ITS_DTE_NEXT_SHIFT;
2394 if (!vgic_its_check_id(its, baser, id, NULL))
2397 dev = vgic_its_alloc_device(its, id, itt_addr, num_eventid_bits);
2399 return PTR_ERR(dev);
2401 ret = vgic_its_restore_itt(its, dev);
2403 vgic_its_free_device(its->dev->kvm, dev);
2410 static int vgic_its_device_cmp(void *priv, const struct list_head *a,
2411 const struct list_head *b)
2413 struct its_device *deva = container_of(a, struct its_device, dev_list);
2414 struct its_device *devb = container_of(b, struct its_device, dev_list);
2416 if (deva->device_id < devb->device_id)
2423 * vgic_its_save_device_tables - Save the device table and all ITT
2426 * L1/L2 handling is hidden by vgic_its_check_id() helper which directly
2427 * returns the GPA of the device entry
2429 static int vgic_its_save_device_tables(struct vgic_its *its)
2431 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2432 u64 baser = its->baser_device_table;
2433 struct its_device *dev;
2434 int dte_esz = abi->dte_esz;
2436 if (!(baser & GITS_BASER_VALID))
2439 list_sort(NULL, &its->device_list, vgic_its_device_cmp);
2441 list_for_each_entry(dev, &its->device_list, dev_list) {
2445 if (!vgic_its_check_id(its, baser,
2446 dev->device_id, &eaddr))
2449 ret = vgic_its_save_itt(its, dev);
2453 ret = vgic_its_save_dte(its, dev, eaddr, dte_esz);
2461 * handle_l1_dte - callback used for L1 device table entries (2 stage case)
2464 * @id: index of the entry in the L1 table
2468 * L1 table entries are scanned by steps of 1 entry
2469 * Return < 0 if error, 0 if last dte was found when scanning the L2
2470 * table, +1 otherwise (meaning next L1 entry must be scanned)
2472 static int handle_l1_dte(struct vgic_its *its, u32 id, void *addr,
2475 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2476 int l2_start_id = id * (SZ_64K / abi->dte_esz);
2477 u64 entry = *(u64 *)addr;
2478 int dte_esz = abi->dte_esz;
2482 entry = le64_to_cpu(entry);
2484 if (!(entry & KVM_ITS_L1E_VALID_MASK))
2487 gpa = entry & KVM_ITS_L1E_ADDR_MASK;
2489 ret = scan_its_table(its, gpa, SZ_64K, dte_esz,
2490 l2_start_id, vgic_its_restore_dte, NULL);
2496 * vgic_its_restore_device_tables - Restore the device table and all ITT
2497 * from guest RAM to internal data structs
2499 static int vgic_its_restore_device_tables(struct vgic_its *its)
2501 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2502 u64 baser = its->baser_device_table;
2504 int l1_tbl_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
2507 if (!(baser & GITS_BASER_VALID))
2510 l1_gpa = GITS_BASER_ADDR_48_to_52(baser);
2512 if (baser & GITS_BASER_INDIRECT) {
2513 l1_esz = GITS_LVL1_ENTRY_SIZE;
2514 ret = scan_its_table(its, l1_gpa, l1_tbl_size, l1_esz, 0,
2515 handle_l1_dte, NULL);
2517 l1_esz = abi->dte_esz;
2518 ret = scan_its_table(its, l1_gpa, l1_tbl_size, l1_esz, 0,
2519 vgic_its_restore_dte, NULL);
2522 /* scan_its_table returns +1 if all entries are invalid */
2527 vgic_its_free_device_list(its->dev->kvm, its);
2532 static int vgic_its_save_cte(struct vgic_its *its,
2533 struct its_collection *collection,
2538 val = (1ULL << KVM_ITS_CTE_VALID_SHIFT |
2539 ((u64)collection->target_addr << KVM_ITS_CTE_RDBASE_SHIFT) |
2540 collection->collection_id);
2541 val = cpu_to_le64(val);
2542 return vgic_write_guest_lock(its->dev->kvm, gpa, &val, esz);
2546 * Restore a collection entry into the ITS collection table.
2547 * Return +1 on success, 0 if the entry was invalid (which should be
2548 * interpreted as end-of-table), and a negative error value for generic errors.
2550 static int vgic_its_restore_cte(struct vgic_its *its, gpa_t gpa, int esz)
2552 struct its_collection *collection;
2553 struct kvm *kvm = its->dev->kvm;
2554 u32 target_addr, coll_id;
2558 BUG_ON(esz > sizeof(val));
2559 ret = kvm_read_guest_lock(kvm, gpa, &val, esz);
2562 val = le64_to_cpu(val);
2563 if (!(val & KVM_ITS_CTE_VALID_MASK))
2566 target_addr = (u32)(val >> KVM_ITS_CTE_RDBASE_SHIFT);
2567 coll_id = val & KVM_ITS_CTE_ICID_MASK;
2569 if (target_addr != COLLECTION_NOT_MAPPED &&
2570 target_addr >= atomic_read(&kvm->online_vcpus))
2573 collection = find_collection(its, coll_id);
2577 if (!vgic_its_check_id(its, its->baser_coll_table, coll_id, NULL))
2580 ret = vgic_its_alloc_collection(its, &collection, coll_id);
2583 collection->target_addr = target_addr;
2588 * vgic_its_save_collection_table - Save the collection table into
2591 static int vgic_its_save_collection_table(struct vgic_its *its)
2593 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2594 u64 baser = its->baser_coll_table;
2595 gpa_t gpa = GITS_BASER_ADDR_48_to_52(baser);
2596 struct its_collection *collection;
2598 size_t max_size, filled = 0;
2599 int ret, cte_esz = abi->cte_esz;
2601 if (!(baser & GITS_BASER_VALID))
2604 max_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
2606 list_for_each_entry(collection, &its->collection_list, coll_list) {
2607 ret = vgic_its_save_cte(its, collection, gpa, cte_esz);
2614 if (filled == max_size)
2618 * table is not fully filled, add a last dummy element
2619 * with valid bit unset
2622 BUG_ON(cte_esz > sizeof(val));
2623 ret = vgic_write_guest_lock(its->dev->kvm, gpa, &val, cte_esz);
2628 * vgic_its_restore_collection_table - reads the collection table
2629 * in guest memory and restores the ITS internal state. Requires the
2630 * BASER registers to be restored before.
2632 static int vgic_its_restore_collection_table(struct vgic_its *its)
2634 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2635 u64 baser = its->baser_coll_table;
2636 int cte_esz = abi->cte_esz;
2637 size_t max_size, read = 0;
2641 if (!(baser & GITS_BASER_VALID))
2644 gpa = GITS_BASER_ADDR_48_to_52(baser);
2646 max_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
2648 while (read < max_size) {
2649 ret = vgic_its_restore_cte(its, gpa, cte_esz);
2660 vgic_its_free_collection_list(its->dev->kvm, its);
2666 * vgic_its_save_tables_v0 - Save the ITS tables into guest ARM
2667 * according to v0 ABI
2669 static int vgic_its_save_tables_v0(struct vgic_its *its)
2673 ret = vgic_its_save_device_tables(its);
2677 return vgic_its_save_collection_table(its);
2681 * vgic_its_restore_tables_v0 - Restore the ITS tables from guest RAM
2682 * to internal data structs according to V0 ABI
2685 static int vgic_its_restore_tables_v0(struct vgic_its *its)
2689 ret = vgic_its_restore_collection_table(its);
2693 ret = vgic_its_restore_device_tables(its);
2695 vgic_its_free_collection_list(its->dev->kvm, its);
2699 static int vgic_its_commit_v0(struct vgic_its *its)
2701 const struct vgic_its_abi *abi;
2703 abi = vgic_its_get_abi(its);
2704 its->baser_coll_table &= ~GITS_BASER_ENTRY_SIZE_MASK;
2705 its->baser_device_table &= ~GITS_BASER_ENTRY_SIZE_MASK;
2707 its->baser_coll_table |= (GIC_ENCODE_SZ(abi->cte_esz, 5)
2708 << GITS_BASER_ENTRY_SIZE_SHIFT);
2710 its->baser_device_table |= (GIC_ENCODE_SZ(abi->dte_esz, 5)
2711 << GITS_BASER_ENTRY_SIZE_SHIFT);
2715 static void vgic_its_reset(struct kvm *kvm, struct vgic_its *its)
2717 /* We need to keep the ABI specific field values */
2718 its->baser_coll_table &= ~GITS_BASER_VALID;
2719 its->baser_device_table &= ~GITS_BASER_VALID;
2724 vgic_its_free_device_list(kvm, its);
2725 vgic_its_free_collection_list(kvm, its);
2728 static int vgic_its_has_attr(struct kvm_device *dev,
2729 struct kvm_device_attr *attr)
2731 switch (attr->group) {
2732 case KVM_DEV_ARM_VGIC_GRP_ADDR:
2733 switch (attr->attr) {
2734 case KVM_VGIC_ITS_ADDR_TYPE:
2738 case KVM_DEV_ARM_VGIC_GRP_CTRL:
2739 switch (attr->attr) {
2740 case KVM_DEV_ARM_VGIC_CTRL_INIT:
2742 case KVM_DEV_ARM_ITS_CTRL_RESET:
2744 case KVM_DEV_ARM_ITS_SAVE_TABLES:
2746 case KVM_DEV_ARM_ITS_RESTORE_TABLES:
2750 case KVM_DEV_ARM_VGIC_GRP_ITS_REGS:
2751 return vgic_its_has_attr_regs(dev, attr);
2756 static int vgic_its_ctrl(struct kvm *kvm, struct vgic_its *its, u64 attr)
2758 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2761 if (attr == KVM_DEV_ARM_VGIC_CTRL_INIT) /* Nothing to do */
2764 mutex_lock(&kvm->lock);
2766 if (!lock_all_vcpus(kvm)) {
2767 mutex_unlock(&kvm->lock);
2771 mutex_lock(&kvm->arch.config_lock);
2772 mutex_lock(&its->its_lock);
2775 case KVM_DEV_ARM_ITS_CTRL_RESET:
2776 vgic_its_reset(kvm, its);
2778 case KVM_DEV_ARM_ITS_SAVE_TABLES:
2779 ret = abi->save_tables(its);
2781 case KVM_DEV_ARM_ITS_RESTORE_TABLES:
2782 ret = abi->restore_tables(its);
2786 mutex_unlock(&its->its_lock);
2787 mutex_unlock(&kvm->arch.config_lock);
2788 unlock_all_vcpus(kvm);
2789 mutex_unlock(&kvm->lock);
2794 * kvm_arch_allow_write_without_running_vcpu - allow writing guest memory
2795 * without the running VCPU when dirty ring is enabled.
2797 * The running VCPU is required to track dirty guest pages when dirty ring
2798 * is enabled. Otherwise, the backup bitmap should be used to track the
2799 * dirty guest pages. When vgic/its tables are being saved, the backup
2800 * bitmap is used to track the dirty guest pages due to the missed running
2801 * VCPU in the period.
2803 bool kvm_arch_allow_write_without_running_vcpu(struct kvm *kvm)
2805 struct vgic_dist *dist = &kvm->arch.vgic;
2807 return dist->table_write_in_progress;
2810 static int vgic_its_set_attr(struct kvm_device *dev,
2811 struct kvm_device_attr *attr)
2813 struct vgic_its *its = dev->private;
2816 switch (attr->group) {
2817 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
2818 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2819 unsigned long type = (unsigned long)attr->attr;
2822 if (type != KVM_VGIC_ITS_ADDR_TYPE)
2825 if (copy_from_user(&addr, uaddr, sizeof(addr)))
2828 ret = vgic_check_iorange(dev->kvm, its->vgic_its_base,
2829 addr, SZ_64K, KVM_VGIC_V3_ITS_SIZE);
2833 return vgic_register_its_iodev(dev->kvm, its, addr);
2835 case KVM_DEV_ARM_VGIC_GRP_CTRL:
2836 return vgic_its_ctrl(dev->kvm, its, attr->attr);
2837 case KVM_DEV_ARM_VGIC_GRP_ITS_REGS: {
2838 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2841 if (get_user(reg, uaddr))
2844 return vgic_its_attr_regs_access(dev, attr, ®, true);
2850 static int vgic_its_get_attr(struct kvm_device *dev,
2851 struct kvm_device_attr *attr)
2853 switch (attr->group) {
2854 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
2855 struct vgic_its *its = dev->private;
2856 u64 addr = its->vgic_its_base;
2857 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2858 unsigned long type = (unsigned long)attr->attr;
2860 if (type != KVM_VGIC_ITS_ADDR_TYPE)
2863 if (copy_to_user(uaddr, &addr, sizeof(addr)))
2867 case KVM_DEV_ARM_VGIC_GRP_ITS_REGS: {
2868 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2872 ret = vgic_its_attr_regs_access(dev, attr, ®, false);
2875 return put_user(reg, uaddr);
2884 static struct kvm_device_ops kvm_arm_vgic_its_ops = {
2885 .name = "kvm-arm-vgic-its",
2886 .create = vgic_its_create,
2887 .destroy = vgic_its_destroy,
2888 .set_attr = vgic_its_set_attr,
2889 .get_attr = vgic_its_get_attr,
2890 .has_attr = vgic_its_has_attr,
2893 int kvm_vgic_register_its_device(void)
2895 return kvm_register_device_ops(&kvm_arm_vgic_its_ops,
2896 KVM_DEV_TYPE_ARM_VGIC_ITS);