1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
6 * Derived from arch/arm/kvm/coproc.c:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Authors: Rusty Russell <rusty@rustcorp.com.au>
9 * Christoffer Dall <c.dall@virtualopensystems.com>
12 #include <linux/bitfield.h>
13 #include <linux/bsearch.h>
14 #include <linux/kvm_host.h>
16 #include <linux/printk.h>
17 #include <linux/uaccess.h>
19 #include <asm/cacheflush.h>
20 #include <asm/cputype.h>
21 #include <asm/debug-monitors.h>
23 #include <asm/kvm_arm.h>
24 #include <asm/kvm_emulate.h>
25 #include <asm/kvm_hyp.h>
26 #include <asm/kvm_mmu.h>
27 #include <asm/perf_event.h>
28 #include <asm/sysreg.h>
30 #include <trace/events/kvm.h>
37 * For AArch32, we only take care of what is being trapped. Anything
38 * that has to do with init and userspace access has to go via the
42 static u64 sys_reg_to_index(const struct sys_reg_desc *reg);
44 static bool read_from_write_only(struct kvm_vcpu *vcpu,
45 struct sys_reg_params *params,
46 const struct sys_reg_desc *r)
48 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n");
49 print_sys_reg_instr(params);
50 kvm_inject_undefined(vcpu);
54 static bool write_to_read_only(struct kvm_vcpu *vcpu,
55 struct sys_reg_params *params,
56 const struct sys_reg_desc *r)
58 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n");
59 print_sys_reg_instr(params);
60 kvm_inject_undefined(vcpu);
64 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
66 u64 val = 0x8badf00d8badf00d;
68 if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) &&
69 __vcpu_read_sys_reg_from_cpu(reg, &val))
72 return __vcpu_sys_reg(vcpu, reg);
75 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
77 if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) &&
78 __vcpu_write_sys_reg_to_cpu(val, reg))
81 __vcpu_sys_reg(vcpu, reg) = val;
84 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
85 static u32 cache_levels;
87 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
90 /* Which cache CCSIDR represents depends on CSSELR value. */
91 static u32 get_ccsidr(u32 csselr)
95 /* Make sure noone else changes CSSELR during this! */
97 write_sysreg(csselr, csselr_el1);
99 ccsidr = read_sysreg(ccsidr_el1);
106 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
108 static bool access_dcsw(struct kvm_vcpu *vcpu,
109 struct sys_reg_params *p,
110 const struct sys_reg_desc *r)
113 return read_from_write_only(vcpu, p, r);
116 * Only track S/W ops if we don't have FWB. It still indicates
117 * that the guest is a bit broken (S/W operations should only
118 * be done by firmware, knowing that there is only a single
119 * CPU left in the system, and certainly not from non-secure
122 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
123 kvm_set_way_flush(vcpu);
128 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift)
130 switch (r->aarch32_map) {
132 *mask = GENMASK_ULL(31, 0);
136 *mask = GENMASK_ULL(63, 32);
140 *mask = GENMASK_ULL(63, 0);
147 * Generic accessor for VM registers. Only called as long as HCR_TVM
148 * is set. If the guest enables the MMU, we stop trapping the VM
149 * sys_regs and leave it in complete control of the caches.
151 static bool access_vm_reg(struct kvm_vcpu *vcpu,
152 struct sys_reg_params *p,
153 const struct sys_reg_desc *r)
155 bool was_enabled = vcpu_has_cache_enabled(vcpu);
156 u64 val, mask, shift;
158 BUG_ON(!p->is_write);
160 get_access_mask(r, &mask, &shift);
163 val = vcpu_read_sys_reg(vcpu, r->reg);
169 val |= (p->regval & (mask >> shift)) << shift;
170 vcpu_write_sys_reg(vcpu, val, r->reg);
172 kvm_toggle_cache(vcpu, was_enabled);
176 static bool access_actlr(struct kvm_vcpu *vcpu,
177 struct sys_reg_params *p,
178 const struct sys_reg_desc *r)
183 return ignore_write(vcpu, p);
185 get_access_mask(r, &mask, &shift);
186 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift;
192 * Trap handler for the GICv3 SGI generation system register.
193 * Forward the request to the VGIC emulation.
194 * The cp15_64 code makes sure this automatically works
195 * for both AArch64 and AArch32 accesses.
197 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
198 struct sys_reg_params *p,
199 const struct sys_reg_desc *r)
204 return read_from_write_only(vcpu, p, r);
207 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates
208 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group,
209 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively
210 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure
213 if (p->Op0 == 0) { /* AArch32 */
215 default: /* Keep GCC quiet */
216 case 0: /* ICC_SGI1R */
219 case 1: /* ICC_ASGI1R */
220 case 2: /* ICC_SGI0R */
224 } else { /* AArch64 */
226 default: /* Keep GCC quiet */
227 case 5: /* ICC_SGI1R_EL1 */
230 case 6: /* ICC_ASGI1R_EL1 */
231 case 7: /* ICC_SGI0R_EL1 */
237 vgic_v3_dispatch_sgi(vcpu, p->regval, g1);
242 static bool access_gic_sre(struct kvm_vcpu *vcpu,
243 struct sys_reg_params *p,
244 const struct sys_reg_desc *r)
247 return ignore_write(vcpu, p);
249 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
253 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
254 struct sys_reg_params *p,
255 const struct sys_reg_desc *r)
258 return ignore_write(vcpu, p);
260 return read_zero(vcpu, p);
264 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
265 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
266 * system, these registers should UNDEF. LORID_EL1 being a RO register, we
267 * treat it separately.
269 static bool trap_loregion(struct kvm_vcpu *vcpu,
270 struct sys_reg_params *p,
271 const struct sys_reg_desc *r)
273 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
274 u32 sr = reg_to_encoding(r);
276 if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) {
277 kvm_inject_undefined(vcpu);
281 if (p->is_write && sr == SYS_LORID_EL1)
282 return write_to_read_only(vcpu, p, r);
284 return trap_raz_wi(vcpu, p, r);
287 static bool trap_oslar_el1(struct kvm_vcpu *vcpu,
288 struct sys_reg_params *p,
289 const struct sys_reg_desc *r)
294 return read_from_write_only(vcpu, p, r);
296 /* Forward the OSLK bit to OSLSR */
297 oslsr = __vcpu_sys_reg(vcpu, OSLSR_EL1) & ~SYS_OSLSR_OSLK;
298 if (p->regval & SYS_OSLAR_OSLK)
299 oslsr |= SYS_OSLSR_OSLK;
301 __vcpu_sys_reg(vcpu, OSLSR_EL1) = oslsr;
305 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
306 struct sys_reg_params *p,
307 const struct sys_reg_desc *r)
310 return write_to_read_only(vcpu, p, r);
312 p->regval = __vcpu_sys_reg(vcpu, r->reg);
316 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
320 * The only modifiable bit is the OSLK bit. Refuse the write if
321 * userspace attempts to change any other bit in the register.
323 if ((val ^ rd->val) & ~SYS_OSLSR_OSLK)
326 __vcpu_sys_reg(vcpu, rd->reg) = val;
330 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
331 struct sys_reg_params *p,
332 const struct sys_reg_desc *r)
335 return ignore_write(vcpu, p);
337 p->regval = read_sysreg(dbgauthstatus_el1);
343 * We want to avoid world-switching all the DBG registers all the
346 * - If we've touched any debug register, it is likely that we're
347 * going to touch more of them. It then makes sense to disable the
348 * traps and start doing the save/restore dance
349 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
350 * then mandatory to save/restore the registers, as the guest
353 * For this, we use a DIRTY bit, indicating the guest has modified the
354 * debug registers, used as follow:
357 * - If the dirty bit is set (because we're coming back from trapping),
358 * disable the traps, save host registers, restore guest registers.
359 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
360 * set the dirty bit, disable the traps, save host registers,
361 * restore guest registers.
362 * - Otherwise, enable the traps
365 * - If the dirty bit is set, save guest registers, restore host
366 * registers and clear the dirty bit. This ensure that the host can
367 * now use the debug registers.
369 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
370 struct sys_reg_params *p,
371 const struct sys_reg_desc *r)
374 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
375 vcpu_set_flag(vcpu, DEBUG_DIRTY);
377 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
380 trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
386 * reg_to_dbg/dbg_to_reg
388 * A 32 bit write to a debug register leave top bits alone
389 * A 32 bit read from a debug register only returns the bottom bits
391 * All writes will set the DEBUG_DIRTY flag to ensure the hyp code
392 * switches between host and guest values in future.
394 static void reg_to_dbg(struct kvm_vcpu *vcpu,
395 struct sys_reg_params *p,
396 const struct sys_reg_desc *rd,
399 u64 mask, shift, val;
401 get_access_mask(rd, &mask, &shift);
405 val |= (p->regval & (mask >> shift)) << shift;
408 vcpu_set_flag(vcpu, DEBUG_DIRTY);
411 static void dbg_to_reg(struct kvm_vcpu *vcpu,
412 struct sys_reg_params *p,
413 const struct sys_reg_desc *rd,
418 get_access_mask(rd, &mask, &shift);
419 p->regval = (*dbg_reg & mask) >> shift;
422 static bool trap_bvr(struct kvm_vcpu *vcpu,
423 struct sys_reg_params *p,
424 const struct sys_reg_desc *rd)
426 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
429 reg_to_dbg(vcpu, p, rd, dbg_reg);
431 dbg_to_reg(vcpu, p, rd, dbg_reg);
433 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
438 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
441 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = val;
445 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
448 *val = vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
452 static void reset_bvr(struct kvm_vcpu *vcpu,
453 const struct sys_reg_desc *rd)
455 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val;
458 static bool trap_bcr(struct kvm_vcpu *vcpu,
459 struct sys_reg_params *p,
460 const struct sys_reg_desc *rd)
462 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
465 reg_to_dbg(vcpu, p, rd, dbg_reg);
467 dbg_to_reg(vcpu, p, rd, dbg_reg);
469 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
474 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
477 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = val;
481 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
484 *val = vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
488 static void reset_bcr(struct kvm_vcpu *vcpu,
489 const struct sys_reg_desc *rd)
491 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val;
494 static bool trap_wvr(struct kvm_vcpu *vcpu,
495 struct sys_reg_params *p,
496 const struct sys_reg_desc *rd)
498 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
501 reg_to_dbg(vcpu, p, rd, dbg_reg);
503 dbg_to_reg(vcpu, p, rd, dbg_reg);
505 trace_trap_reg(__func__, rd->CRm, p->is_write,
506 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]);
511 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
514 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = val;
518 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
521 *val = vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
525 static void reset_wvr(struct kvm_vcpu *vcpu,
526 const struct sys_reg_desc *rd)
528 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val;
531 static bool trap_wcr(struct kvm_vcpu *vcpu,
532 struct sys_reg_params *p,
533 const struct sys_reg_desc *rd)
535 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
538 reg_to_dbg(vcpu, p, rd, dbg_reg);
540 dbg_to_reg(vcpu, p, rd, dbg_reg);
542 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
547 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
550 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = val;
554 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
557 *val = vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
561 static void reset_wcr(struct kvm_vcpu *vcpu,
562 const struct sys_reg_desc *rd)
564 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val;
567 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
569 u64 amair = read_sysreg(amair_el1);
570 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
573 static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
575 u64 actlr = read_sysreg(actlr_el1);
576 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1);
579 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
584 * Map the vcpu_id into the first three affinity level fields of
585 * the MPIDR. We limit the number of VCPUs in level 0 due to a
586 * limitation to 16 CPUs in that level in the ICC_SGIxR registers
587 * of the GICv3 to be able to address each CPU directly when
590 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
591 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
592 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
593 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1);
596 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu,
597 const struct sys_reg_desc *r)
599 if (kvm_vcpu_has_pmu(vcpu))
605 static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
607 u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX);
609 /* No PMU available, any PMU reg may UNDEF... */
610 if (!kvm_arm_support_pmu_v3())
613 n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT;
614 n &= ARMV8_PMU_PMCR_N_MASK;
616 mask |= GENMASK(n - 1, 0);
618 reset_unknown(vcpu, r);
619 __vcpu_sys_reg(vcpu, r->reg) &= mask;
622 static void reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
624 reset_unknown(vcpu, r);
625 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0);
628 static void reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
630 reset_unknown(vcpu, r);
631 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_EVTYPE_MASK;
634 static void reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
636 reset_unknown(vcpu, r);
637 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK;
640 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
644 /* No PMU available, PMCR_EL0 may UNDEF... */
645 if (!kvm_arm_support_pmu_v3())
648 pmcr = read_sysreg(pmcr_el0);
650 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
651 * except PMCR.E resetting to zero.
653 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
654 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
655 if (!system_supports_32bit_el0())
656 val |= ARMV8_PMU_PMCR_LC;
657 __vcpu_sys_reg(vcpu, r->reg) = val;
660 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
662 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
663 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
666 kvm_inject_undefined(vcpu);
671 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
673 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
676 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
678 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
681 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
683 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
686 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
688 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
691 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
692 const struct sys_reg_desc *r)
696 if (pmu_access_el0_disabled(vcpu))
700 /* Only update writeable bits of PMCR */
701 val = __vcpu_sys_reg(vcpu, PMCR_EL0);
702 val &= ~ARMV8_PMU_PMCR_MASK;
703 val |= p->regval & ARMV8_PMU_PMCR_MASK;
704 if (!system_supports_32bit_el0())
705 val |= ARMV8_PMU_PMCR_LC;
706 __vcpu_sys_reg(vcpu, PMCR_EL0) = val;
707 kvm_pmu_handle_pmcr(vcpu, val);
708 kvm_vcpu_pmu_restore_guest(vcpu);
710 /* PMCR.P & PMCR.C are RAZ */
711 val = __vcpu_sys_reg(vcpu, PMCR_EL0)
712 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
719 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
720 const struct sys_reg_desc *r)
722 if (pmu_access_event_counter_el0_disabled(vcpu))
726 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
728 /* return PMSELR.SEL field */
729 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
730 & ARMV8_PMU_COUNTER_MASK;
735 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
736 const struct sys_reg_desc *r)
738 u64 pmceid, mask, shift;
742 if (pmu_access_el0_disabled(vcpu))
745 get_access_mask(r, &mask, &shift);
747 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1));
756 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
760 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0);
761 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
762 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
763 kvm_inject_undefined(vcpu);
770 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
771 struct sys_reg_params *p,
772 const struct sys_reg_desc *r)
776 if (r->CRn == 9 && r->CRm == 13) {
779 if (pmu_access_event_counter_el0_disabled(vcpu))
782 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0)
783 & ARMV8_PMU_COUNTER_MASK;
784 } else if (r->Op2 == 0) {
786 if (pmu_access_cycle_counter_el0_disabled(vcpu))
789 idx = ARMV8_PMU_CYCLE_IDX;
791 } else if (r->CRn == 0 && r->CRm == 9) {
793 if (pmu_access_event_counter_el0_disabled(vcpu))
796 idx = ARMV8_PMU_CYCLE_IDX;
797 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
799 if (pmu_access_event_counter_el0_disabled(vcpu))
802 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
805 /* Catch any decoding mistake */
806 WARN_ON(idx == ~0UL);
808 if (!pmu_counter_idx_valid(vcpu, idx))
812 if (pmu_access_el0_disabled(vcpu))
815 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
817 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
823 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
824 const struct sys_reg_desc *r)
828 if (pmu_access_el0_disabled(vcpu))
831 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
833 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
834 reg = PMEVTYPER0_EL0 + idx;
835 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
836 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
837 if (idx == ARMV8_PMU_CYCLE_IDX)
841 reg = PMEVTYPER0_EL0 + idx;
846 if (!pmu_counter_idx_valid(vcpu, idx))
850 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
851 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
852 kvm_vcpu_pmu_restore_guest(vcpu);
854 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
860 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
861 const struct sys_reg_desc *r)
865 if (pmu_access_el0_disabled(vcpu))
868 mask = kvm_pmu_valid_counter_mask(vcpu);
870 val = p->regval & mask;
872 /* accessing PMCNTENSET_EL0 */
873 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
874 kvm_pmu_enable_counter_mask(vcpu, val);
875 kvm_vcpu_pmu_restore_guest(vcpu);
877 /* accessing PMCNTENCLR_EL0 */
878 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
879 kvm_pmu_disable_counter_mask(vcpu, val);
882 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
888 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
889 const struct sys_reg_desc *r)
891 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
893 if (check_pmu_access_disabled(vcpu, 0))
897 u64 val = p->regval & mask;
900 /* accessing PMINTENSET_EL1 */
901 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
903 /* accessing PMINTENCLR_EL1 */
904 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
906 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1);
912 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
913 const struct sys_reg_desc *r)
915 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
917 if (pmu_access_el0_disabled(vcpu))
922 /* accessing PMOVSSET_EL0 */
923 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
925 /* accessing PMOVSCLR_EL0 */
926 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
928 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);
934 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
935 const struct sys_reg_desc *r)
940 return read_from_write_only(vcpu, p, r);
942 if (pmu_write_swinc_el0_disabled(vcpu))
945 mask = kvm_pmu_valid_counter_mask(vcpu);
946 kvm_pmu_software_increment(vcpu, p->regval & mask);
950 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
951 const struct sys_reg_desc *r)
954 if (!vcpu_mode_priv(vcpu)) {
955 kvm_inject_undefined(vcpu);
959 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) =
960 p->regval & ARMV8_PMU_USERENR_MASK;
962 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
963 & ARMV8_PMU_USERENR_MASK;
969 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
970 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \
971 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \
972 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \
973 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \
974 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \
975 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \
976 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \
977 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \
978 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr }
980 #define PMU_SYS_REG(r) \
981 SYS_DESC(r), .reset = reset_pmu_reg, .visibility = pmu_visibility
983 /* Macro to expand the PMEVCNTRn_EL0 register */
984 #define PMU_PMEVCNTR_EL0(n) \
985 { PMU_SYS_REG(SYS_PMEVCNTRn_EL0(n)), \
986 .reset = reset_pmevcntr, \
987 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), }
989 /* Macro to expand the PMEVTYPERn_EL0 register */
990 #define PMU_PMEVTYPER_EL0(n) \
991 { PMU_SYS_REG(SYS_PMEVTYPERn_EL0(n)), \
992 .reset = reset_pmevtyper, \
993 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), }
995 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
996 const struct sys_reg_desc *r)
998 kvm_inject_undefined(vcpu);
1003 /* Macro to expand the AMU counter and type registers*/
1004 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access }
1005 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access }
1006 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access }
1007 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access }
1009 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu,
1010 const struct sys_reg_desc *rd)
1012 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN;
1016 * If we land here on a PtrAuth access, that is because we didn't
1017 * fixup the access on exit by allowing the PtrAuth sysregs. The only
1018 * way this happens is when the guest does not have PtrAuth support
1021 #define __PTRAUTH_KEY(k) \
1022 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \
1023 .visibility = ptrauth_visibility}
1025 #define PTRAUTH_KEY(k) \
1026 __PTRAUTH_KEY(k ## KEYLO_EL1), \
1027 __PTRAUTH_KEY(k ## KEYHI_EL1)
1029 static bool access_arch_timer(struct kvm_vcpu *vcpu,
1030 struct sys_reg_params *p,
1031 const struct sys_reg_desc *r)
1033 enum kvm_arch_timers tmr;
1034 enum kvm_arch_timer_regs treg;
1035 u64 reg = reg_to_encoding(r);
1038 case SYS_CNTP_TVAL_EL0:
1039 case SYS_AARCH32_CNTP_TVAL:
1041 treg = TIMER_REG_TVAL;
1043 case SYS_CNTP_CTL_EL0:
1044 case SYS_AARCH32_CNTP_CTL:
1046 treg = TIMER_REG_CTL;
1048 case SYS_CNTP_CVAL_EL0:
1049 case SYS_AARCH32_CNTP_CVAL:
1051 treg = TIMER_REG_CVAL;
1058 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval);
1060 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg);
1065 /* Read a sanitised cpufeature ID register by sys_reg_desc */
1066 static u64 read_id_reg(const struct kvm_vcpu *vcpu,
1067 struct sys_reg_desc const *r, bool raz)
1069 u32 id = reg_to_encoding(r);
1075 val = read_sanitised_ftr_reg(id);
1078 case SYS_ID_AA64PFR0_EL1:
1079 if (!vcpu_has_sve(vcpu))
1080 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_SVE);
1081 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_AMU);
1082 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2);
1083 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2);
1084 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3);
1085 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3);
1086 if (kvm_vgic_global_state.type == VGIC_V3) {
1087 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_GIC);
1088 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_GIC), 1);
1091 case SYS_ID_AA64PFR1_EL1:
1092 if (!kvm_has_mte(vcpu->kvm))
1093 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE);
1095 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_SME);
1097 case SYS_ID_AA64ISAR1_EL1:
1098 if (!vcpu_has_ptrauth(vcpu))
1099 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) |
1100 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) |
1101 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) |
1102 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI));
1104 case SYS_ID_AA64ISAR2_EL1:
1105 if (!vcpu_has_ptrauth(vcpu))
1106 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) |
1107 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3));
1108 if (!cpus_have_final_cap(ARM64_HAS_WFXT))
1109 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT);
1111 case SYS_ID_AA64DFR0_EL1:
1112 /* Limit debug to ARMv8.0 */
1113 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER);
1114 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER), 6);
1115 /* Limit guests to PMUv3 for ARMv8.4 */
1116 val = cpuid_feature_cap_perfmon_field(val,
1117 ID_AA64DFR0_PMUVER_SHIFT,
1118 kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_4 : 0);
1119 /* Hide SPE from guests */
1120 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_PMSVER);
1122 case SYS_ID_DFR0_EL1:
1123 /* Limit guests to PMUv3 for ARMv8.4 */
1124 val = cpuid_feature_cap_perfmon_field(val,
1125 ID_DFR0_PERFMON_SHIFT,
1126 kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0);
1133 static unsigned int id_visibility(const struct kvm_vcpu *vcpu,
1134 const struct sys_reg_desc *r)
1136 u32 id = reg_to_encoding(r);
1139 case SYS_ID_AA64ZFR0_EL1:
1140 if (!vcpu_has_sve(vcpu))
1148 /* cpufeature ID register access trap handlers */
1150 static bool __access_id_reg(struct kvm_vcpu *vcpu,
1151 struct sys_reg_params *p,
1152 const struct sys_reg_desc *r,
1156 return write_to_read_only(vcpu, p, r);
1158 p->regval = read_id_reg(vcpu, r, raz);
1162 static bool access_id_reg(struct kvm_vcpu *vcpu,
1163 struct sys_reg_params *p,
1164 const struct sys_reg_desc *r)
1166 bool raz = sysreg_visible_as_raz(vcpu, r);
1168 return __access_id_reg(vcpu, p, r, raz);
1171 static bool access_raz_id_reg(struct kvm_vcpu *vcpu,
1172 struct sys_reg_params *p,
1173 const struct sys_reg_desc *r)
1175 return __access_id_reg(vcpu, p, r, true);
1178 /* Visibility overrides for SVE-specific control registers */
1179 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
1180 const struct sys_reg_desc *rd)
1182 if (vcpu_has_sve(vcpu))
1188 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
1189 const struct sys_reg_desc *rd,
1195 * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as
1196 * it doesn't promise more than what is actually provided (the
1197 * guest could otherwise be covered in ectoplasmic residue).
1199 csv2 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV2_SHIFT);
1201 (csv2 && arm64_get_spectre_v2_state() != SPECTRE_UNAFFECTED))
1204 /* Same thing for CSV3 */
1205 csv3 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV3_SHIFT);
1207 (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED))
1210 /* We can only differ with CSV[23], and anything else is an error */
1211 val ^= read_id_reg(vcpu, rd, false);
1212 val &= ~((0xFUL << ID_AA64PFR0_CSV2_SHIFT) |
1213 (0xFUL << ID_AA64PFR0_CSV3_SHIFT));
1217 vcpu->kvm->arch.pfr0_csv2 = csv2;
1218 vcpu->kvm->arch.pfr0_csv3 = csv3;
1224 * cpufeature ID register user accessors
1226 * For now, these registers are immutable for userspace, so no values
1227 * are stored, and for set_id_reg() we don't allow the effective value
1230 static int __get_id_reg(const struct kvm_vcpu *vcpu,
1231 const struct sys_reg_desc *rd, u64 *val,
1234 *val = read_id_reg(vcpu, rd, raz);
1238 static int __set_id_reg(const struct kvm_vcpu *vcpu,
1239 const struct sys_reg_desc *rd, u64 val,
1242 /* This is what we mean by invariant: you can't change it. */
1243 if (val != read_id_reg(vcpu, rd, raz))
1249 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1252 bool raz = sysreg_visible_as_raz(vcpu, rd);
1254 return __get_id_reg(vcpu, rd, val, raz);
1257 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1260 bool raz = sysreg_visible_as_raz(vcpu, rd);
1262 return __set_id_reg(vcpu, rd, val, raz);
1265 static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1268 return __set_id_reg(vcpu, rd, val, true);
1271 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1278 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1284 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1285 const struct sys_reg_desc *r)
1288 return write_to_read_only(vcpu, p, r);
1290 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0);
1294 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1295 const struct sys_reg_desc *r)
1298 return write_to_read_only(vcpu, p, r);
1300 p->regval = read_sysreg(clidr_el1);
1304 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1305 const struct sys_reg_desc *r)
1310 vcpu_write_sys_reg(vcpu, p->regval, reg);
1312 p->regval = vcpu_read_sys_reg(vcpu, reg);
1316 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1317 const struct sys_reg_desc *r)
1322 return write_to_read_only(vcpu, p, r);
1324 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1);
1325 p->regval = get_ccsidr(csselr);
1328 * Guests should not be doing cache operations by set/way at all, and
1329 * for this reason, we trap them and attempt to infer the intent, so
1330 * that we can flush the entire guest's address space at the appropriate
1332 * To prevent this trapping from causing performance problems, let's
1333 * expose the geometry of all data and unified caches (which are
1334 * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way.
1335 * [If guests should attempt to infer aliasing properties from the
1336 * geometry (which is not permitted by the architecture), they would
1337 * only do so for virtually indexed caches.]
1339 if (!(csselr & 1)) // data or unified cache
1340 p->regval &= ~GENMASK(27, 3);
1344 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu,
1345 const struct sys_reg_desc *rd)
1347 if (kvm_has_mte(vcpu->kvm))
1353 #define MTE_REG(name) { \
1354 SYS_DESC(SYS_##name), \
1355 .access = undef_access, \
1356 .reset = reset_unknown, \
1358 .visibility = mte_visibility, \
1361 /* sys_reg_desc initialiser for known cpufeature ID registers */
1362 #define ID_SANITISED(name) { \
1363 SYS_DESC(SYS_##name), \
1364 .access = access_id_reg, \
1365 .get_user = get_id_reg, \
1366 .set_user = set_id_reg, \
1367 .visibility = id_visibility, \
1371 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
1372 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1373 * (1 <= crm < 8, 0 <= Op2 < 8).
1375 #define ID_UNALLOCATED(crm, op2) { \
1376 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
1377 .access = access_raz_id_reg, \
1378 .get_user = get_raz_reg, \
1379 .set_user = set_raz_id_reg, \
1383 * sys_reg_desc initialiser for known ID registers that we hide from guests.
1384 * For now, these are exposed just like unallocated ID regs: they appear
1385 * RAZ for the guest.
1387 #define ID_HIDDEN(name) { \
1388 SYS_DESC(SYS_##name), \
1389 .access = access_raz_id_reg, \
1390 .get_user = get_raz_reg, \
1391 .set_user = set_raz_id_reg, \
1395 * Architected system registers.
1396 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
1398 * Debug handling: We do trap most, if not all debug related system
1399 * registers. The implementation is good enough to ensure that a guest
1400 * can use these with minimal performance degradation. The drawback is
1401 * that we don't implement any of the external debug architecture.
1402 * This should be revisited if we ever encounter a more demanding
1405 static const struct sys_reg_desc sys_reg_descs[] = {
1406 { SYS_DESC(SYS_DC_ISW), access_dcsw },
1407 { SYS_DESC(SYS_DC_CSW), access_dcsw },
1408 { SYS_DESC(SYS_DC_CISW), access_dcsw },
1410 DBG_BCR_BVR_WCR_WVR_EL1(0),
1411 DBG_BCR_BVR_WCR_WVR_EL1(1),
1412 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
1413 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
1414 DBG_BCR_BVR_WCR_WVR_EL1(2),
1415 DBG_BCR_BVR_WCR_WVR_EL1(3),
1416 DBG_BCR_BVR_WCR_WVR_EL1(4),
1417 DBG_BCR_BVR_WCR_WVR_EL1(5),
1418 DBG_BCR_BVR_WCR_WVR_EL1(6),
1419 DBG_BCR_BVR_WCR_WVR_EL1(7),
1420 DBG_BCR_BVR_WCR_WVR_EL1(8),
1421 DBG_BCR_BVR_WCR_WVR_EL1(9),
1422 DBG_BCR_BVR_WCR_WVR_EL1(10),
1423 DBG_BCR_BVR_WCR_WVR_EL1(11),
1424 DBG_BCR_BVR_WCR_WVR_EL1(12),
1425 DBG_BCR_BVR_WCR_WVR_EL1(13),
1426 DBG_BCR_BVR_WCR_WVR_EL1(14),
1427 DBG_BCR_BVR_WCR_WVR_EL1(15),
1429 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
1430 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 },
1431 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1,
1432 SYS_OSLSR_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, },
1433 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
1434 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
1435 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
1436 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
1437 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
1439 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
1440 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
1441 // DBGDTR[TR]X_EL0 share the same encoding
1442 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
1444 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
1446 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
1449 * ID regs: all ID_SANITISED() entries here must have corresponding
1450 * entries in arm64_ftr_regs[].
1453 /* AArch64 mappings of the AArch32 ID registers */
1455 ID_SANITISED(ID_PFR0_EL1),
1456 ID_SANITISED(ID_PFR1_EL1),
1457 ID_SANITISED(ID_DFR0_EL1),
1458 ID_HIDDEN(ID_AFR0_EL1),
1459 ID_SANITISED(ID_MMFR0_EL1),
1460 ID_SANITISED(ID_MMFR1_EL1),
1461 ID_SANITISED(ID_MMFR2_EL1),
1462 ID_SANITISED(ID_MMFR3_EL1),
1465 ID_SANITISED(ID_ISAR0_EL1),
1466 ID_SANITISED(ID_ISAR1_EL1),
1467 ID_SANITISED(ID_ISAR2_EL1),
1468 ID_SANITISED(ID_ISAR3_EL1),
1469 ID_SANITISED(ID_ISAR4_EL1),
1470 ID_SANITISED(ID_ISAR5_EL1),
1471 ID_SANITISED(ID_MMFR4_EL1),
1472 ID_SANITISED(ID_ISAR6_EL1),
1475 ID_SANITISED(MVFR0_EL1),
1476 ID_SANITISED(MVFR1_EL1),
1477 ID_SANITISED(MVFR2_EL1),
1478 ID_UNALLOCATED(3,3),
1479 ID_SANITISED(ID_PFR2_EL1),
1480 ID_HIDDEN(ID_DFR1_EL1),
1481 ID_SANITISED(ID_MMFR5_EL1),
1482 ID_UNALLOCATED(3,7),
1484 /* AArch64 ID registers */
1486 { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg,
1487 .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, },
1488 ID_SANITISED(ID_AA64PFR1_EL1),
1489 ID_UNALLOCATED(4,2),
1490 ID_UNALLOCATED(4,3),
1491 ID_SANITISED(ID_AA64ZFR0_EL1),
1492 ID_HIDDEN(ID_AA64SMFR0_EL1),
1493 ID_UNALLOCATED(4,6),
1494 ID_UNALLOCATED(4,7),
1497 ID_SANITISED(ID_AA64DFR0_EL1),
1498 ID_SANITISED(ID_AA64DFR1_EL1),
1499 ID_UNALLOCATED(5,2),
1500 ID_UNALLOCATED(5,3),
1501 ID_HIDDEN(ID_AA64AFR0_EL1),
1502 ID_HIDDEN(ID_AA64AFR1_EL1),
1503 ID_UNALLOCATED(5,6),
1504 ID_UNALLOCATED(5,7),
1507 ID_SANITISED(ID_AA64ISAR0_EL1),
1508 ID_SANITISED(ID_AA64ISAR1_EL1),
1509 ID_SANITISED(ID_AA64ISAR2_EL1),
1510 ID_UNALLOCATED(6,3),
1511 ID_UNALLOCATED(6,4),
1512 ID_UNALLOCATED(6,5),
1513 ID_UNALLOCATED(6,6),
1514 ID_UNALLOCATED(6,7),
1517 ID_SANITISED(ID_AA64MMFR0_EL1),
1518 ID_SANITISED(ID_AA64MMFR1_EL1),
1519 ID_SANITISED(ID_AA64MMFR2_EL1),
1520 ID_UNALLOCATED(7,3),
1521 ID_UNALLOCATED(7,4),
1522 ID_UNALLOCATED(7,5),
1523 ID_UNALLOCATED(7,6),
1524 ID_UNALLOCATED(7,7),
1526 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
1527 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 },
1528 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
1533 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
1534 { SYS_DESC(SYS_TRFCR_EL1), undef_access },
1535 { SYS_DESC(SYS_SMPRI_EL1), undef_access },
1536 { SYS_DESC(SYS_SMCR_EL1), undef_access },
1537 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
1538 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
1539 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
1547 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
1548 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
1549 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
1551 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi },
1552 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi },
1553 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi },
1554 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi },
1555 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi },
1556 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi },
1557 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
1558 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
1561 MTE_REG(TFSRE0_EL1),
1563 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
1564 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
1566 { SYS_DESC(SYS_PMSCR_EL1), undef_access },
1567 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access },
1568 { SYS_DESC(SYS_PMSICR_EL1), undef_access },
1569 { SYS_DESC(SYS_PMSIRR_EL1), undef_access },
1570 { SYS_DESC(SYS_PMSFCR_EL1), undef_access },
1571 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access },
1572 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access },
1573 { SYS_DESC(SYS_PMSIDR_EL1), undef_access },
1574 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access },
1575 { SYS_DESC(SYS_PMBPTR_EL1), undef_access },
1576 { SYS_DESC(SYS_PMBSR_EL1), undef_access },
1577 /* PMBIDR_EL1 is not trapped */
1579 { PMU_SYS_REG(SYS_PMINTENSET_EL1),
1580 .access = access_pminten, .reg = PMINTENSET_EL1 },
1581 { PMU_SYS_REG(SYS_PMINTENCLR_EL1),
1582 .access = access_pminten, .reg = PMINTENSET_EL1 },
1583 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi },
1585 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
1586 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
1588 { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
1589 { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
1590 { SYS_DESC(SYS_LORN_EL1), trap_loregion },
1591 { SYS_DESC(SYS_LORC_EL1), trap_loregion },
1592 { SYS_DESC(SYS_LORID_EL1), trap_loregion },
1594 { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
1595 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
1597 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
1598 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
1599 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only },
1600 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },
1601 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only },
1602 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
1603 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
1604 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
1605 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only },
1606 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only },
1607 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only },
1608 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
1610 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
1611 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
1613 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access },
1615 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
1617 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
1618 { SYS_DESC(SYS_CLIDR_EL1), access_clidr },
1619 { SYS_DESC(SYS_SMIDR_EL1), undef_access },
1620 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
1621 { SYS_DESC(SYS_CTR_EL0), access_ctr },
1622 { SYS_DESC(SYS_SVCR), undef_access },
1624 { PMU_SYS_REG(SYS_PMCR_EL0), .access = access_pmcr,
1625 .reset = reset_pmcr, .reg = PMCR_EL0 },
1626 { PMU_SYS_REG(SYS_PMCNTENSET_EL0),
1627 .access = access_pmcnten, .reg = PMCNTENSET_EL0 },
1628 { PMU_SYS_REG(SYS_PMCNTENCLR_EL0),
1629 .access = access_pmcnten, .reg = PMCNTENSET_EL0 },
1630 { PMU_SYS_REG(SYS_PMOVSCLR_EL0),
1631 .access = access_pmovs, .reg = PMOVSSET_EL0 },
1633 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was
1634 * previously (and pointlessly) advertised in the past...
1636 { PMU_SYS_REG(SYS_PMSWINC_EL0),
1637 .get_user = get_raz_reg, .set_user = set_wi_reg,
1638 .access = access_pmswinc, .reset = NULL },
1639 { PMU_SYS_REG(SYS_PMSELR_EL0),
1640 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 },
1641 { PMU_SYS_REG(SYS_PMCEID0_EL0),
1642 .access = access_pmceid, .reset = NULL },
1643 { PMU_SYS_REG(SYS_PMCEID1_EL0),
1644 .access = access_pmceid, .reset = NULL },
1645 { PMU_SYS_REG(SYS_PMCCNTR_EL0),
1646 .access = access_pmu_evcntr, .reset = reset_unknown, .reg = PMCCNTR_EL0 },
1647 { PMU_SYS_REG(SYS_PMXEVTYPER_EL0),
1648 .access = access_pmu_evtyper, .reset = NULL },
1649 { PMU_SYS_REG(SYS_PMXEVCNTR_EL0),
1650 .access = access_pmu_evcntr, .reset = NULL },
1652 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
1653 * in 32bit mode. Here we choose to reset it as zero for consistency.
1655 { PMU_SYS_REG(SYS_PMUSERENR_EL0), .access = access_pmuserenr,
1656 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 },
1657 { PMU_SYS_REG(SYS_PMOVSSET_EL0),
1658 .access = access_pmovs, .reg = PMOVSSET_EL0 },
1660 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
1661 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
1662 { SYS_DESC(SYS_TPIDR2_EL0), undef_access },
1664 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access },
1666 { SYS_DESC(SYS_AMCR_EL0), undef_access },
1667 { SYS_DESC(SYS_AMCFGR_EL0), undef_access },
1668 { SYS_DESC(SYS_AMCGCR_EL0), undef_access },
1669 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access },
1670 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access },
1671 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access },
1672 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access },
1673 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access },
1674 AMU_AMEVCNTR0_EL0(0),
1675 AMU_AMEVCNTR0_EL0(1),
1676 AMU_AMEVCNTR0_EL0(2),
1677 AMU_AMEVCNTR0_EL0(3),
1678 AMU_AMEVCNTR0_EL0(4),
1679 AMU_AMEVCNTR0_EL0(5),
1680 AMU_AMEVCNTR0_EL0(6),
1681 AMU_AMEVCNTR0_EL0(7),
1682 AMU_AMEVCNTR0_EL0(8),
1683 AMU_AMEVCNTR0_EL0(9),
1684 AMU_AMEVCNTR0_EL0(10),
1685 AMU_AMEVCNTR0_EL0(11),
1686 AMU_AMEVCNTR0_EL0(12),
1687 AMU_AMEVCNTR0_EL0(13),
1688 AMU_AMEVCNTR0_EL0(14),
1689 AMU_AMEVCNTR0_EL0(15),
1690 AMU_AMEVTYPER0_EL0(0),
1691 AMU_AMEVTYPER0_EL0(1),
1692 AMU_AMEVTYPER0_EL0(2),
1693 AMU_AMEVTYPER0_EL0(3),
1694 AMU_AMEVTYPER0_EL0(4),
1695 AMU_AMEVTYPER0_EL0(5),
1696 AMU_AMEVTYPER0_EL0(6),
1697 AMU_AMEVTYPER0_EL0(7),
1698 AMU_AMEVTYPER0_EL0(8),
1699 AMU_AMEVTYPER0_EL0(9),
1700 AMU_AMEVTYPER0_EL0(10),
1701 AMU_AMEVTYPER0_EL0(11),
1702 AMU_AMEVTYPER0_EL0(12),
1703 AMU_AMEVTYPER0_EL0(13),
1704 AMU_AMEVTYPER0_EL0(14),
1705 AMU_AMEVTYPER0_EL0(15),
1706 AMU_AMEVCNTR1_EL0(0),
1707 AMU_AMEVCNTR1_EL0(1),
1708 AMU_AMEVCNTR1_EL0(2),
1709 AMU_AMEVCNTR1_EL0(3),
1710 AMU_AMEVCNTR1_EL0(4),
1711 AMU_AMEVCNTR1_EL0(5),
1712 AMU_AMEVCNTR1_EL0(6),
1713 AMU_AMEVCNTR1_EL0(7),
1714 AMU_AMEVCNTR1_EL0(8),
1715 AMU_AMEVCNTR1_EL0(9),
1716 AMU_AMEVCNTR1_EL0(10),
1717 AMU_AMEVCNTR1_EL0(11),
1718 AMU_AMEVCNTR1_EL0(12),
1719 AMU_AMEVCNTR1_EL0(13),
1720 AMU_AMEVCNTR1_EL0(14),
1721 AMU_AMEVCNTR1_EL0(15),
1722 AMU_AMEVTYPER1_EL0(0),
1723 AMU_AMEVTYPER1_EL0(1),
1724 AMU_AMEVTYPER1_EL0(2),
1725 AMU_AMEVTYPER1_EL0(3),
1726 AMU_AMEVTYPER1_EL0(4),
1727 AMU_AMEVTYPER1_EL0(5),
1728 AMU_AMEVTYPER1_EL0(6),
1729 AMU_AMEVTYPER1_EL0(7),
1730 AMU_AMEVTYPER1_EL0(8),
1731 AMU_AMEVTYPER1_EL0(9),
1732 AMU_AMEVTYPER1_EL0(10),
1733 AMU_AMEVTYPER1_EL0(11),
1734 AMU_AMEVTYPER1_EL0(12),
1735 AMU_AMEVTYPER1_EL0(13),
1736 AMU_AMEVTYPER1_EL0(14),
1737 AMU_AMEVTYPER1_EL0(15),
1739 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },
1740 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer },
1741 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer },
1744 PMU_PMEVCNTR_EL0(0),
1745 PMU_PMEVCNTR_EL0(1),
1746 PMU_PMEVCNTR_EL0(2),
1747 PMU_PMEVCNTR_EL0(3),
1748 PMU_PMEVCNTR_EL0(4),
1749 PMU_PMEVCNTR_EL0(5),
1750 PMU_PMEVCNTR_EL0(6),
1751 PMU_PMEVCNTR_EL0(7),
1752 PMU_PMEVCNTR_EL0(8),
1753 PMU_PMEVCNTR_EL0(9),
1754 PMU_PMEVCNTR_EL0(10),
1755 PMU_PMEVCNTR_EL0(11),
1756 PMU_PMEVCNTR_EL0(12),
1757 PMU_PMEVCNTR_EL0(13),
1758 PMU_PMEVCNTR_EL0(14),
1759 PMU_PMEVCNTR_EL0(15),
1760 PMU_PMEVCNTR_EL0(16),
1761 PMU_PMEVCNTR_EL0(17),
1762 PMU_PMEVCNTR_EL0(18),
1763 PMU_PMEVCNTR_EL0(19),
1764 PMU_PMEVCNTR_EL0(20),
1765 PMU_PMEVCNTR_EL0(21),
1766 PMU_PMEVCNTR_EL0(22),
1767 PMU_PMEVCNTR_EL0(23),
1768 PMU_PMEVCNTR_EL0(24),
1769 PMU_PMEVCNTR_EL0(25),
1770 PMU_PMEVCNTR_EL0(26),
1771 PMU_PMEVCNTR_EL0(27),
1772 PMU_PMEVCNTR_EL0(28),
1773 PMU_PMEVCNTR_EL0(29),
1774 PMU_PMEVCNTR_EL0(30),
1775 /* PMEVTYPERn_EL0 */
1776 PMU_PMEVTYPER_EL0(0),
1777 PMU_PMEVTYPER_EL0(1),
1778 PMU_PMEVTYPER_EL0(2),
1779 PMU_PMEVTYPER_EL0(3),
1780 PMU_PMEVTYPER_EL0(4),
1781 PMU_PMEVTYPER_EL0(5),
1782 PMU_PMEVTYPER_EL0(6),
1783 PMU_PMEVTYPER_EL0(7),
1784 PMU_PMEVTYPER_EL0(8),
1785 PMU_PMEVTYPER_EL0(9),
1786 PMU_PMEVTYPER_EL0(10),
1787 PMU_PMEVTYPER_EL0(11),
1788 PMU_PMEVTYPER_EL0(12),
1789 PMU_PMEVTYPER_EL0(13),
1790 PMU_PMEVTYPER_EL0(14),
1791 PMU_PMEVTYPER_EL0(15),
1792 PMU_PMEVTYPER_EL0(16),
1793 PMU_PMEVTYPER_EL0(17),
1794 PMU_PMEVTYPER_EL0(18),
1795 PMU_PMEVTYPER_EL0(19),
1796 PMU_PMEVTYPER_EL0(20),
1797 PMU_PMEVTYPER_EL0(21),
1798 PMU_PMEVTYPER_EL0(22),
1799 PMU_PMEVTYPER_EL0(23),
1800 PMU_PMEVTYPER_EL0(24),
1801 PMU_PMEVTYPER_EL0(25),
1802 PMU_PMEVTYPER_EL0(26),
1803 PMU_PMEVTYPER_EL0(27),
1804 PMU_PMEVTYPER_EL0(28),
1805 PMU_PMEVTYPER_EL0(29),
1806 PMU_PMEVTYPER_EL0(30),
1808 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
1809 * in 32bit mode. Here we choose to reset it as zero for consistency.
1811 { PMU_SYS_REG(SYS_PMCCFILTR_EL0), .access = access_pmu_evtyper,
1812 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 },
1814 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
1815 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
1816 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
1819 static bool trap_dbgdidr(struct kvm_vcpu *vcpu,
1820 struct sys_reg_params *p,
1821 const struct sys_reg_desc *r)
1824 return ignore_write(vcpu, p);
1826 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
1827 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1828 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
1830 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1831 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1832 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1833 | (6 << 16) | (1 << 15) | (el3 << 14) | (el3 << 12));
1839 * AArch32 debug register mappings
1841 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1842 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1844 * None of the other registers share their location, so treat them as
1845 * if they were 64bit.
1847 #define DBG_BCR_BVR_WCR_WVR(n) \
1849 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1851 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
1853 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
1855 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1857 #define DBGBXVR(n) \
1858 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n }
1861 * Trapped cp14 registers. We generally ignore most of the external
1862 * debug, on the principle that they don't really make sense to a
1863 * guest. Revisit this one day, would this principle change.
1865 static const struct sys_reg_desc cp14_regs[] = {
1867 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr },
1869 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1871 DBG_BCR_BVR_WCR_WVR(0),
1873 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1874 DBG_BCR_BVR_WCR_WVR(1),
1876 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 },
1878 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 },
1879 DBG_BCR_BVR_WCR_WVR(2),
1880 /* DBGDTR[RT]Xint */
1881 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1882 /* DBGDTR[RT]Xext */
1883 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1884 DBG_BCR_BVR_WCR_WVR(3),
1885 DBG_BCR_BVR_WCR_WVR(4),
1886 DBG_BCR_BVR_WCR_WVR(5),
1888 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1890 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1891 DBG_BCR_BVR_WCR_WVR(6),
1893 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 },
1894 DBG_BCR_BVR_WCR_WVR(7),
1895 DBG_BCR_BVR_WCR_WVR(8),
1896 DBG_BCR_BVR_WCR_WVR(9),
1897 DBG_BCR_BVR_WCR_WVR(10),
1898 DBG_BCR_BVR_WCR_WVR(11),
1899 DBG_BCR_BVR_WCR_WVR(12),
1900 DBG_BCR_BVR_WCR_WVR(13),
1901 DBG_BCR_BVR_WCR_WVR(14),
1902 DBG_BCR_BVR_WCR_WVR(15),
1904 /* DBGDRAR (32bit) */
1905 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1909 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 },
1912 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 },
1916 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1919 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1932 /* DBGDSAR (32bit) */
1933 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1936 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1938 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1940 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1942 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1944 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1946 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
1949 /* Trapped cp14 64bit registers */
1950 static const struct sys_reg_desc cp14_64_regs[] = {
1951 /* DBGDRAR (64bit) */
1952 { Op1( 0), CRm( 1), .access = trap_raz_wi },
1954 /* DBGDSAR (64bit) */
1955 { Op1( 0), CRm( 2), .access = trap_raz_wi },
1958 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \
1960 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \
1961 .visibility = pmu_visibility
1963 /* Macro to expand the PMEVCNTRn register */
1964 #define PMU_PMEVCNTR(n) \
1965 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \
1966 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \
1967 .access = access_pmu_evcntr }
1969 /* Macro to expand the PMEVTYPERn register */
1970 #define PMU_PMEVTYPER(n) \
1971 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \
1972 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \
1973 .access = access_pmu_evtyper }
1975 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1976 * depending on the way they are accessed (as a 32bit or a 64bit
1979 static const struct sys_reg_desc cp15_regs[] = {
1980 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
1981 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 },
1983 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 },
1985 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 },
1986 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
1987 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 },
1989 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 },
1991 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 },
1992 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 },
1994 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 },
1995 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 },
1997 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 },
1999 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 },
2001 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 },
2003 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 },
2006 * DC{C,I,CI}SW operations:
2008 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
2009 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
2010 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
2013 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr },
2014 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten },
2015 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten },
2016 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs },
2017 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc },
2018 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr },
2019 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid },
2020 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid },
2021 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr },
2022 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper },
2023 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr },
2024 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr },
2025 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten },
2026 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten },
2027 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs },
2028 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid },
2029 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid },
2031 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi },
2034 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 },
2036 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 },
2038 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 },
2040 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 },
2043 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
2045 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 },
2048 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer },
2049 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer },
2116 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper },
2118 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
2119 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
2120 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 },
2123 static const struct sys_reg_desc cp15_64_regs[] = {
2124 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
2125 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr },
2126 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
2127 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 },
2128 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
2129 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
2130 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer },
2133 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n,
2138 for (i = 0; i < n; i++) {
2139 if (!is_32 && table[i].reg && !table[i].reset) {
2140 kvm_err("sys_reg table %pS entry %d lacks reset\n", &table[i], i);
2144 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2145 kvm_err("sys_reg table %pS entry %d out of order\n", &table[i - 1], i - 1);
2153 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu)
2155 kvm_inject_undefined(vcpu);
2159 static void perform_access(struct kvm_vcpu *vcpu,
2160 struct sys_reg_params *params,
2161 const struct sys_reg_desc *r)
2163 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r);
2165 /* Check for regs disabled by runtime config */
2166 if (sysreg_hidden(vcpu, r)) {
2167 kvm_inject_undefined(vcpu);
2172 * Not having an accessor means that we have configured a trap
2173 * that we don't know how to handle. This certainly qualifies
2174 * as a gross bug that should be fixed right away.
2178 /* Skip instruction if instructed so */
2179 if (likely(r->access(vcpu, params, r)))
2184 * emulate_cp -- tries to match a sys_reg access in a handling table, and
2185 * call the corresponding trap handler.
2187 * @params: pointer to the descriptor of the access
2188 * @table: array of trap descriptors
2189 * @num: size of the trap descriptor array
2191 * Return true if the access has been handled, false if not.
2193 static bool emulate_cp(struct kvm_vcpu *vcpu,
2194 struct sys_reg_params *params,
2195 const struct sys_reg_desc *table,
2198 const struct sys_reg_desc *r;
2201 return false; /* Not handled */
2203 r = find_reg(params, table, num);
2206 perform_access(vcpu, params, r);
2214 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
2215 struct sys_reg_params *params)
2217 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
2221 case ESR_ELx_EC_CP15_32:
2222 case ESR_ELx_EC_CP15_64:
2225 case ESR_ELx_EC_CP14_MR:
2226 case ESR_ELx_EC_CP14_64:
2233 print_sys_reg_msg(params,
2234 "Unsupported guest CP%d access at: %08lx [%08lx]\n",
2235 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
2236 kvm_inject_undefined(vcpu);
2240 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
2241 * @vcpu: The VCPU pointer
2242 * @run: The kvm_run struct
2244 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
2245 const struct sys_reg_desc *global,
2248 struct sys_reg_params params;
2249 u64 esr = kvm_vcpu_get_esr(vcpu);
2250 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2251 int Rt2 = (esr >> 10) & 0x1f;
2253 params.CRm = (esr >> 1) & 0xf;
2254 params.is_write = ((esr & 1) == 0);
2257 params.Op1 = (esr >> 16) & 0xf;
2262 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
2263 * backends between AArch32 and AArch64, we get away with it.
2265 if (params.is_write) {
2266 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
2267 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
2271 * If the table contains a handler, handle the
2272 * potential register operation in the case of a read and return
2275 if (emulate_cp(vcpu, ¶ms, global, nr_global)) {
2276 /* Split up the value between registers for the read side */
2277 if (!params.is_write) {
2278 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
2279 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
2285 unhandled_cp_access(vcpu, ¶ms);
2289 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params);
2292 * The CP10 ID registers are architecturally mapped to AArch64 feature
2293 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses
2296 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params)
2298 u8 reg_id = (esr >> 10) & 0xf;
2301 params->is_write = ((esr & 1) == 0);
2307 /* CP10 ID registers are read-only */
2308 valid = !params->is_write;
2330 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n",
2331 params->is_write ? "write" : "read", reg_id);
2336 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and
2337 * VFP Register' from AArch32.
2338 * @vcpu: The vCPU pointer
2340 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers.
2341 * Work out the correct AArch64 system register encoding and reroute to the
2342 * AArch64 system register emulation.
2344 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu)
2346 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2347 u64 esr = kvm_vcpu_get_esr(vcpu);
2348 struct sys_reg_params params;
2350 /* UNDEF on any unhandled register access */
2351 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) {
2352 kvm_inject_undefined(vcpu);
2356 if (emulate_sys_reg(vcpu, ¶ms))
2357 vcpu_set_reg(vcpu, Rt, params.regval);
2363 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where
2364 * CRn=0, which corresponds to the AArch32 feature
2366 * @vcpu: the vCPU pointer
2367 * @params: the system register access parameters.
2369 * Our cp15 system register tables do not enumerate the AArch32 feature
2370 * registers. Conveniently, our AArch64 table does, and the AArch32 system
2371 * register encoding can be trivially remapped into the AArch64 for the feature
2372 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same.
2374 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit
2375 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this
2376 * range are either UNKNOWN or RES0. Rerouting remains architectural as we
2377 * treat undefined registers in this range as RAZ.
2379 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu,
2380 struct sys_reg_params *params)
2382 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2384 /* Treat impossible writes to RO registers as UNDEFINED */
2385 if (params->is_write) {
2386 unhandled_cp_access(vcpu, params);
2393 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32.
2394 * Avoid conflicting with future expansion of AArch64 feature registers
2395 * and simply treat them as RAZ here.
2397 if (params->CRm > 3)
2399 else if (!emulate_sys_reg(vcpu, params))
2402 vcpu_set_reg(vcpu, Rt, params->regval);
2407 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
2408 * @vcpu: The VCPU pointer
2409 * @run: The kvm_run struct
2411 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
2412 struct sys_reg_params *params,
2413 const struct sys_reg_desc *global,
2416 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2418 params->regval = vcpu_get_reg(vcpu, Rt);
2420 if (emulate_cp(vcpu, params, global, nr_global)) {
2421 if (!params->is_write)
2422 vcpu_set_reg(vcpu, Rt, params->regval);
2426 unhandled_cp_access(vcpu, params);
2430 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu)
2432 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs));
2435 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu)
2437 struct sys_reg_params params;
2439 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu));
2442 * Certain AArch32 ID registers are handled by rerouting to the AArch64
2443 * system register table. Registers in the ID range where CRm=0 are
2444 * excluded from this scheme as they do not trivially map into AArch64
2445 * system register encodings.
2447 if (params.Op1 == 0 && params.CRn == 0 && params.CRm)
2448 return kvm_emulate_cp15_id_reg(vcpu, ¶ms);
2450 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs));
2453 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu)
2455 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs));
2458 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu)
2460 struct sys_reg_params params;
2462 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu));
2464 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs));
2467 static bool is_imp_def_sys_reg(struct sys_reg_params *params)
2469 // See ARM DDI 0487E.a, section D12.3.2
2470 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011;
2474 * emulate_sys_reg - Emulate a guest access to an AArch64 system register
2475 * @vcpu: The VCPU pointer
2476 * @params: Decoded system register parameters
2478 * Return: true if the system register access was successful, false otherwise.
2480 static bool emulate_sys_reg(struct kvm_vcpu *vcpu,
2481 struct sys_reg_params *params)
2483 const struct sys_reg_desc *r;
2485 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2488 perform_access(vcpu, params, r);
2492 if (is_imp_def_sys_reg(params)) {
2493 kvm_inject_undefined(vcpu);
2495 print_sys_reg_msg(params,
2496 "Unsupported guest sys_reg access at: %lx [%08lx]\n",
2497 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
2498 kvm_inject_undefined(vcpu);
2504 * kvm_reset_sys_regs - sets system registers to reset value
2505 * @vcpu: The VCPU pointer
2507 * This function finds the right table above and sets the registers on the
2508 * virtual CPU struct to their architecturally defined reset values.
2510 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
2514 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++)
2515 if (sys_reg_descs[i].reset)
2516 sys_reg_descs[i].reset(vcpu, &sys_reg_descs[i]);
2520 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
2521 * @vcpu: The VCPU pointer
2523 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu)
2525 struct sys_reg_params params;
2526 unsigned long esr = kvm_vcpu_get_esr(vcpu);
2527 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2529 trace_kvm_handle_sys_reg(esr);
2531 params = esr_sys64_to_params(esr);
2532 params.regval = vcpu_get_reg(vcpu, Rt);
2534 if (!emulate_sys_reg(vcpu, ¶ms))
2537 if (!params.is_write)
2538 vcpu_set_reg(vcpu, Rt, params.regval);
2542 /******************************************************************************
2544 *****************************************************************************/
2546 static bool index_to_params(u64 id, struct sys_reg_params *params)
2548 switch (id & KVM_REG_SIZE_MASK) {
2549 case KVM_REG_SIZE_U64:
2550 /* Any unused index bits means it's not valid. */
2551 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
2552 | KVM_REG_ARM_COPROC_MASK
2553 | KVM_REG_ARM64_SYSREG_OP0_MASK
2554 | KVM_REG_ARM64_SYSREG_OP1_MASK
2555 | KVM_REG_ARM64_SYSREG_CRN_MASK
2556 | KVM_REG_ARM64_SYSREG_CRM_MASK
2557 | KVM_REG_ARM64_SYSREG_OP2_MASK))
2559 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
2560 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
2561 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
2562 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
2563 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
2564 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
2565 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
2566 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
2567 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
2568 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
2575 const struct sys_reg_desc *get_reg_by_id(u64 id,
2576 const struct sys_reg_desc table[],
2579 struct sys_reg_params params;
2581 if (!index_to_params(id, ¶ms))
2584 return find_reg(¶ms, table, num);
2587 /* Decode an index value, and find the sys_reg_desc entry. */
2588 static const struct sys_reg_desc *
2589 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id,
2590 const struct sys_reg_desc table[], unsigned int num)
2593 const struct sys_reg_desc *r;
2595 /* We only do sys_reg for now. */
2596 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
2599 r = get_reg_by_id(id, table, num);
2601 /* Not saved in the sys_reg array and not otherwise accessible? */
2602 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r)))
2609 * These are the invariant sys_reg registers: we let the guest see the
2610 * host versions of these, so they're part of the guest state.
2612 * A future CPU may provide a mechanism to present different values to
2613 * the guest, or a future kvm may trap them.
2616 #define FUNCTION_INVARIANT(reg) \
2617 static void get_##reg(struct kvm_vcpu *v, \
2618 const struct sys_reg_desc *r) \
2620 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
2623 FUNCTION_INVARIANT(midr_el1)
2624 FUNCTION_INVARIANT(revidr_el1)
2625 FUNCTION_INVARIANT(clidr_el1)
2626 FUNCTION_INVARIANT(aidr_el1)
2628 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)
2630 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0);
2633 /* ->val is filled in by kvm_sys_reg_table_init() */
2634 static struct sys_reg_desc invariant_sys_regs[] = {
2635 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 },
2636 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 },
2637 { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 },
2638 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 },
2639 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 },
2642 static int get_invariant_sys_reg(u64 id, u64 __user *uaddr)
2644 const struct sys_reg_desc *r;
2646 r = get_reg_by_id(id, invariant_sys_regs,
2647 ARRAY_SIZE(invariant_sys_regs));
2651 return put_user(r->val, uaddr);
2654 static int set_invariant_sys_reg(u64 id, u64 __user *uaddr)
2656 const struct sys_reg_desc *r;
2659 r = get_reg_by_id(id, invariant_sys_regs,
2660 ARRAY_SIZE(invariant_sys_regs));
2664 if (get_user(val, uaddr))
2667 /* This is what we mean by invariant: you can't change it. */
2674 static bool is_valid_cache(u32 val)
2678 if (val >= CSSELR_MAX)
2681 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
2683 ctype = (cache_levels >> (level * 3)) & 7;
2686 case 0: /* No cache */
2688 case 1: /* Instruction cache only */
2690 case 2: /* Data cache only */
2691 case 4: /* Unified cache */
2693 case 3: /* Separate instruction and data caches */
2695 default: /* Reserved: we can't know instruction or data. */
2700 static int demux_c15_get(u64 id, void __user *uaddr)
2703 u32 __user *uval = uaddr;
2705 /* Fail if we have unknown bits set. */
2706 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2707 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2710 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2711 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2712 if (KVM_REG_SIZE(id) != 4)
2714 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2715 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2716 if (!is_valid_cache(val))
2719 return put_user(get_ccsidr(val), uval);
2725 static int demux_c15_set(u64 id, void __user *uaddr)
2728 u32 __user *uval = uaddr;
2730 /* Fail if we have unknown bits set. */
2731 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2732 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2735 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2736 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2737 if (KVM_REG_SIZE(id) != 4)
2739 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2740 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2741 if (!is_valid_cache(val))
2744 if (get_user(newval, uval))
2747 /* This is also invariant: you can't change it. */
2748 if (newval != get_ccsidr(val))
2756 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
2757 const struct sys_reg_desc table[], unsigned int num)
2759 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr;
2760 const struct sys_reg_desc *r;
2764 r = id_to_sys_reg_desc(vcpu, reg->id, table, num);
2769 ret = (r->get_user)(vcpu, r, &val);
2771 val = __vcpu_sys_reg(vcpu, r->reg);
2776 ret = put_user(val, uaddr);
2781 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2783 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2786 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2787 return demux_c15_get(reg->id, uaddr);
2789 err = get_invariant_sys_reg(reg->id, uaddr);
2793 return kvm_sys_reg_get_user(vcpu, reg,
2794 sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2797 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
2798 const struct sys_reg_desc table[], unsigned int num)
2800 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr;
2801 const struct sys_reg_desc *r;
2805 if (get_user(val, uaddr))
2808 r = id_to_sys_reg_desc(vcpu, reg->id, table, num);
2813 ret = (r->set_user)(vcpu, r, val);
2815 __vcpu_sys_reg(vcpu, r->reg) = val;
2822 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2824 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2827 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2828 return demux_c15_set(reg->id, uaddr);
2830 err = set_invariant_sys_reg(reg->id, uaddr);
2834 return kvm_sys_reg_set_user(vcpu, reg,
2835 sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2838 static unsigned int num_demux_regs(void)
2840 unsigned int i, count = 0;
2842 for (i = 0; i < CSSELR_MAX; i++)
2843 if (is_valid_cache(i))
2849 static int write_demux_regids(u64 __user *uindices)
2851 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
2854 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2855 for (i = 0; i < CSSELR_MAX; i++) {
2856 if (!is_valid_cache(i))
2858 if (put_user(val | i, uindices))
2865 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2867 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2868 KVM_REG_ARM64_SYSREG |
2869 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2870 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2871 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2872 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2873 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2876 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2881 if (put_user(sys_reg_to_index(reg), *uind))
2888 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu,
2889 const struct sys_reg_desc *rd,
2891 unsigned int *total)
2894 * Ignore registers we trap but don't save,
2895 * and for which no custom user accessor is provided.
2897 if (!(rd->reg || rd->get_user))
2900 if (sysreg_hidden(vcpu, rd))
2903 if (!copy_reg_to_user(rd, uind))
2910 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
2911 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2913 const struct sys_reg_desc *i2, *end2;
2914 unsigned int total = 0;
2918 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2920 while (i2 != end2) {
2921 err = walk_one_sys_reg(vcpu, i2++, &uind, &total);
2928 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2930 return ARRAY_SIZE(invariant_sys_regs)
2932 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2935 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2940 /* Then give them all the invariant registers' indices. */
2941 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2942 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2947 err = walk_sys_regs(vcpu, uindices);
2952 return write_demux_regids(uindices);
2955 int kvm_sys_reg_table_init(void)
2959 struct sys_reg_desc clidr;
2961 /* Make sure tables are unique and in order. */
2962 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false);
2963 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true);
2964 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true);
2965 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true);
2966 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true);
2967 valid &= check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false);
2972 /* We abuse the reset function to overwrite the table itself. */
2973 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2974 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2977 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
2979 * If software reads the Cache Type fields from Ctype1
2980 * upwards, once it has seen a value of 0b000, no caches
2981 * exist at further-out levels of the hierarchy. So, for
2982 * example, if Ctype3 is the first Cache Type field with a
2983 * value of 0b000, the values of Ctype4 to Ctype7 must be
2986 get_clidr_el1(NULL, &clidr); /* Ugly... */
2987 cache_levels = clidr.val;
2988 for (i = 0; i < 7; i++)
2989 if (((cache_levels >> (i*3)) & 7) == 0)
2991 /* Clear all higher bits. */
2992 cache_levels &= (1 << (i*3))-1;