arch/arm64/kvm/sys_regs.c

   1 /*
   2  * Copyright (C) 2012,2013 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * Derived from arch/arm/kvm/coproc.c:
   6  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
   7  * Authors: Rusty Russell <rusty@rustcorp.com.au>
   8  *          Christoffer Dall <c.dall@virtualopensystems.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License, version 2, as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include <linux/bsearch.h>
  24 #include <linux/kvm_host.h>
  25 #include <linux/mm.h>
  26 #include <linux/uaccess.h>
  27
  28 #include <asm/cacheflush.h>
  29 #include <asm/cputype.h>
  30 #include <asm/debug-monitors.h>
  31 #include <asm/esr.h>
  32 #include <asm/kvm_arm.h>
  33 #include <asm/kvm_asm.h>
  34 #include <asm/kvm_coproc.h>
  35 #include <asm/kvm_emulate.h>
  36 #include <asm/kvm_host.h>
  37 #include <asm/kvm_mmu.h>
  38 #include <asm/perf_event.h>
  39
  40 #include <trace/events/kvm.h>
  41
  42 #include "sys_regs.h"
  43
  44 #include "trace.h"
  45
  46 /*
  47  * All of this file is extremly similar to the ARM coproc.c, but the
  48  * types are different. My gut feeling is that it should be pretty
  49  * easy to merge, but that would be an ABI breakage -- again. VFP
  50  * would also need to be abstracted.
  51  *
  52  * For AArch32, we only take care of what is being trapped. Anything
  53  * that has to do with init and userspace access has to go via the
  54  * 64bit interface.
  55  */
  56
  57 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
  58 static u32 cache_levels;
  59
  60 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
  61 #define CSSELR_MAX 12
  62
  63 /* Which cache CCSIDR represents depends on CSSELR value. */
  64 static u32 get_ccsidr(u32 csselr)
  65 {
  66         u32 ccsidr;
  67
  68         /* Make sure noone else changes CSSELR during this! */
  69         local_irq_disable();
  70         /* Put value into CSSELR */
  71         asm volatile("msr csselr_el1, %x0" : : "r" (csselr));
  72         isb();
  73         /* Read result out of CCSIDR */
  74         asm volatile("mrs %0, ccsidr_el1" : "=r" (ccsidr));
  75         local_irq_enable();
  76
  77         return ccsidr;
  78 }
  79
  80 /*
  81  * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
  82  */
  83 static bool access_dcsw(struct kvm_vcpu *vcpu,
  84                         struct sys_reg_params *p,
  85                         const struct sys_reg_desc *r)
  86 {
  87         if (!p->is_write)
  88                 return read_from_write_only(vcpu, p);
  89
  90         kvm_set_way_flush(vcpu);
  91         return true;
  92 }
  93
  94 /*
  95  * Generic accessor for VM registers. Only called as long as HCR_TVM
  96  * is set. If the guest enables the MMU, we stop trapping the VM
  97  * sys_regs and leave it in complete control of the caches.
  98  */
  99 static bool access_vm_reg(struct kvm_vcpu *vcpu,
 100                           struct sys_reg_params *p,
 101                           const struct sys_reg_desc *r)
 102 {
 103         bool was_enabled = vcpu_has_cache_enabled(vcpu);
 104
 105         BUG_ON(!p->is_write);
 106
 107         if (!p->is_aarch32) {
 108                 vcpu_sys_reg(vcpu, r->reg) = p->regval;
 109         } else {
 110                 if (!p->is_32bit)
 111                         vcpu_cp15_64_high(vcpu, r->reg) = upper_32_bits(p->regval);
 112                 vcpu_cp15_64_low(vcpu, r->reg) = lower_32_bits(p->regval);
 113         }
 114
 115         kvm_toggle_cache(vcpu, was_enabled);
 116         return true;
 117 }
 118
 119 /*
 120  * Trap handler for the GICv3 SGI generation system register.
 121  * Forward the request to the VGIC emulation.
 122  * The cp15_64 code makes sure this automatically works
 123  * for both AArch64 and AArch32 accesses.
 124  */
 125 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
 126                            struct sys_reg_params *p,
 127                            const struct sys_reg_desc *r)
 128 {
 129         if (!p->is_write)
 130                 return read_from_write_only(vcpu, p);
 131
 132         vgic_v3_dispatch_sgi(vcpu, p->regval);
 133
 134         return true;
 135 }
 136
 137 static bool access_gic_sre(struct kvm_vcpu *vcpu,
 138                            struct sys_reg_params *p,
 139                            const struct sys_reg_desc *r)
 140 {
 141         if (p->is_write)
 142                 return ignore_write(vcpu, p);
 143
 144         p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
 145         return true;
 146 }
 147
 148 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
 149                         struct sys_reg_params *p,
 150                         const struct sys_reg_desc *r)
 151 {
 152         if (p->is_write)
 153                 return ignore_write(vcpu, p);
 154         else
 155                 return read_zero(vcpu, p);
 156 }
 157
 158 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
 159                            struct sys_reg_params *p,
 160                            const struct sys_reg_desc *r)
 161 {
 162         if (p->is_write) {
 163                 return ignore_write(vcpu, p);
 164         } else {
 165                 p->regval = (1 << 3);
 166                 return true;
 167         }
 168 }
 169
 170 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
 171                                    struct sys_reg_params *p,
 172                                    const struct sys_reg_desc *r)
 173 {
 174         if (p->is_write) {
 175                 return ignore_write(vcpu, p);
 176         } else {
 177                 u32 val;
 178                 asm volatile("mrs %0, dbgauthstatus_el1" : "=r" (val));
 179                 p->regval = val;
 180                 return true;
 181         }
 182 }
 183
 184 /*
 185  * We want to avoid world-switching all the DBG registers all the
 186  * time:
 187  *
 188  * - If we've touched any debug register, it is likely that we're
 189  *   going to touch more of them. It then makes sense to disable the
 190  *   traps and start doing the save/restore dance
 191  * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
 192  *   then mandatory to save/restore the registers, as the guest
 193  *   depends on them.
 194  *
 195  * For this, we use a DIRTY bit, indicating the guest has modified the
 196  * debug registers, used as follow:
 197  *
 198  * On guest entry:
 199  * - If the dirty bit is set (because we're coming back from trapping),
 200  *   disable the traps, save host registers, restore guest registers.
 201  * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
 202  *   set the dirty bit, disable the traps, save host registers,
 203  *   restore guest registers.
 204  * - Otherwise, enable the traps
 205  *
 206  * On guest exit:
 207  * - If the dirty bit is set, save guest registers, restore host
 208  *   registers and clear the dirty bit. This ensure that the host can
 209  *   now use the debug registers.
 210  */
 211 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
 212                             struct sys_reg_params *p,
 213                             const struct sys_reg_desc *r)
 214 {
 215         if (p->is_write) {
 216                 vcpu_sys_reg(vcpu, r->reg) = p->regval;
 217                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
 218         } else {
 219                 p->regval = vcpu_sys_reg(vcpu, r->reg);
 220         }
 221
 222         trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
 223
 224         return true;
 225 }
 226
 227 /*
 228  * reg_to_dbg/dbg_to_reg
 229  *
 230  * A 32 bit write to a debug register leave top bits alone
 231  * A 32 bit read from a debug register only returns the bottom bits
 232  *
 233  * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
 234  * hyp.S code switches between host and guest values in future.
 235  */
 236 static void reg_to_dbg(struct kvm_vcpu *vcpu,
 237                        struct sys_reg_params *p,
 238                        u64 *dbg_reg)
 239 {
 240         u64 val = p->regval;
 241
 242         if (p->is_32bit) {
 243                 val &= 0xffffffffUL;
 244                 val |= ((*dbg_reg >> 32) << 32);
 245         }
 246
 247         *dbg_reg = val;
 248         vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
 249 }
 250
 251 static void dbg_to_reg(struct kvm_vcpu *vcpu,
 252                        struct sys_reg_params *p,
 253                        u64 *dbg_reg)
 254 {
 255         p->regval = *dbg_reg;
 256         if (p->is_32bit)
 257                 p->regval &= 0xffffffffUL;
 258 }
 259
 260 static bool trap_bvr(struct kvm_vcpu *vcpu,
 261                      struct sys_reg_params *p,
 262                      const struct sys_reg_desc *rd)
 263 {
 264         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
 265
 266         if (p->is_write)
 267                 reg_to_dbg(vcpu, p, dbg_reg);
 268         else
 269                 dbg_to_reg(vcpu, p, dbg_reg);
 270
 271         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
 272
 273         return true;
 274 }
 275
 276 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 277                 const struct kvm_one_reg *reg, void __user *uaddr)
 278 {
 279         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
 280
 281         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 282                 return -EFAULT;
 283         return 0;
 284 }
 285
 286 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 287         const struct kvm_one_reg *reg, void __user *uaddr)
 288 {
 289         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
 290
 291         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 292                 return -EFAULT;
 293         return 0;
 294 }
 295
 296 static void reset_bvr(struct kvm_vcpu *vcpu,
 297                       const struct sys_reg_desc *rd)
 298 {
 299         vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val;
 300 }
 301
 302 static bool trap_bcr(struct kvm_vcpu *vcpu,
 303                      struct sys_reg_params *p,
 304                      const struct sys_reg_desc *rd)
 305 {
 306         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
 307
 308         if (p->is_write)
 309                 reg_to_dbg(vcpu, p, dbg_reg);
 310         else
 311                 dbg_to_reg(vcpu, p, dbg_reg);
 312
 313         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
 314
 315         return true;
 316 }
 317
 318 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 319                 const struct kvm_one_reg *reg, void __user *uaddr)
 320 {
 321         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
 322
 323         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 324                 return -EFAULT;
 325
 326         return 0;
 327 }
 328
 329 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 330         const struct kvm_one_reg *reg, void __user *uaddr)
 331 {
 332         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
 333
 334         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 335                 return -EFAULT;
 336         return 0;
 337 }
 338
 339 static void reset_bcr(struct kvm_vcpu *vcpu,
 340                       const struct sys_reg_desc *rd)
 341 {
 342         vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val;
 343 }
 344
 345 static bool trap_wvr(struct kvm_vcpu *vcpu,
 346                      struct sys_reg_params *p,
 347                      const struct sys_reg_desc *rd)
 348 {
 349         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
 350
 351         if (p->is_write)
 352                 reg_to_dbg(vcpu, p, dbg_reg);
 353         else
 354                 dbg_to_reg(vcpu, p, dbg_reg);
 355
 356         trace_trap_reg(__func__, rd->reg, p->is_write,
 357                 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]);
 358
 359         return true;
 360 }
 361
 362 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 363                 const struct kvm_one_reg *reg, void __user *uaddr)
 364 {
 365         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
 366
 367         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 368                 return -EFAULT;
 369         return 0;
 370 }
 371
 372 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 373         const struct kvm_one_reg *reg, void __user *uaddr)
 374 {
 375         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
 376
 377         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 378                 return -EFAULT;
 379         return 0;
 380 }
 381
 382 static void reset_wvr(struct kvm_vcpu *vcpu,
 383                       const struct sys_reg_desc *rd)
 384 {
 385         vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val;
 386 }
 387
 388 static bool trap_wcr(struct kvm_vcpu *vcpu,
 389                      struct sys_reg_params *p,
 390                      const struct sys_reg_desc *rd)
 391 {
 392         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
 393
 394         if (p->is_write)
 395                 reg_to_dbg(vcpu, p, dbg_reg);
 396         else
 397                 dbg_to_reg(vcpu, p, dbg_reg);
 398
 399         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
 400
 401         return true;
 402 }
 403
 404 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 405                 const struct kvm_one_reg *reg, void __user *uaddr)
 406 {
 407         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
 408
 409         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 410                 return -EFAULT;
 411         return 0;
 412 }
 413
 414 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 415         const struct kvm_one_reg *reg, void __user *uaddr)
 416 {
 417         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
 418
 419         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 420                 return -EFAULT;
 421         return 0;
 422 }
 423
 424 static void reset_wcr(struct kvm_vcpu *vcpu,
 425                       const struct sys_reg_desc *rd)
 426 {
 427         vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val;
 428 }
 429
 430 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 431 {
 432         u64 amair;
 433
 434         asm volatile("mrs %0, amair_el1\n" : "=r" (amair));
 435         vcpu_sys_reg(vcpu, AMAIR_EL1) = amair;
 436 }
 437
 438 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 439 {
 440         u64 mpidr;
 441
 442         /*
 443          * Map the vcpu_id into the first three affinity level fields of
 444          * the MPIDR. We limit the number of VCPUs in level 0 due to a
 445          * limitation to 16 CPUs in that level in the ICC_SGIxR registers
 446          * of the GICv3 to be able to address each CPU directly when
 447          * sending IPIs.
 448          */
 449         mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
 450         mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
 451         mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
 452         vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr;
 453 }
 454
 455 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 456 {
 457         u64 pmcr, val;
 458
 459         asm volatile("mrs %0, pmcr_el0\n" : "=r" (pmcr));
 460         /* Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) is reset to UNKNOWN
 461          * except PMCR.E resetting to zero.
 462          */
 463         val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
 464                | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
 465         vcpu_sys_reg(vcpu, PMCR_EL0) = val;
 466 }
 467
 468 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
 469 {
 470         u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
 471
 472         return !((reg & ARMV8_PMU_USERENR_EN) || vcpu_mode_priv(vcpu));
 473 }
 474
 475 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
 476 {
 477         u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
 478
 479         return !((reg & (ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN))
 480                  || vcpu_mode_priv(vcpu));
 481 }
 482
 483 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
 484 {
 485         u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
 486
 487         return !((reg & (ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN))
 488                  || vcpu_mode_priv(vcpu));
 489 }
 490
 491 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
 492 {
 493         u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
 494
 495         return !((reg & (ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN))
 496                  || vcpu_mode_priv(vcpu));
 497 }
 498
 499 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 500                         const struct sys_reg_desc *r)
 501 {
 502         u64 val;
 503
 504         if (!kvm_arm_pmu_v3_ready(vcpu))
 505                 return trap_raz_wi(vcpu, p, r);
 506
 507         if (pmu_access_el0_disabled(vcpu))
 508                 return false;
 509
 510         if (p->is_write) {
 511                 /* Only update writeable bits of PMCR */
 512                 val = vcpu_sys_reg(vcpu, PMCR_EL0);
 513                 val &= ~ARMV8_PMU_PMCR_MASK;
 514                 val |= p->regval & ARMV8_PMU_PMCR_MASK;
 515                 vcpu_sys_reg(vcpu, PMCR_EL0) = val;
 516                 kvm_pmu_handle_pmcr(vcpu, val);
 517         } else {
 518                 /* PMCR.P & PMCR.C are RAZ */
 519                 val = vcpu_sys_reg(vcpu, PMCR_EL0)
 520                       & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
 521                 p->regval = val;
 522         }
 523
 524         return true;
 525 }
 526
 527 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 528                           const struct sys_reg_desc *r)
 529 {
 530         if (!kvm_arm_pmu_v3_ready(vcpu))
 531                 return trap_raz_wi(vcpu, p, r);
 532
 533         if (pmu_access_event_counter_el0_disabled(vcpu))
 534                 return false;
 535
 536         if (p->is_write)
 537                 vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
 538         else
 539                 /* return PMSELR.SEL field */
 540                 p->regval = vcpu_sys_reg(vcpu, PMSELR_EL0)
 541                             & ARMV8_PMU_COUNTER_MASK;
 542
 543         return true;
 544 }
 545
 546 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 547                           const struct sys_reg_desc *r)
 548 {
 549         u64 pmceid;
 550
 551         if (!kvm_arm_pmu_v3_ready(vcpu))
 552                 return trap_raz_wi(vcpu, p, r);
 553
 554         BUG_ON(p->is_write);
 555
 556         if (pmu_access_el0_disabled(vcpu))
 557                 return false;
 558
 559         if (!(p->Op2 & 1))
 560                 asm volatile("mrs %0, pmceid0_el0\n" : "=r" (pmceid));
 561         else
 562                 asm volatile("mrs %0, pmceid1_el0\n" : "=r" (pmceid));
 563
 564         p->regval = pmceid;
 565
 566         return true;
 567 }
 568
 569 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
 570 {
 571         u64 pmcr, val;
 572
 573         pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
 574         val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
 575         if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX)
 576                 return false;
 577
 578         return true;
 579 }
 580
 581 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
 582                               struct sys_reg_params *p,
 583                               const struct sys_reg_desc *r)
 584 {
 585         u64 idx;
 586
 587         if (!kvm_arm_pmu_v3_ready(vcpu))
 588                 return trap_raz_wi(vcpu, p, r);
 589
 590         if (r->CRn == 9 && r->CRm == 13) {
 591                 if (r->Op2 == 2) {
 592                         /* PMXEVCNTR_EL0 */
 593                         if (pmu_access_event_counter_el0_disabled(vcpu))
 594                                 return false;
 595
 596                         idx = vcpu_sys_reg(vcpu, PMSELR_EL0)
 597                               & ARMV8_PMU_COUNTER_MASK;
 598                 } else if (r->Op2 == 0) {
 599                         /* PMCCNTR_EL0 */
 600                         if (pmu_access_cycle_counter_el0_disabled(vcpu))
 601                                 return false;
 602
 603                         idx = ARMV8_PMU_CYCLE_IDX;
 604                 } else {
 605                         BUG();
 606                 }
 607         } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
 608                 /* PMEVCNTRn_EL0 */
 609                 if (pmu_access_event_counter_el0_disabled(vcpu))
 610                         return false;
 611
 612                 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
 613         } else {
 614                 BUG();
 615         }
 616
 617         if (!pmu_counter_idx_valid(vcpu, idx))
 618                 return false;
 619
 620         if (p->is_write) {
 621                 if (pmu_access_el0_disabled(vcpu))
 622                         return false;
 623
 624                 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
 625         } else {
 626                 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
 627         }
 628
 629         return true;
 630 }
 631
 632 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 633                                const struct sys_reg_desc *r)
 634 {
 635         u64 idx, reg;
 636
 637         if (!kvm_arm_pmu_v3_ready(vcpu))
 638                 return trap_raz_wi(vcpu, p, r);
 639
 640         if (pmu_access_el0_disabled(vcpu))
 641                 return false;
 642
 643         if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
 644                 /* PMXEVTYPER_EL0 */
 645                 idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
 646                 reg = PMEVTYPER0_EL0 + idx;
 647         } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
 648                 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
 649                 if (idx == ARMV8_PMU_CYCLE_IDX)
 650                         reg = PMCCFILTR_EL0;
 651                 else
 652                         /* PMEVTYPERn_EL0 */
 653                         reg = PMEVTYPER0_EL0 + idx;
 654         } else {
 655                 BUG();
 656         }
 657
 658         if (!pmu_counter_idx_valid(vcpu, idx))
 659                 return false;
 660
 661         if (p->is_write) {
 662                 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
 663                 vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
 664         } else {
 665                 p->regval = vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
 666         }
 667
 668         return true;
 669 }
 670
 671 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 672                            const struct sys_reg_desc *r)
 673 {
 674         u64 val, mask;
 675
 676         if (!kvm_arm_pmu_v3_ready(vcpu))
 677                 return trap_raz_wi(vcpu, p, r);
 678
 679         if (pmu_access_el0_disabled(vcpu))
 680                 return false;
 681
 682         mask = kvm_pmu_valid_counter_mask(vcpu);
 683         if (p->is_write) {
 684                 val = p->regval & mask;
 685                 if (r->Op2 & 0x1) {
 686                         /* accessing PMCNTENSET_EL0 */
 687                         vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
 688                         kvm_pmu_enable_counter(vcpu, val);
 689                 } else {
 690                         /* accessing PMCNTENCLR_EL0 */
 691                         vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
 692                         kvm_pmu_disable_counter(vcpu, val);
 693                 }
 694         } else {
 695                 p->regval = vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
 696         }
 697
 698         return true;
 699 }
 700
 701 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 702                            const struct sys_reg_desc *r)
 703 {
 704         u64 mask = kvm_pmu_valid_counter_mask(vcpu);
 705
 706         if (!kvm_arm_pmu_v3_ready(vcpu))
 707                 return trap_raz_wi(vcpu, p, r);
 708
 709         if (!vcpu_mode_priv(vcpu))
 710                 return false;
 711
 712         if (p->is_write) {
 713                 u64 val = p->regval & mask;
 714
 715                 if (r->Op2 & 0x1)
 716                         /* accessing PMINTENSET_EL1 */
 717                         vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
 718                 else
 719                         /* accessing PMINTENCLR_EL1 */
 720                         vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
 721         } else {
 722                 p->regval = vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
 723         }
 724
 725         return true;
 726 }
 727
 728 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 729                          const struct sys_reg_desc *r)
 730 {
 731         u64 mask = kvm_pmu_valid_counter_mask(vcpu);
 732
 733         if (!kvm_arm_pmu_v3_ready(vcpu))
 734                 return trap_raz_wi(vcpu, p, r);
 735
 736         if (pmu_access_el0_disabled(vcpu))
 737                 return false;
 738
 739         if (p->is_write) {
 740                 if (r->CRm & 0x2)
 741                         /* accessing PMOVSSET_EL0 */
 742                         kvm_pmu_overflow_set(vcpu, p->regval & mask);
 743                 else
 744                         /* accessing PMOVSCLR_EL0 */
 745                         vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
 746         } else {
 747                 p->regval = vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
 748         }
 749
 750         return true;
 751 }
 752
 753 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 754                            const struct sys_reg_desc *r)
 755 {
 756         u64 mask;
 757
 758         if (!kvm_arm_pmu_v3_ready(vcpu))
 759                 return trap_raz_wi(vcpu, p, r);
 760
 761         if (pmu_write_swinc_el0_disabled(vcpu))
 762                 return false;
 763
 764         if (p->is_write) {
 765                 mask = kvm_pmu_valid_counter_mask(vcpu);
 766                 kvm_pmu_software_increment(vcpu, p->regval & mask);
 767                 return true;
 768         }
 769
 770         return false;
 771 }
 772
 773 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 774                              const struct sys_reg_desc *r)
 775 {
 776         if (!kvm_arm_pmu_v3_ready(vcpu))
 777                 return trap_raz_wi(vcpu, p, r);
 778
 779         if (p->is_write) {
 780                 if (!vcpu_mode_priv(vcpu))
 781                         return false;
 782
 783                 vcpu_sys_reg(vcpu, PMUSERENR_EL0) = p->regval
 784                                                     & ARMV8_PMU_USERENR_MASK;
 785         } else {
 786                 p->regval = vcpu_sys_reg(vcpu, PMUSERENR_EL0)
 787                             & ARMV8_PMU_USERENR_MASK;
 788         }
 789
 790         return true;
 791 }
 792
 793 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
 794 #define DBG_BCR_BVR_WCR_WVR_EL1(n)                                      \
 795         /* DBGBVRn_EL1 */                                               \
 796         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b100),     \
 797           trap_bvr, reset_bvr, n, 0, get_bvr, set_bvr },                \
 798         /* DBGBCRn_EL1 */                                               \
 799         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b101),     \
 800           trap_bcr, reset_bcr, n, 0, get_bcr, set_bcr },                \
 801         /* DBGWVRn_EL1 */                                               \
 802         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b110),     \
 803           trap_wvr, reset_wvr, n, 0,  get_wvr, set_wvr },               \
 804         /* DBGWCRn_EL1 */                                               \
 805         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b111),     \
 806           trap_wcr, reset_wcr, n, 0,  get_wcr, set_wcr }
 807
 808 /* Macro to expand the PMEVCNTRn_EL0 register */
 809 #define PMU_PMEVCNTR_EL0(n)                                             \
 810         /* PMEVCNTRn_EL0 */                                             \
 811         { Op0(0b11), Op1(0b011), CRn(0b1110),                           \
 812           CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
 813           access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
 814
 815 /* Macro to expand the PMEVTYPERn_EL0 register */
 816 #define PMU_PMEVTYPER_EL0(n)                                            \
 817         /* PMEVTYPERn_EL0 */                                            \
 818         { Op0(0b11), Op1(0b011), CRn(0b1110),                           \
 819           CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
 820           access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
 821
 822 /*
 823  * Architected system registers.
 824  * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
 825  *
 826  * We could trap ID_DFR0 and tell the guest we don't support performance
 827  * monitoring.  Unfortunately the patch to make the kernel check ID_DFR0 was
 828  * NAKed, so it will read the PMCR anyway.
 829  *
 830  * Therefore we tell the guest we have 0 counters.  Unfortunately, we
 831  * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
 832  * all PM registers, which doesn't crash the guest kernel at least.
 833  *
 834  * Debug handling: We do trap most, if not all debug related system
 835  * registers. The implementation is good enough to ensure that a guest
 836  * can use these with minimal performance degradation. The drawback is
 837  * that we don't implement any of the external debug, none of the
 838  * OSlock protocol. This should be revisited if we ever encounter a
 839  * more demanding guest...
 840  */
 841 static const struct sys_reg_desc sys_reg_descs[] = {
 842         /* DC ISW */
 843         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010),
 844           access_dcsw },
 845         /* DC CSW */
 846         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010),
 847           access_dcsw },
 848         /* DC CISW */
 849         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
 850           access_dcsw },
 851
 852         DBG_BCR_BVR_WCR_WVR_EL1(0),
 853         DBG_BCR_BVR_WCR_WVR_EL1(1),
 854         /* MDCCINT_EL1 */
 855         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
 856           trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
 857         /* MDSCR_EL1 */
 858         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
 859           trap_debug_regs, reset_val, MDSCR_EL1, 0 },
 860         DBG_BCR_BVR_WCR_WVR_EL1(2),
 861         DBG_BCR_BVR_WCR_WVR_EL1(3),
 862         DBG_BCR_BVR_WCR_WVR_EL1(4),
 863         DBG_BCR_BVR_WCR_WVR_EL1(5),
 864         DBG_BCR_BVR_WCR_WVR_EL1(6),
 865         DBG_BCR_BVR_WCR_WVR_EL1(7),
 866         DBG_BCR_BVR_WCR_WVR_EL1(8),
 867         DBG_BCR_BVR_WCR_WVR_EL1(9),
 868         DBG_BCR_BVR_WCR_WVR_EL1(10),
 869         DBG_BCR_BVR_WCR_WVR_EL1(11),
 870         DBG_BCR_BVR_WCR_WVR_EL1(12),
 871         DBG_BCR_BVR_WCR_WVR_EL1(13),
 872         DBG_BCR_BVR_WCR_WVR_EL1(14),
 873         DBG_BCR_BVR_WCR_WVR_EL1(15),
 874
 875         /* MDRAR_EL1 */
 876         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
 877           trap_raz_wi },
 878         /* OSLAR_EL1 */
 879         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b100),
 880           trap_raz_wi },
 881         /* OSLSR_EL1 */
 882         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0001), Op2(0b100),
 883           trap_oslsr_el1 },
 884         /* OSDLR_EL1 */
 885         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0011), Op2(0b100),
 886           trap_raz_wi },
 887         /* DBGPRCR_EL1 */
 888         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0100), Op2(0b100),
 889           trap_raz_wi },
 890         /* DBGCLAIMSET_EL1 */
 891         { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1000), Op2(0b110),
 892           trap_raz_wi },
 893         /* DBGCLAIMCLR_EL1 */
 894         { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1001), Op2(0b110),
 895           trap_raz_wi },
 896         /* DBGAUTHSTATUS_EL1 */
 897         { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b110),
 898           trap_dbgauthstatus_el1 },
 899
 900         /* MDCCSR_EL1 */
 901         { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0001), Op2(0b000),
 902           trap_raz_wi },
 903         /* DBGDTR_EL0 */
 904         { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0100), Op2(0b000),
 905           trap_raz_wi },
 906         /* DBGDTR[TR]X_EL0 */
 907         { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0101), Op2(0b000),
 908           trap_raz_wi },
 909
 910         /* DBGVCR32_EL2 */
 911         { Op0(0b10), Op1(0b100), CRn(0b0000), CRm(0b0111), Op2(0b000),
 912           NULL, reset_val, DBGVCR32_EL2, 0 },
 913
 914         /* MPIDR_EL1 */
 915         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101),
 916           NULL, reset_mpidr, MPIDR_EL1 },
 917         /* SCTLR_EL1 */
 918         { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
 919           access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
 920         /* CPACR_EL1 */
 921         { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),
 922           NULL, reset_val, CPACR_EL1, 0 },
 923         /* TTBR0_EL1 */
 924         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000),
 925           access_vm_reg, reset_unknown, TTBR0_EL1 },
 926         /* TTBR1_EL1 */
 927         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001),
 928           access_vm_reg, reset_unknown, TTBR1_EL1 },
 929         /* TCR_EL1 */
 930         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010),
 931           access_vm_reg, reset_val, TCR_EL1, 0 },
 932
 933         /* AFSR0_EL1 */
 934         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000),
 935           access_vm_reg, reset_unknown, AFSR0_EL1 },
 936         /* AFSR1_EL1 */
 937         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001),
 938           access_vm_reg, reset_unknown, AFSR1_EL1 },
 939         /* ESR_EL1 */
 940         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000),
 941           access_vm_reg, reset_unknown, ESR_EL1 },
 942         /* FAR_EL1 */
 943         { Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
 944           access_vm_reg, reset_unknown, FAR_EL1 },
 945         /* PAR_EL1 */
 946         { Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000),
 947           NULL, reset_unknown, PAR_EL1 },
 948
 949         /* PMINTENSET_EL1 */
 950         { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
 951           access_pminten, reset_unknown, PMINTENSET_EL1 },
 952         /* PMINTENCLR_EL1 */
 953         { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
 954           access_pminten, NULL, PMINTENSET_EL1 },
 955
 956         /* MAIR_EL1 */
 957         { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
 958           access_vm_reg, reset_unknown, MAIR_EL1 },
 959         /* AMAIR_EL1 */
 960         { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000),
 961           access_vm_reg, reset_amair_el1, AMAIR_EL1 },
 962
 963         /* VBAR_EL1 */
 964         { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
 965           NULL, reset_val, VBAR_EL1, 0 },
 966
 967         /* ICC_SGI1R_EL1 */
 968         { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1011), Op2(0b101),
 969           access_gic_sgi },
 970         /* ICC_SRE_EL1 */
 971         { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1100), Op2(0b101),
 972           access_gic_sre },
 973
 974         /* CONTEXTIDR_EL1 */
 975         { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
 976           access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
 977         /* TPIDR_EL1 */
 978         { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100),
 979           NULL, reset_unknown, TPIDR_EL1 },
 980
 981         /* CNTKCTL_EL1 */
 982         { Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000),
 983           NULL, reset_val, CNTKCTL_EL1, 0},
 984
 985         /* CSSELR_EL1 */
 986         { Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
 987           NULL, reset_unknown, CSSELR_EL1 },
 988
 989         /* PMCR_EL0 */
 990         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
 991           access_pmcr, reset_pmcr, },
 992         /* PMCNTENSET_EL0 */
 993         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
 994           access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
 995         /* PMCNTENCLR_EL0 */
 996         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
 997           access_pmcnten, NULL, PMCNTENSET_EL0 },
 998         /* PMOVSCLR_EL0 */
 999         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
1000           access_pmovs, NULL, PMOVSSET_EL0 },
1001         /* PMSWINC_EL0 */
1002         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
1003           access_pmswinc, reset_unknown, PMSWINC_EL0 },
1004         /* PMSELR_EL0 */
1005         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
1006           access_pmselr, reset_unknown, PMSELR_EL0 },
1007         /* PMCEID0_EL0 */
1008         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
1009           access_pmceid },
1010         /* PMCEID1_EL0 */
1011         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
1012           access_pmceid },
1013         /* PMCCNTR_EL0 */
1014         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
1015           access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 },
1016         /* PMXEVTYPER_EL0 */
1017         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
1018           access_pmu_evtyper },
1019         /* PMXEVCNTR_EL0 */
1020         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
1021           access_pmu_evcntr },
1022         /* PMUSERENR_EL0
1023          * This register resets as unknown in 64bit mode while it resets as zero
1024          * in 32bit mode. Here we choose to reset it as zero for consistency.
1025          */
1026         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
1027           access_pmuserenr, reset_val, PMUSERENR_EL0, 0 },
1028         /* PMOVSSET_EL0 */
1029         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
1030           access_pmovs, reset_unknown, PMOVSSET_EL0 },
1031
1032         /* TPIDR_EL0 */
1033         { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010),
1034           NULL, reset_unknown, TPIDR_EL0 },
1035         /* TPIDRRO_EL0 */
1036         { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
1037           NULL, reset_unknown, TPIDRRO_EL0 },
1038
1039         /* PMEVCNTRn_EL0 */
1040         PMU_PMEVCNTR_EL0(0),
1041         PMU_PMEVCNTR_EL0(1),
1042         PMU_PMEVCNTR_EL0(2),
1043         PMU_PMEVCNTR_EL0(3),
1044         PMU_PMEVCNTR_EL0(4),
1045         PMU_PMEVCNTR_EL0(5),
1046         PMU_PMEVCNTR_EL0(6),
1047         PMU_PMEVCNTR_EL0(7),
1048         PMU_PMEVCNTR_EL0(8),
1049         PMU_PMEVCNTR_EL0(9),
1050         PMU_PMEVCNTR_EL0(10),
1051         PMU_PMEVCNTR_EL0(11),
1052         PMU_PMEVCNTR_EL0(12),
1053         PMU_PMEVCNTR_EL0(13),
1054         PMU_PMEVCNTR_EL0(14),
1055         PMU_PMEVCNTR_EL0(15),
1056         PMU_PMEVCNTR_EL0(16),
1057         PMU_PMEVCNTR_EL0(17),
1058         PMU_PMEVCNTR_EL0(18),
1059         PMU_PMEVCNTR_EL0(19),
1060         PMU_PMEVCNTR_EL0(20),
1061         PMU_PMEVCNTR_EL0(21),
1062         PMU_PMEVCNTR_EL0(22),
1063         PMU_PMEVCNTR_EL0(23),
1064         PMU_PMEVCNTR_EL0(24),
1065         PMU_PMEVCNTR_EL0(25),
1066         PMU_PMEVCNTR_EL0(26),
1067         PMU_PMEVCNTR_EL0(27),
1068         PMU_PMEVCNTR_EL0(28),
1069         PMU_PMEVCNTR_EL0(29),
1070         PMU_PMEVCNTR_EL0(30),
1071         /* PMEVTYPERn_EL0 */
1072         PMU_PMEVTYPER_EL0(0),
1073         PMU_PMEVTYPER_EL0(1),
1074         PMU_PMEVTYPER_EL0(2),
1075         PMU_PMEVTYPER_EL0(3),
1076         PMU_PMEVTYPER_EL0(4),
1077         PMU_PMEVTYPER_EL0(5),
1078         PMU_PMEVTYPER_EL0(6),
1079         PMU_PMEVTYPER_EL0(7),
1080         PMU_PMEVTYPER_EL0(8),
1081         PMU_PMEVTYPER_EL0(9),
1082         PMU_PMEVTYPER_EL0(10),
1083         PMU_PMEVTYPER_EL0(11),
1084         PMU_PMEVTYPER_EL0(12),
1085         PMU_PMEVTYPER_EL0(13),
1086         PMU_PMEVTYPER_EL0(14),
1087         PMU_PMEVTYPER_EL0(15),
1088         PMU_PMEVTYPER_EL0(16),
1089         PMU_PMEVTYPER_EL0(17),
1090         PMU_PMEVTYPER_EL0(18),
1091         PMU_PMEVTYPER_EL0(19),
1092         PMU_PMEVTYPER_EL0(20),
1093         PMU_PMEVTYPER_EL0(21),
1094         PMU_PMEVTYPER_EL0(22),
1095         PMU_PMEVTYPER_EL0(23),
1096         PMU_PMEVTYPER_EL0(24),
1097         PMU_PMEVTYPER_EL0(25),
1098         PMU_PMEVTYPER_EL0(26),
1099         PMU_PMEVTYPER_EL0(27),
1100         PMU_PMEVTYPER_EL0(28),
1101         PMU_PMEVTYPER_EL0(29),
1102         PMU_PMEVTYPER_EL0(30),
1103         /* PMCCFILTR_EL0
1104          * This register resets as unknown in 64bit mode while it resets as zero
1105          * in 32bit mode. Here we choose to reset it as zero for consistency.
1106          */
1107         { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b1111), Op2(0b111),
1108           access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
1109
1110         /* DACR32_EL2 */
1111         { Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
1112           NULL, reset_unknown, DACR32_EL2 },
1113         /* IFSR32_EL2 */
1114         { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001),
1115           NULL, reset_unknown, IFSR32_EL2 },
1116         /* FPEXC32_EL2 */
1117         { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000),
1118           NULL, reset_val, FPEXC32_EL2, 0x70 },
1119 };
1120
1121 static bool trap_dbgidr(struct kvm_vcpu *vcpu,
1122                         struct sys_reg_params *p,
1123                         const struct sys_reg_desc *r)
1124 {
1125         if (p->is_write) {
1126                 return ignore_write(vcpu, p);
1127         } else {
1128                 u64 dfr = read_system_reg(SYS_ID_AA64DFR0_EL1);
1129                 u64 pfr = read_system_reg(SYS_ID_AA64PFR0_EL1);
1130                 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
1131
1132                 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1133                              (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1134                              (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1135                              | (6 << 16) | (el3 << 14) | (el3 << 12));
1136                 return true;
1137         }
1138 }
1139
1140 static bool trap_debug32(struct kvm_vcpu *vcpu,
1141                          struct sys_reg_params *p,
1142                          const struct sys_reg_desc *r)
1143 {
1144         if (p->is_write) {
1145                 vcpu_cp14(vcpu, r->reg) = p->regval;
1146                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
1147         } else {
1148                 p->regval = vcpu_cp14(vcpu, r->reg);
1149         }
1150
1151         return true;
1152 }
1153
1154 /* AArch32 debug register mappings
1155  *
1156  * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1157  * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1158  *
1159  * All control registers and watchpoint value registers are mapped to
1160  * the lower 32 bits of their AArch64 equivalents. We share the trap
1161  * handlers with the above AArch64 code which checks what mode the
1162  * system is in.
1163  */
1164
1165 static bool trap_xvr(struct kvm_vcpu *vcpu,
1166                      struct sys_reg_params *p,
1167                      const struct sys_reg_desc *rd)
1168 {
1169         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
1170
1171         if (p->is_write) {
1172                 u64 val = *dbg_reg;
1173
1174                 val &= 0xffffffffUL;
1175                 val |= p->regval << 32;
1176                 *dbg_reg = val;
1177
1178                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
1179         } else {
1180                 p->regval = *dbg_reg >> 32;
1181         }
1182
1183         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
1184
1185         return true;
1186 }
1187
1188 #define DBG_BCR_BVR_WCR_WVR(n)                                          \
1189         /* DBGBVRn */                                                   \
1190         { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n },     \
1191         /* DBGBCRn */                                                   \
1192         { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n },     \
1193         /* DBGWVRn */                                                   \
1194         { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n },     \
1195         /* DBGWCRn */                                                   \
1196         { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1197
1198 #define DBGBXVR(n)                                                      \
1199         { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
1200
1201 /*
1202  * Trapped cp14 registers. We generally ignore most of the external
1203  * debug, on the principle that they don't really make sense to a
1204  * guest. Revisit this one day, would this principle change.
1205  */
1206 static const struct sys_reg_desc cp14_regs[] = {
1207         /* DBGIDR */
1208         { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
1209         /* DBGDTRRXext */
1210         { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1211
1212         DBG_BCR_BVR_WCR_WVR(0),
1213         /* DBGDSCRint */
1214         { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1215         DBG_BCR_BVR_WCR_WVR(1),
1216         /* DBGDCCINT */
1217         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
1218         /* DBGDSCRext */
1219         { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
1220         DBG_BCR_BVR_WCR_WVR(2),
1221         /* DBGDTR[RT]Xint */
1222         { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1223         /* DBGDTR[RT]Xext */
1224         { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1225         DBG_BCR_BVR_WCR_WVR(3),
1226         DBG_BCR_BVR_WCR_WVR(4),
1227         DBG_BCR_BVR_WCR_WVR(5),
1228         /* DBGWFAR */
1229         { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1230         /* DBGOSECCR */
1231         { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1232         DBG_BCR_BVR_WCR_WVR(6),
1233         /* DBGVCR */
1234         { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
1235         DBG_BCR_BVR_WCR_WVR(7),
1236         DBG_BCR_BVR_WCR_WVR(8),
1237         DBG_BCR_BVR_WCR_WVR(9),
1238         DBG_BCR_BVR_WCR_WVR(10),
1239         DBG_BCR_BVR_WCR_WVR(11),
1240         DBG_BCR_BVR_WCR_WVR(12),
1241         DBG_BCR_BVR_WCR_WVR(13),
1242         DBG_BCR_BVR_WCR_WVR(14),
1243         DBG_BCR_BVR_WCR_WVR(15),
1244
1245         /* DBGDRAR (32bit) */
1246         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1247
1248         DBGBXVR(0),
1249         /* DBGOSLAR */
1250         { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1251         DBGBXVR(1),
1252         /* DBGOSLSR */
1253         { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1254         DBGBXVR(2),
1255         DBGBXVR(3),
1256         /* DBGOSDLR */
1257         { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1258         DBGBXVR(4),
1259         /* DBGPRCR */
1260         { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1261         DBGBXVR(5),
1262         DBGBXVR(6),
1263         DBGBXVR(7),
1264         DBGBXVR(8),
1265         DBGBXVR(9),
1266         DBGBXVR(10),
1267         DBGBXVR(11),
1268         DBGBXVR(12),
1269         DBGBXVR(13),
1270         DBGBXVR(14),
1271         DBGBXVR(15),
1272
1273         /* DBGDSAR (32bit) */
1274         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1275
1276         /* DBGDEVID2 */
1277         { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1278         /* DBGDEVID1 */
1279         { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1280         /* DBGDEVID */
1281         { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1282         /* DBGCLAIMSET */
1283         { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1284         /* DBGCLAIMCLR */
1285         { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1286         /* DBGAUTHSTATUS */
1287         { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
1288 };
1289
1290 /* Trapped cp14 64bit registers */
1291 static const struct sys_reg_desc cp14_64_regs[] = {
1292         /* DBGDRAR (64bit) */
1293         { Op1( 0), CRm( 1), .access = trap_raz_wi },
1294
1295         /* DBGDSAR (64bit) */
1296         { Op1( 0), CRm( 2), .access = trap_raz_wi },
1297 };
1298
1299 /* Macro to expand the PMEVCNTRn register */
1300 #define PMU_PMEVCNTR(n)                                                 \
1301         /* PMEVCNTRn */                                                 \
1302         { Op1(0), CRn(0b1110),                                          \
1303           CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
1304           access_pmu_evcntr }
1305
1306 /* Macro to expand the PMEVTYPERn register */
1307 #define PMU_PMEVTYPER(n)                                                \
1308         /* PMEVTYPERn */                                                \
1309         { Op1(0), CRn(0b1110),                                          \
1310           CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
1311           access_pmu_evtyper }
1312
1313 /*
1314  * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1315  * depending on the way they are accessed (as a 32bit or a 64bit
1316  * register).
1317  */
1318 static const struct sys_reg_desc cp15_regs[] = {
1319         { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
1320
1321         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
1322         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1323         { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
1324         { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
1325         { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
1326         { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
1327         { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
1328         { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
1329         { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
1330         { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
1331         { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
1332
1333         /*
1334          * DC{C,I,CI}SW operations:
1335          */
1336         { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
1337         { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
1338         { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
1339
1340         /* PMU */
1341         { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
1342         { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
1343         { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
1344         { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
1345         { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
1346         { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
1347         { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
1348         { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
1349         { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
1350         { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
1351         { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
1352         { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
1353         { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
1354         { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
1355         { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
1356
1357         { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
1358         { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
1359         { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
1360         { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
1361
1362         /* ICC_SRE */
1363         { Op1( 0), CRn(12), CRm(12), Op2( 5), trap_raz_wi },
1364
1365         { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
1366
1367         /* PMEVCNTRn */
1368         PMU_PMEVCNTR(0),
1369         PMU_PMEVCNTR(1),
1370         PMU_PMEVCNTR(2),
1371         PMU_PMEVCNTR(3),
1372         PMU_PMEVCNTR(4),
1373         PMU_PMEVCNTR(5),
1374         PMU_PMEVCNTR(6),
1375         PMU_PMEVCNTR(7),
1376         PMU_PMEVCNTR(8),
1377         PMU_PMEVCNTR(9),
1378         PMU_PMEVCNTR(10),
1379         PMU_PMEVCNTR(11),
1380         PMU_PMEVCNTR(12),
1381         PMU_PMEVCNTR(13),
1382         PMU_PMEVCNTR(14),
1383         PMU_PMEVCNTR(15),
1384         PMU_PMEVCNTR(16),
1385         PMU_PMEVCNTR(17),
1386         PMU_PMEVCNTR(18),
1387         PMU_PMEVCNTR(19),
1388         PMU_PMEVCNTR(20),
1389         PMU_PMEVCNTR(21),
1390         PMU_PMEVCNTR(22),
1391         PMU_PMEVCNTR(23),
1392         PMU_PMEVCNTR(24),
1393         PMU_PMEVCNTR(25),
1394         PMU_PMEVCNTR(26),
1395         PMU_PMEVCNTR(27),
1396         PMU_PMEVCNTR(28),
1397         PMU_PMEVCNTR(29),
1398         PMU_PMEVCNTR(30),
1399         /* PMEVTYPERn */
1400         PMU_PMEVTYPER(0),
1401         PMU_PMEVTYPER(1),
1402         PMU_PMEVTYPER(2),
1403         PMU_PMEVTYPER(3),
1404         PMU_PMEVTYPER(4),
1405         PMU_PMEVTYPER(5),
1406         PMU_PMEVTYPER(6),
1407         PMU_PMEVTYPER(7),
1408         PMU_PMEVTYPER(8),
1409         PMU_PMEVTYPER(9),
1410         PMU_PMEVTYPER(10),
1411         PMU_PMEVTYPER(11),
1412         PMU_PMEVTYPER(12),
1413         PMU_PMEVTYPER(13),
1414         PMU_PMEVTYPER(14),
1415         PMU_PMEVTYPER(15),
1416         PMU_PMEVTYPER(16),
1417         PMU_PMEVTYPER(17),
1418         PMU_PMEVTYPER(18),
1419         PMU_PMEVTYPER(19),
1420         PMU_PMEVTYPER(20),
1421         PMU_PMEVTYPER(21),
1422         PMU_PMEVTYPER(22),
1423         PMU_PMEVTYPER(23),
1424         PMU_PMEVTYPER(24),
1425         PMU_PMEVTYPER(25),
1426         PMU_PMEVTYPER(26),
1427         PMU_PMEVTYPER(27),
1428         PMU_PMEVTYPER(28),
1429         PMU_PMEVTYPER(29),
1430         PMU_PMEVTYPER(30),
1431         /* PMCCFILTR */
1432         { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
1433 };
1434
1435 static const struct sys_reg_desc cp15_64_regs[] = {
1436         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1437         { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
1438         { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
1439         { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
1440 };
1441
1442 /* Target specific emulation tables */
1443 static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
1444
1445 void kvm_register_target_sys_reg_table(unsigned int target,
1446                                        struct kvm_sys_reg_target_table *table)
1447 {
1448         target_tables[target] = table;
1449 }
1450
1451 /* Get specific register table for this target. */
1452 static const struct sys_reg_desc *get_target_table(unsigned target,
1453                                                    bool mode_is_64,
1454                                                    size_t *num)
1455 {
1456         struct kvm_sys_reg_target_table *table;
1457
1458         table = target_tables[target];
1459         if (mode_is_64) {
1460                 *num = table->table64.num;
1461                 return table->table64.table;
1462         } else {
1463                 *num = table->table32.num;
1464                 return table->table32.table;
1465         }
1466 }
1467
1468 #define reg_to_match_value(x)                                           \
1469         ({                                                              \
1470                 unsigned long val;                                      \
1471                 val  = (x)->Op0 << 14;                                  \
1472                 val |= (x)->Op1 << 11;                                  \
1473                 val |= (x)->CRn << 7;                                   \
1474                 val |= (x)->CRm << 3;                                   \
1475                 val |= (x)->Op2;                                        \
1476                 val;                                                    \
1477          })
1478
1479 static int match_sys_reg(const void *key, const void *elt)
1480 {
1481         const unsigned long pval = (unsigned long)key;
1482         const struct sys_reg_desc *r = elt;
1483
1484         return pval - reg_to_match_value(r);
1485 }
1486
1487 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
1488                                          const struct sys_reg_desc table[],
1489                                          unsigned int num)
1490 {
1491         unsigned long pval = reg_to_match_value(params);
1492
1493         return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
1494 }
1495
1496 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
1497 {
1498         kvm_inject_undefined(vcpu);
1499         return 1;
1500 }
1501
1502 /*
1503  * emulate_cp --  tries to match a sys_reg access in a handling table, and
1504  *                call the corresponding trap handler.
1505  *
1506  * @params: pointer to the descriptor of the access
1507  * @table: array of trap descriptors
1508  * @num: size of the trap descriptor array
1509  *
1510  * Return 0 if the access has been handled, and -1 if not.
1511  */
1512 static int emulate_cp(struct kvm_vcpu *vcpu,
1513                       struct sys_reg_params *params,
1514                       const struct sys_reg_desc *table,
1515                       size_t num)
1516 {
1517         const struct sys_reg_desc *r;
1518
1519         if (!table)
1520                 return -1;      /* Not handled */
1521
1522         r = find_reg(params, table, num);
1523
1524         if (r) {
1525                 /*
1526                  * Not having an accessor means that we have
1527                  * configured a trap that we don't know how to
1528                  * handle. This certainly qualifies as a gross bug
1529                  * that should be fixed right away.
1530                  */
1531                 BUG_ON(!r->access);
1532
1533                 if (likely(r->access(vcpu, params, r))) {
1534                         /* Skip instruction, since it was emulated */
1535                         kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
1536                         /* Handled */
1537                         return 0;
1538                 }
1539         }
1540
1541         /* Not handled */
1542         return -1;
1543 }
1544
1545 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
1546                                 struct sys_reg_params *params)
1547 {
1548         u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
1549         int cp = -1;
1550
1551         switch(hsr_ec) {
1552         case ESR_ELx_EC_CP15_32:
1553         case ESR_ELx_EC_CP15_64:
1554                 cp = 15;
1555                 break;
1556         case ESR_ELx_EC_CP14_MR:
1557         case ESR_ELx_EC_CP14_64:
1558                 cp = 14;
1559                 break;
1560         default:
1561                 WARN_ON(1);
1562         }
1563
1564         kvm_err("Unsupported guest CP%d access at: %08lx\n",
1565                 cp, *vcpu_pc(vcpu));
1566         print_sys_reg_instr(params);
1567         kvm_inject_undefined(vcpu);
1568 }
1569
1570 /**
1571  * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
1572  * @vcpu: The VCPU pointer
1573  * @run:  The kvm_run struct
1574  */
1575 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
1576                             const struct sys_reg_desc *global,
1577                             size_t nr_global,
1578                             const struct sys_reg_desc *target_specific,
1579                             size_t nr_specific)
1580 {
1581         struct sys_reg_params params;
1582         u32 hsr = kvm_vcpu_get_hsr(vcpu);
1583         int Rt = (hsr >> 5) & 0xf;
1584         int Rt2 = (hsr >> 10) & 0xf;
1585
1586         params.is_aarch32 = true;
1587         params.is_32bit = false;
1588         params.CRm = (hsr >> 1) & 0xf;
1589         params.is_write = ((hsr & 1) == 0);
1590
1591         params.Op0 = 0;
1592         params.Op1 = (hsr >> 16) & 0xf;
1593         params.Op2 = 0;
1594         params.CRn = 0;
1595
1596         /*
1597          * Make a 64-bit value out of Rt and Rt2. As we use the same trap
1598          * backends between AArch32 and AArch64, we get away with it.
1599          */
1600         if (params.is_write) {
1601                 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
1602                 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
1603         }
1604
1605         if (!emulate_cp(vcpu, &params, target_specific, nr_specific))
1606                 goto out;
1607         if (!emulate_cp(vcpu, &params, global, nr_global))
1608                 goto out;
1609
1610         unhandled_cp_access(vcpu, &params);
1611
1612 out:
1613         /* Split up the value between registers for the read side */
1614         if (!params.is_write) {
1615                 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
1616                 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
1617         }
1618
1619         return 1;
1620 }
1621
1622 /**
1623  * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
1624  * @vcpu: The VCPU pointer
1625  * @run:  The kvm_run struct
1626  */
1627 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
1628                             const struct sys_reg_desc *global,
1629                             size_t nr_global,
1630                             const struct sys_reg_desc *target_specific,
1631                             size_t nr_specific)
1632 {
1633         struct sys_reg_params params;
1634         u32 hsr = kvm_vcpu_get_hsr(vcpu);
1635         int Rt  = (hsr >> 5) & 0xf;
1636
1637         params.is_aarch32 = true;
1638         params.is_32bit = true;
1639         params.CRm = (hsr >> 1) & 0xf;
1640         params.regval = vcpu_get_reg(vcpu, Rt);
1641         params.is_write = ((hsr & 1) == 0);
1642         params.CRn = (hsr >> 10) & 0xf;
1643         params.Op0 = 0;
1644         params.Op1 = (hsr >> 14) & 0x7;
1645         params.Op2 = (hsr >> 17) & 0x7;
1646
1647         if (!emulate_cp(vcpu, &params, target_specific, nr_specific) ||
1648             !emulate_cp(vcpu, &params, global, nr_global)) {
1649                 if (!params.is_write)
1650                         vcpu_set_reg(vcpu, Rt, params.regval);
1651                 return 1;
1652         }
1653
1654         unhandled_cp_access(vcpu, &params);
1655         return 1;
1656 }
1657
1658 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
1659 {
1660         const struct sys_reg_desc *target_specific;
1661         size_t num;
1662
1663         target_specific = get_target_table(vcpu->arch.target, false, &num);
1664         return kvm_handle_cp_64(vcpu,
1665                                 cp15_64_regs, ARRAY_SIZE(cp15_64_regs),
1666                                 target_specific, num);
1667 }
1668
1669 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
1670 {
1671         const struct sys_reg_desc *target_specific;
1672         size_t num;
1673
1674         target_specific = get_target_table(vcpu->arch.target, false, &num);
1675         return kvm_handle_cp_32(vcpu,
1676                                 cp15_regs, ARRAY_SIZE(cp15_regs),
1677                                 target_specific, num);
1678 }
1679
1680 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
1681 {
1682         return kvm_handle_cp_64(vcpu,
1683                                 cp14_64_regs, ARRAY_SIZE(cp14_64_regs),
1684                                 NULL, 0);
1685 }
1686
1687 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
1688 {
1689         return kvm_handle_cp_32(vcpu,
1690                                 cp14_regs, ARRAY_SIZE(cp14_regs),
1691                                 NULL, 0);
1692 }
1693
1694 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
1695                            struct sys_reg_params *params)
1696 {
1697         size_t num;
1698         const struct sys_reg_desc *table, *r;
1699
1700         table = get_target_table(vcpu->arch.target, true, &num);
1701
1702         /* Search target-specific then generic table. */
1703         r = find_reg(params, table, num);
1704         if (!r)
1705                 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1706
1707         if (likely(r)) {
1708                 /*
1709                  * Not having an accessor means that we have
1710                  * configured a trap that we don't know how to
1711                  * handle. This certainly qualifies as a gross bug
1712                  * that should be fixed right away.
1713                  */
1714                 BUG_ON(!r->access);
1715
1716                 if (likely(r->access(vcpu, params, r))) {
1717                         /* Skip instruction, since it was emulated */
1718                         kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
1719                         return 1;
1720                 }
1721                 /* If access function fails, it should complain. */
1722         } else {
1723                 kvm_err("Unsupported guest sys_reg access at: %lx\n",
1724                         *vcpu_pc(vcpu));
1725                 print_sys_reg_instr(params);
1726         }
1727         kvm_inject_undefined(vcpu);
1728         return 1;
1729 }
1730
1731 static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
1732                               const struct sys_reg_desc *table, size_t num)
1733 {
1734         unsigned long i;
1735
1736         for (i = 0; i < num; i++)
1737                 if (table[i].reset)
1738                         table[i].reset(vcpu, &table[i]);
1739 }
1740
1741 /**
1742  * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
1743  * @vcpu: The VCPU pointer
1744  * @run:  The kvm_run struct
1745  */
1746 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
1747 {
1748         struct sys_reg_params params;
1749         unsigned long esr = kvm_vcpu_get_hsr(vcpu);
1750         int Rt = (esr >> 5) & 0x1f;
1751         int ret;
1752
1753         trace_kvm_handle_sys_reg(esr);
1754
1755         params.is_aarch32 = false;
1756         params.is_32bit = false;
1757         params.Op0 = (esr >> 20) & 3;
1758         params.Op1 = (esr >> 14) & 0x7;
1759         params.CRn = (esr >> 10) & 0xf;
1760         params.CRm = (esr >> 1) & 0xf;
1761         params.Op2 = (esr >> 17) & 0x7;
1762         params.regval = vcpu_get_reg(vcpu, Rt);
1763         params.is_write = !(esr & 1);
1764
1765         ret = emulate_sys_reg(vcpu, &params);
1766
1767         if (!params.is_write)
1768                 vcpu_set_reg(vcpu, Rt, params.regval);
1769         return ret;
1770 }
1771
1772 /******************************************************************************
1773  * Userspace API
1774  *****************************************************************************/
1775
1776 static bool index_to_params(u64 id, struct sys_reg_params *params)
1777 {
1778         switch (id & KVM_REG_SIZE_MASK) {
1779         case KVM_REG_SIZE_U64:
1780                 /* Any unused index bits means it's not valid. */
1781                 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
1782                               | KVM_REG_ARM_COPROC_MASK
1783                               | KVM_REG_ARM64_SYSREG_OP0_MASK
1784                               | KVM_REG_ARM64_SYSREG_OP1_MASK
1785                               | KVM_REG_ARM64_SYSREG_CRN_MASK
1786                               | KVM_REG_ARM64_SYSREG_CRM_MASK
1787                               | KVM_REG_ARM64_SYSREG_OP2_MASK))
1788                         return false;
1789                 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
1790                                >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
1791                 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
1792                                >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
1793                 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
1794                                >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
1795                 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
1796                                >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
1797                 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
1798                                >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
1799                 return true;
1800         default:
1801                 return false;
1802         }
1803 }
1804
1805 /* Decode an index value, and find the sys_reg_desc entry. */
1806 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
1807                                                     u64 id)
1808 {
1809         size_t num;
1810         const struct sys_reg_desc *table, *r;
1811         struct sys_reg_params params;
1812
1813         /* We only do sys_reg for now. */
1814         if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
1815                 return NULL;
1816
1817         if (!index_to_params(id, &params))
1818                 return NULL;
1819
1820         table = get_target_table(vcpu->arch.target, true, &num);
1821         r = find_reg(&params, table, num);
1822         if (!r)
1823                 r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1824
1825         /* Not saved in the sys_reg array? */
1826         if (r && !r->reg)
1827                 r = NULL;
1828
1829         return r;
1830 }
1831
1832 /*
1833  * These are the invariant sys_reg registers: we let the guest see the
1834  * host versions of these, so they're part of the guest state.
1835  *
1836  * A future CPU may provide a mechanism to present different values to
1837  * the guest, or a future kvm may trap them.
1838  */
1839
1840 #define FUNCTION_INVARIANT(reg)                                         \
1841         static void get_##reg(struct kvm_vcpu *v,                       \
1842                               const struct sys_reg_desc *r)             \
1843         {                                                               \
1844                 u64 val;                                                \
1845                                                                         \
1846                 asm volatile("mrs %0, " __stringify(reg) "\n"           \
1847                              : "=r" (val));                             \
1848                 ((struct sys_reg_desc *)r)->val = val;                  \
1849         }
1850
1851 FUNCTION_INVARIANT(midr_el1)
1852 FUNCTION_INVARIANT(ctr_el0)
1853 FUNCTION_INVARIANT(revidr_el1)
1854 FUNCTION_INVARIANT(id_pfr0_el1)
1855 FUNCTION_INVARIANT(id_pfr1_el1)
1856 FUNCTION_INVARIANT(id_dfr0_el1)
1857 FUNCTION_INVARIANT(id_afr0_el1)
1858 FUNCTION_INVARIANT(id_mmfr0_el1)
1859 FUNCTION_INVARIANT(id_mmfr1_el1)
1860 FUNCTION_INVARIANT(id_mmfr2_el1)
1861 FUNCTION_INVARIANT(id_mmfr3_el1)
1862 FUNCTION_INVARIANT(id_isar0_el1)
1863 FUNCTION_INVARIANT(id_isar1_el1)
1864 FUNCTION_INVARIANT(id_isar2_el1)
1865 FUNCTION_INVARIANT(id_isar3_el1)
1866 FUNCTION_INVARIANT(id_isar4_el1)
1867 FUNCTION_INVARIANT(id_isar5_el1)
1868 FUNCTION_INVARIANT(clidr_el1)
1869 FUNCTION_INVARIANT(aidr_el1)
1870
1871 /* ->val is filled in by kvm_sys_reg_table_init() */
1872 static struct sys_reg_desc invariant_sys_regs[] = {
1873         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000),
1874           NULL, get_midr_el1 },
1875         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110),
1876           NULL, get_revidr_el1 },
1877         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000),
1878           NULL, get_id_pfr0_el1 },
1879         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b001),
1880           NULL, get_id_pfr1_el1 },
1881         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b010),
1882           NULL, get_id_dfr0_el1 },
1883         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b011),
1884           NULL, get_id_afr0_el1 },
1885         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b100),
1886           NULL, get_id_mmfr0_el1 },
1887         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b101),
1888           NULL, get_id_mmfr1_el1 },
1889         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b110),
1890           NULL, get_id_mmfr2_el1 },
1891         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b111),
1892           NULL, get_id_mmfr3_el1 },
1893         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
1894           NULL, get_id_isar0_el1 },
1895         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b001),
1896           NULL, get_id_isar1_el1 },
1897         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
1898           NULL, get_id_isar2_el1 },
1899         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b011),
1900           NULL, get_id_isar3_el1 },
1901         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b100),
1902           NULL, get_id_isar4_el1 },
1903         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b101),
1904           NULL, get_id_isar5_el1 },
1905         { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b001),
1906           NULL, get_clidr_el1 },
1907         { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b111),
1908           NULL, get_aidr_el1 },
1909         { Op0(0b11), Op1(0b011), CRn(0b0000), CRm(0b0000), Op2(0b001),
1910           NULL, get_ctr_el0 },
1911 };
1912
1913 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
1914 {
1915         if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
1916                 return -EFAULT;
1917         return 0;
1918 }
1919
1920 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
1921 {
1922         if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
1923                 return -EFAULT;
1924         return 0;
1925 }
1926
1927 static int get_invariant_sys_reg(u64 id, void __user *uaddr)
1928 {
1929         struct sys_reg_params params;
1930         const struct sys_reg_desc *r;
1931
1932         if (!index_to_params(id, &params))
1933                 return -ENOENT;
1934
1935         r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1936         if (!r)
1937                 return -ENOENT;
1938
1939         return reg_to_user(uaddr, &r->val, id);
1940 }
1941
1942 static int set_invariant_sys_reg(u64 id, void __user *uaddr)
1943 {
1944         struct sys_reg_params params;
1945         const struct sys_reg_desc *r;
1946         int err;
1947         u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
1948
1949         if (!index_to_params(id, &params))
1950                 return -ENOENT;
1951         r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1952         if (!r)
1953                 return -ENOENT;
1954
1955         err = reg_from_user(&val, uaddr, id);
1956         if (err)
1957                 return err;
1958
1959         /* This is what we mean by invariant: you can't change it. */
1960         if (r->val != val)
1961                 return -EINVAL;
1962
1963         return 0;
1964 }
1965
1966 static bool is_valid_cache(u32 val)
1967 {
1968         u32 level, ctype;
1969
1970         if (val >= CSSELR_MAX)
1971                 return false;
1972
1973         /* Bottom bit is Instruction or Data bit.  Next 3 bits are level. */
1974         level = (val >> 1);
1975         ctype = (cache_levels >> (level * 3)) & 7;
1976
1977         switch (ctype) {
1978         case 0: /* No cache */
1979                 return false;
1980         case 1: /* Instruction cache only */
1981                 return (val & 1);
1982         case 2: /* Data cache only */
1983         case 4: /* Unified cache */
1984                 return !(val & 1);
1985         case 3: /* Separate instruction and data caches */
1986                 return true;
1987         default: /* Reserved: we can't know instruction or data. */
1988                 return false;
1989         }
1990 }
1991
1992 static int demux_c15_get(u64 id, void __user *uaddr)
1993 {
1994         u32 val;
1995         u32 __user *uval = uaddr;
1996
1997         /* Fail if we have unknown bits set. */
1998         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1999                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2000                 return -ENOENT;
2001
2002         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2003         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2004                 if (KVM_REG_SIZE(id) != 4)
2005                         return -ENOENT;
2006                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2007                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2008                 if (!is_valid_cache(val))
2009                         return -ENOENT;
2010
2011                 return put_user(get_ccsidr(val), uval);
2012         default:
2013                 return -ENOENT;
2014         }
2015 }
2016
2017 static int demux_c15_set(u64 id, void __user *uaddr)
2018 {
2019         u32 val, newval;
2020         u32 __user *uval = uaddr;
2021
2022         /* Fail if we have unknown bits set. */
2023         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2024                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2025                 return -ENOENT;
2026
2027         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2028         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2029                 if (KVM_REG_SIZE(id) != 4)
2030                         return -ENOENT;
2031                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2032                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2033                 if (!is_valid_cache(val))
2034                         return -ENOENT;
2035
2036                 if (get_user(newval, uval))
2037                         return -EFAULT;
2038
2039                 /* This is also invariant: you can't change it. */
2040                 if (newval != get_ccsidr(val))
2041                         return -EINVAL;
2042                 return 0;
2043         default:
2044                 return -ENOENT;
2045         }
2046 }
2047
2048 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2049 {
2050         const struct sys_reg_desc *r;
2051         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2052
2053         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2054                 return demux_c15_get(reg->id, uaddr);
2055
2056         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2057                 return -ENOENT;
2058
2059         r = index_to_sys_reg_desc(vcpu, reg->id);
2060         if (!r)
2061                 return get_invariant_sys_reg(reg->id, uaddr);
2062
2063         if (r->get_user)
2064                 return (r->get_user)(vcpu, r, reg, uaddr);
2065
2066         return reg_to_user(uaddr, &vcpu_sys_reg(vcpu, r->reg), reg->id);
2067 }
2068
2069 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2070 {
2071         const struct sys_reg_desc *r;
2072         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2073
2074         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2075                 return demux_c15_set(reg->id, uaddr);
2076
2077         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2078                 return -ENOENT;
2079
2080         r = index_to_sys_reg_desc(vcpu, reg->id);
2081         if (!r)
2082                 return set_invariant_sys_reg(reg->id, uaddr);
2083
2084         if (r->set_user)
2085                 return (r->set_user)(vcpu, r, reg, uaddr);
2086
2087         return reg_from_user(&vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
2088 }
2089
2090 static unsigned int num_demux_regs(void)
2091 {
2092         unsigned int i, count = 0;
2093
2094         for (i = 0; i < CSSELR_MAX; i++)
2095                 if (is_valid_cache(i))
2096                         count++;
2097
2098         return count;
2099 }
2100
2101 static int write_demux_regids(u64 __user *uindices)
2102 {
2103         u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
2104         unsigned int i;
2105
2106         val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2107         for (i = 0; i < CSSELR_MAX; i++) {
2108                 if (!is_valid_cache(i))
2109                         continue;
2110                 if (put_user(val | i, uindices))
2111                         return -EFAULT;
2112                 uindices++;
2113         }
2114         return 0;
2115 }
2116
2117 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2118 {
2119         return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2120                 KVM_REG_ARM64_SYSREG |
2121                 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2122                 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2123                 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2124                 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2125                 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2126 }
2127
2128 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2129 {
2130         if (!*uind)
2131                 return true;
2132
2133         if (put_user(sys_reg_to_index(reg), *uind))
2134                 return false;
2135
2136         (*uind)++;
2137         return true;
2138 }
2139
2140 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
2141 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2142 {
2143         const struct sys_reg_desc *i1, *i2, *end1, *end2;
2144         unsigned int total = 0;
2145         size_t num;
2146
2147         /* We check for duplicates here, to allow arch-specific overrides. */
2148         i1 = get_target_table(vcpu->arch.target, true, &num);
2149         end1 = i1 + num;
2150         i2 = sys_reg_descs;
2151         end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2152
2153         BUG_ON(i1 == end1 || i2 == end2);
2154
2155         /* Walk carefully, as both tables may refer to the same register. */
2156         while (i1 || i2) {
2157                 int cmp = cmp_sys_reg(i1, i2);
2158                 /* target-specific overrides generic entry. */
2159                 if (cmp <= 0) {
2160                         /* Ignore registers we trap but don't save. */
2161                         if (i1->reg) {
2162                                 if (!copy_reg_to_user(i1, &uind))
2163                                         return -EFAULT;
2164                                 total++;
2165                         }
2166                 } else {
2167                         /* Ignore registers we trap but don't save. */
2168                         if (i2->reg) {
2169                                 if (!copy_reg_to_user(i2, &uind))
2170                                         return -EFAULT;
2171                                 total++;
2172                         }
2173                 }
2174
2175                 if (cmp <= 0 && ++i1 == end1)
2176                         i1 = NULL;
2177                 if (cmp >= 0 && ++i2 == end2)
2178                         i2 = NULL;
2179         }
2180         return total;
2181 }
2182
2183 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2184 {
2185         return ARRAY_SIZE(invariant_sys_regs)
2186                 + num_demux_regs()
2187                 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2188 }
2189
2190 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2191 {
2192         unsigned int i;
2193         int err;
2194
2195         /* Then give them all the invariant registers' indices. */
2196         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2197                 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2198                         return -EFAULT;
2199                 uindices++;
2200         }
2201
2202         err = walk_sys_regs(vcpu, uindices);
2203         if (err < 0)
2204                 return err;
2205         uindices += err;
2206
2207         return write_demux_regids(uindices);
2208 }
2209
2210 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n)
2211 {
2212         unsigned int i;
2213
2214         for (i = 1; i < n; i++) {
2215                 if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2216                         kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2217                         return 1;
2218                 }
2219         }
2220
2221         return 0;
2222 }
2223
2224 void kvm_sys_reg_table_init(void)
2225 {
2226         unsigned int i;
2227         struct sys_reg_desc clidr;
2228
2229         /* Make sure tables are unique and in order. */
2230         BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs)));
2231         BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs)));
2232         BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs)));
2233         BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
2234         BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs)));
2235         BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)));
2236
2237         /* We abuse the reset function to overwrite the table itself. */
2238         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2239                 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2240
2241         /*
2242          * CLIDR format is awkward, so clean it up.  See ARM B4.1.20:
2243          *
2244          *   If software reads the Cache Type fields from Ctype1
2245          *   upwards, once it has seen a value of 0b000, no caches
2246          *   exist at further-out levels of the hierarchy. So, for
2247          *   example, if Ctype3 is the first Cache Type field with a
2248          *   value of 0b000, the values of Ctype4 to Ctype7 must be
2249          *   ignored.
2250          */
2251         get_clidr_el1(NULL, &clidr); /* Ugly... */
2252         cache_levels = clidr.val;
2253         for (i = 0; i < 7; i++)
2254                 if (((cache_levels >> (i*3)) & 7) == 0)
2255                         break;
2256         /* Clear all higher bits. */
2257         cache_levels &= (1 << (i*3))-1;
2258 }
2259
2260 /**
2261  * kvm_reset_sys_regs - sets system registers to reset value
2262  * @vcpu: The VCPU pointer
2263  *
2264  * This function finds the right table above and sets the registers on the
2265  * virtual CPU struct to their architecturally defined reset values.
2266  */
2267 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
2268 {
2269         size_t num;
2270         const struct sys_reg_desc *table;
2271
2272         /* Catch someone adding a register without putting in reset entry. */
2273         memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs));
2274
2275         /* Generic chip reset first (so target could override). */
2276         reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2277
2278         table = get_target_table(vcpu->arch.target, true, &num);
2279         reset_sys_reg_descs(vcpu, table, num);
2280
2281         for (num = 1; num < NR_SYS_REGS; num++)
2282                 if (vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
2283                         panic("Didn't reset vcpu_sys_reg(%zi)", num);
2284 }