arch/arm64/kvm/hyp/switch.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 - ARM Ltd
   4  * Author: Marc Zyngier <marc.zyngier@arm.com>
   5  */
   6
   7 #include <linux/arm-smccc.h>
   8 #include <linux/kvm_host.h>
   9 #include <linux/types.h>
  10 #include <linux/jump_label.h>
  11 #include <uapi/linux/psci.h>
  12
  13 #include <kvm/arm_psci.h>
  14
  15 #include <asm/barrier.h>
  16 #include <asm/cpufeature.h>
  17 #include <asm/kprobes.h>
  18 #include <asm/kvm_asm.h>
  19 #include <asm/kvm_emulate.h>
  20 #include <asm/kvm_hyp.h>
  21 #include <asm/kvm_mmu.h>
  22 #include <asm/fpsimd.h>
  23 #include <asm/debug-monitors.h>
  24 #include <asm/processor.h>
  25 #include <asm/thread_info.h>
  26
  27 /* Check whether the FP regs were dirtied while in the host-side run loop: */
  28 static bool __hyp_text update_fp_enabled(struct kvm_vcpu *vcpu)
  29 {
  30         /*
  31          * When the system doesn't support FP/SIMD, we cannot rely on
  32          * the _TIF_FOREIGN_FPSTATE flag. However, we always inject an
  33          * abort on the very first access to FP and thus we should never
  34          * see KVM_ARM64_FP_ENABLED. For added safety, make sure we always
  35          * trap the accesses.
  36          */
  37         if (!system_supports_fpsimd() ||
  38             vcpu->arch.host_thread_info->flags & _TIF_FOREIGN_FPSTATE)
  39                 vcpu->arch.flags &= ~(KVM_ARM64_FP_ENABLED |
  40                                       KVM_ARM64_FP_HOST);
  41
  42         return !!(vcpu->arch.flags & KVM_ARM64_FP_ENABLED);
  43 }
  44
  45 /* Save the 32-bit only FPSIMD system register state */
  46 static void __hyp_text __fpsimd_save_fpexc32(struct kvm_vcpu *vcpu)
  47 {
  48         if (!vcpu_el1_is_32bit(vcpu))
  49                 return;
  50
  51         vcpu->arch.ctxt.sys_regs[FPEXC32_EL2] = read_sysreg(fpexc32_el2);
  52 }
  53
  54 static void __hyp_text __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
  55 {
  56         /*
  57          * We are about to set CPTR_EL2.TFP to trap all floating point
  58          * register accesses to EL2, however, the ARM ARM clearly states that
  59          * traps are only taken to EL2 if the operation would not otherwise
  60          * trap to EL1.  Therefore, always make sure that for 32-bit guests,
  61          * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
  62          * If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to
  63          * it will cause an exception.
  64          */
  65         if (vcpu_el1_is_32bit(vcpu) && system_supports_fpsimd()) {
  66                 write_sysreg(1 << 30, fpexc32_el2);
  67                 isb();
  68         }
  69 }
  70
  71 static void __hyp_text __activate_traps_common(struct kvm_vcpu *vcpu)
  72 {
  73         /* Trap on AArch32 cp15 c15 (impdef sysregs) accesses (EL1 or EL0) */
  74         write_sysreg(1 << 15, hstr_el2);
  75
  76         /*
  77          * Make sure we trap PMU access from EL0 to EL2. Also sanitize
  78          * PMSELR_EL0 to make sure it never contains the cycle
  79          * counter, which could make a PMXEVCNTR_EL0 access UNDEF at
  80          * EL1 instead of being trapped to EL2.
  81          */
  82         write_sysreg(0, pmselr_el0);
  83         write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
  84         write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
  85 }
  86
  87 static void __hyp_text __deactivate_traps_common(void)
  88 {
  89         write_sysreg(0, hstr_el2);
  90         write_sysreg(0, pmuserenr_el0);
  91 }
  92
  93 static void activate_traps_vhe(struct kvm_vcpu *vcpu)
  94 {
  95         u64 val;
  96
  97         val = read_sysreg(cpacr_el1);
  98         val |= CPACR_EL1_TTA;
  99         val &= ~CPACR_EL1_ZEN;
 100         if (update_fp_enabled(vcpu)) {
 101                 if (vcpu_has_sve(vcpu))
 102                         val |= CPACR_EL1_ZEN;
 103         } else {
 104                 val &= ~CPACR_EL1_FPEN;
 105                 __activate_traps_fpsimd32(vcpu);
 106         }
 107
 108         write_sysreg(val, cpacr_el1);
 109
 110         write_sysreg(kvm_get_hyp_vector(), vbar_el1);
 111 }
 112 NOKPROBE_SYMBOL(activate_traps_vhe);
 113
 114 static void __hyp_text __activate_traps_nvhe(struct kvm_vcpu *vcpu)
 115 {
 116         u64 val;
 117
 118         __activate_traps_common(vcpu);
 119
 120         val = CPTR_EL2_DEFAULT;
 121         val |= CPTR_EL2_TTA | CPTR_EL2_TZ;
 122         if (!update_fp_enabled(vcpu)) {
 123                 val |= CPTR_EL2_TFP;
 124                 __activate_traps_fpsimd32(vcpu);
 125         }
 126
 127         write_sysreg(val, cptr_el2);
 128
 129         if (cpus_have_const_cap(ARM64_WORKAROUND_SPECULATIVE_AT_NVHE)) {
 130                 struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt;
 131
 132                 isb();
 133                 /*
 134                  * At this stage, and thanks to the above isb(), S2 is
 135                  * configured and enabled. We can now restore the guest's S1
 136                  * configuration: SCTLR, and only then TCR.
 137                  */
 138                 write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1],     SYS_SCTLR);
 139                 isb();
 140                 write_sysreg_el1(ctxt->sys_regs[TCR_EL1],       SYS_TCR);
 141         }
 142 }
 143
 144 static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu)
 145 {
 146         u64 hcr = vcpu->arch.hcr_el2;
 147
 148         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM))
 149                 hcr |= HCR_TVM;
 150
 151         write_sysreg(hcr, hcr_el2);
 152
 153         if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE))
 154                 write_sysreg_s(vcpu->arch.vsesr_el2, SYS_VSESR_EL2);
 155
 156         if (has_vhe())
 157                 activate_traps_vhe(vcpu);
 158         else
 159                 __activate_traps_nvhe(vcpu);
 160 }
 161
 162 static void deactivate_traps_vhe(void)
 163 {
 164         extern char vectors[];  /* kernel exception vectors */
 165         write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
 166
 167         /*
 168          * ARM errata 1165522 and 1530923 require the actual execution of the
 169          * above before we can switch to the EL2/EL0 translation regime used by
 170          * the host.
 171          */
 172         asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT_VHE));
 173
 174         write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1);
 175         write_sysreg(vectors, vbar_el1);
 176 }
 177 NOKPROBE_SYMBOL(deactivate_traps_vhe);
 178
 179 static void __hyp_text __deactivate_traps_nvhe(void)
 180 {
 181         u64 mdcr_el2 = read_sysreg(mdcr_el2);
 182
 183         if (cpus_have_const_cap(ARM64_WORKAROUND_SPECULATIVE_AT_NVHE)) {
 184                 u64 val;
 185
 186                 /*
 187                  * Set the TCR and SCTLR registers in the exact opposite
 188                  * sequence as __activate_traps_nvhe (first prevent walks,
 189                  * then force the MMU on). A generous sprinkling of isb()
 190                  * ensure that things happen in this exact order.
 191                  */
 192                 val = read_sysreg_el1(SYS_TCR);
 193                 write_sysreg_el1(val | TCR_EPD1_MASK | TCR_EPD0_MASK, SYS_TCR);
 194                 isb();
 195                 val = read_sysreg_el1(SYS_SCTLR);
 196                 write_sysreg_el1(val | SCTLR_ELx_M, SYS_SCTLR);
 197                 isb();
 198         }
 199
 200         __deactivate_traps_common();
 201
 202         mdcr_el2 &= MDCR_EL2_HPMN_MASK;
 203         mdcr_el2 |= MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT;
 204
 205         write_sysreg(mdcr_el2, mdcr_el2);
 206         write_sysreg(HCR_HOST_NVHE_FLAGS, hcr_el2);
 207         write_sysreg(CPTR_EL2_DEFAULT, cptr_el2);
 208 }
 209
 210 static void __hyp_text __deactivate_traps(struct kvm_vcpu *vcpu)
 211 {
 212         /*
 213          * If we pended a virtual abort, preserve it until it gets
 214          * cleared. See D1.14.3 (Virtual Interrupts) for details, but
 215          * the crucial bit is "On taking a vSError interrupt,
 216          * HCR_EL2.VSE is cleared to 0."
 217          */
 218         if (vcpu->arch.hcr_el2 & HCR_VSE) {
 219                 vcpu->arch.hcr_el2 &= ~HCR_VSE;
 220                 vcpu->arch.hcr_el2 |= read_sysreg(hcr_el2) & HCR_VSE;
 221         }
 222
 223         if (has_vhe())
 224                 deactivate_traps_vhe();
 225         else
 226                 __deactivate_traps_nvhe();
 227 }
 228
 229 void activate_traps_vhe_load(struct kvm_vcpu *vcpu)
 230 {
 231         __activate_traps_common(vcpu);
 232 }
 233
 234 void deactivate_traps_vhe_put(void)
 235 {
 236         u64 mdcr_el2 = read_sysreg(mdcr_el2);
 237
 238         mdcr_el2 &= MDCR_EL2_HPMN_MASK |
 239                     MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT |
 240                     MDCR_EL2_TPMS;
 241
 242         write_sysreg(mdcr_el2, mdcr_el2);
 243
 244         __deactivate_traps_common();
 245 }
 246
 247 static void __hyp_text __activate_vm(struct kvm *kvm)
 248 {
 249         __load_guest_stage2(kvm);
 250 }
 251
 252 static void __hyp_text __deactivate_vm(struct kvm_vcpu *vcpu)
 253 {
 254         write_sysreg(0, vttbr_el2);
 255 }
 256
 257 /* Save VGICv3 state on non-VHE systems */
 258 static void __hyp_text __hyp_vgic_save_state(struct kvm_vcpu *vcpu)
 259 {
 260         if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
 261                 __vgic_v3_save_state(vcpu);
 262                 __vgic_v3_deactivate_traps(vcpu);
 263         }
 264 }
 265
 266 /* Restore VGICv3 state on non_VEH systems */
 267 static void __hyp_text __hyp_vgic_restore_state(struct kvm_vcpu *vcpu)
 268 {
 269         if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
 270                 __vgic_v3_activate_traps(vcpu);
 271                 __vgic_v3_restore_state(vcpu);
 272         }
 273 }
 274
 275 static bool __hyp_text __translate_far_to_hpfar(u64 far, u64 *hpfar)
 276 {
 277         u64 par, tmp;
 278
 279         /*
 280          * Resolve the IPA the hard way using the guest VA.
 281          *
 282          * Stage-1 translation already validated the memory access
 283          * rights. As such, we can use the EL1 translation regime, and
 284          * don't have to distinguish between EL0 and EL1 access.
 285          *
 286          * We do need to save/restore PAR_EL1 though, as we haven't
 287          * saved the guest context yet, and we may return early...
 288          */
 289         par = read_sysreg(par_el1);
 290         asm volatile("at s1e1r, %0" : : "r" (far));
 291         isb();
 292
 293         tmp = read_sysreg(par_el1);
 294         write_sysreg(par, par_el1);
 295
 296         if (unlikely(tmp & SYS_PAR_EL1_F))
 297                 return false; /* Translation failed, back to guest */
 298
 299         /* Convert PAR to HPFAR format */
 300         *hpfar = PAR_TO_HPFAR(tmp);
 301         return true;
 302 }
 303
 304 static bool __hyp_text __populate_fault_info(struct kvm_vcpu *vcpu)
 305 {
 306         u8 ec;
 307         u64 esr;
 308         u64 hpfar, far;
 309
 310         esr = vcpu->arch.fault.esr_el2;
 311         ec = ESR_ELx_EC(esr);
 312
 313         if (ec != ESR_ELx_EC_DABT_LOW && ec != ESR_ELx_EC_IABT_LOW)
 314                 return true;
 315
 316         far = read_sysreg_el2(SYS_FAR);
 317
 318         /*
 319          * The HPFAR can be invalid if the stage 2 fault did not
 320          * happen during a stage 1 page table walk (the ESR_EL2.S1PTW
 321          * bit is clear) and one of the two following cases are true:
 322          *   1. The fault was due to a permission fault
 323          *   2. The processor carries errata 834220
 324          *
 325          * Therefore, for all non S1PTW faults where we either have a
 326          * permission fault or the errata workaround is enabled, we
 327          * resolve the IPA using the AT instruction.
 328          */
 329         if (!(esr & ESR_ELx_S1PTW) &&
 330             (cpus_have_const_cap(ARM64_WORKAROUND_834220) ||
 331              (esr & ESR_ELx_FSC_TYPE) == FSC_PERM)) {
 332                 if (!__translate_far_to_hpfar(far, &hpfar))
 333                         return false;
 334         } else {
 335                 hpfar = read_sysreg(hpfar_el2);
 336         }
 337
 338         vcpu->arch.fault.far_el2 = far;
 339         vcpu->arch.fault.hpfar_el2 = hpfar;
 340         return true;
 341 }
 342
 343 /* Check for an FPSIMD/SVE trap and handle as appropriate */
 344 static bool __hyp_text __hyp_handle_fpsimd(struct kvm_vcpu *vcpu)
 345 {
 346         bool vhe, sve_guest, sve_host;
 347         u8 hsr_ec;
 348
 349         if (!system_supports_fpsimd())
 350                 return false;
 351
 352         if (system_supports_sve()) {
 353                 sve_guest = vcpu_has_sve(vcpu);
 354                 sve_host = vcpu->arch.flags & KVM_ARM64_HOST_SVE_IN_USE;
 355                 vhe = true;
 356         } else {
 357                 sve_guest = false;
 358                 sve_host = false;
 359                 vhe = has_vhe();
 360         }
 361
 362         hsr_ec = kvm_vcpu_trap_get_class(vcpu);
 363         if (hsr_ec != ESR_ELx_EC_FP_ASIMD &&
 364             hsr_ec != ESR_ELx_EC_SVE)
 365                 return false;
 366
 367         /* Don't handle SVE traps for non-SVE vcpus here: */
 368         if (!sve_guest)
 369                 if (hsr_ec != ESR_ELx_EC_FP_ASIMD)
 370                         return false;
 371
 372         /* Valid trap.  Switch the context: */
 373
 374         if (vhe) {
 375                 u64 reg = read_sysreg(cpacr_el1) | CPACR_EL1_FPEN;
 376
 377                 if (sve_guest)
 378                         reg |= CPACR_EL1_ZEN;
 379
 380                 write_sysreg(reg, cpacr_el1);
 381         } else {
 382                 write_sysreg(read_sysreg(cptr_el2) & ~(u64)CPTR_EL2_TFP,
 383                              cptr_el2);
 384         }
 385
 386         isb();
 387
 388         if (vcpu->arch.flags & KVM_ARM64_FP_HOST) {
 389                 /*
 390                  * In the SVE case, VHE is assumed: it is enforced by
 391                  * Kconfig and kvm_arch_init().
 392                  */
 393                 if (sve_host) {
 394                         struct thread_struct *thread = container_of(
 395                                 vcpu->arch.host_fpsimd_state,
 396                                 struct thread_struct, uw.fpsimd_state);
 397
 398                         sve_save_state(sve_pffr(thread),
 399                                        &vcpu->arch.host_fpsimd_state->fpsr);
 400                 } else {
 401                         __fpsimd_save_state(vcpu->arch.host_fpsimd_state);
 402                 }
 403
 404                 vcpu->arch.flags &= ~KVM_ARM64_FP_HOST;
 405         }
 406
 407         if (sve_guest) {
 408                 sve_load_state(vcpu_sve_pffr(vcpu),
 409                                &vcpu->arch.ctxt.gp_regs.fp_regs.fpsr,
 410                                sve_vq_from_vl(vcpu->arch.sve_max_vl) - 1);
 411                 write_sysreg_s(vcpu->arch.ctxt.sys_regs[ZCR_EL1], SYS_ZCR_EL12);
 412         } else {
 413                 __fpsimd_restore_state(&vcpu->arch.ctxt.gp_regs.fp_regs);
 414         }
 415
 416         /* Skip restoring fpexc32 for AArch64 guests */
 417         if (!(read_sysreg(hcr_el2) & HCR_RW))
 418                 write_sysreg(vcpu->arch.ctxt.sys_regs[FPEXC32_EL2],
 419                              fpexc32_el2);
 420
 421         vcpu->arch.flags |= KVM_ARM64_FP_ENABLED;
 422
 423         return true;
 424 }
 425
 426 static bool __hyp_text handle_tx2_tvm(struct kvm_vcpu *vcpu)
 427 {
 428         u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_hsr(vcpu));
 429         int rt = kvm_vcpu_sys_get_rt(vcpu);
 430         u64 val = vcpu_get_reg(vcpu, rt);
 431
 432         /*
 433          * The normal sysreg handling code expects to see the traps,
 434          * let's not do anything here.
 435          */
 436         if (vcpu->arch.hcr_el2 & HCR_TVM)
 437                 return false;
 438
 439         switch (sysreg) {
 440         case SYS_SCTLR_EL1:
 441                 write_sysreg_el1(val, SYS_SCTLR);
 442                 break;
 443         case SYS_TTBR0_EL1:
 444                 write_sysreg_el1(val, SYS_TTBR0);
 445                 break;
 446         case SYS_TTBR1_EL1:
 447                 write_sysreg_el1(val, SYS_TTBR1);
 448                 break;
 449         case SYS_TCR_EL1:
 450                 write_sysreg_el1(val, SYS_TCR);
 451                 break;
 452         case SYS_ESR_EL1:
 453                 write_sysreg_el1(val, SYS_ESR);
 454                 break;
 455         case SYS_FAR_EL1:
 456                 write_sysreg_el1(val, SYS_FAR);
 457                 break;
 458         case SYS_AFSR0_EL1:
 459                 write_sysreg_el1(val, SYS_AFSR0);
 460                 break;
 461         case SYS_AFSR1_EL1:
 462                 write_sysreg_el1(val, SYS_AFSR1);
 463                 break;
 464         case SYS_MAIR_EL1:
 465                 write_sysreg_el1(val, SYS_MAIR);
 466                 break;
 467         case SYS_AMAIR_EL1:
 468                 write_sysreg_el1(val, SYS_AMAIR);
 469                 break;
 470         case SYS_CONTEXTIDR_EL1:
 471                 write_sysreg_el1(val, SYS_CONTEXTIDR);
 472                 break;
 473         default:
 474                 return false;
 475         }
 476
 477         __kvm_skip_instr(vcpu);
 478         return true;
 479 }
 480
 481 /*
 482  * Return true when we were able to fixup the guest exit and should return to
 483  * the guest, false when we should restore the host state and return to the
 484  * main run loop.
 485  */
 486 static bool __hyp_text fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
 487 {
 488         if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ)
 489                 vcpu->arch.fault.esr_el2 = read_sysreg_el2(SYS_ESR);
 490
 491         /*
 492          * We're using the raw exception code in order to only process
 493          * the trap if no SError is pending. We will come back to the
 494          * same PC once the SError has been injected, and replay the
 495          * trapping instruction.
 496          */
 497         if (*exit_code != ARM_EXCEPTION_TRAP)
 498                 goto exit;
 499
 500         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM) &&
 501             kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_SYS64 &&
 502             handle_tx2_tvm(vcpu))
 503                 return true;
 504
 505         /*
 506          * We trap the first access to the FP/SIMD to save the host context
 507          * and restore the guest context lazily.
 508          * If FP/SIMD is not implemented, handle the trap and inject an
 509          * undefined instruction exception to the guest.
 510          * Similarly for trapped SVE accesses.
 511          */
 512         if (__hyp_handle_fpsimd(vcpu))
 513                 return true;
 514
 515         if (!__populate_fault_info(vcpu))
 516                 return true;
 517
 518         if (static_branch_unlikely(&vgic_v2_cpuif_trap)) {
 519                 bool valid;
 520
 521                 valid = kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_DABT_LOW &&
 522                         kvm_vcpu_trap_get_fault_type(vcpu) == FSC_FAULT &&
 523                         kvm_vcpu_dabt_isvalid(vcpu) &&
 524                         !kvm_vcpu_dabt_isextabt(vcpu) &&
 525                         !kvm_vcpu_dabt_iss1tw(vcpu);
 526
 527                 if (valid) {
 528                         int ret = __vgic_v2_perform_cpuif_access(vcpu);
 529
 530                         if (ret == 1)
 531                                 return true;
 532
 533                         /* Promote an illegal access to an SError.*/
 534                         if (ret == -1)
 535                                 *exit_code = ARM_EXCEPTION_EL1_SERROR;
 536
 537                         goto exit;
 538                 }
 539         }
 540
 541         if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
 542             (kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_SYS64 ||
 543              kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_CP15_32)) {
 544                 int ret = __vgic_v3_perform_cpuif_access(vcpu);
 545
 546                 if (ret == 1)
 547                         return true;
 548         }
 549
 550 exit:
 551         /* Return to the host kernel and handle the exit */
 552         return false;
 553 }
 554
 555 static inline bool __hyp_text __needs_ssbd_off(struct kvm_vcpu *vcpu)
 556 {
 557         if (!cpus_have_const_cap(ARM64_SSBD))
 558                 return false;
 559
 560         return !(vcpu->arch.workaround_flags & VCPU_WORKAROUND_2_FLAG);
 561 }
 562
 563 static void __hyp_text __set_guest_arch_workaround_state(struct kvm_vcpu *vcpu)
 564 {
 565 #ifdef CONFIG_ARM64_SSBD
 566         /*
 567          * The host runs with the workaround always present. If the
 568          * guest wants it disabled, so be it...
 569          */
 570         if (__needs_ssbd_off(vcpu) &&
 571             __hyp_this_cpu_read(arm64_ssbd_callback_required))
 572                 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2, 0, NULL);
 573 #endif
 574 }
 575
 576 static void __hyp_text __set_host_arch_workaround_state(struct kvm_vcpu *vcpu)
 577 {
 578 #ifdef CONFIG_ARM64_SSBD
 579         /*
 580          * If the guest has disabled the workaround, bring it back on.
 581          */
 582         if (__needs_ssbd_off(vcpu) &&
 583             __hyp_this_cpu_read(arm64_ssbd_callback_required))
 584                 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2, 1, NULL);
 585 #endif
 586 }
 587
 588 /**
 589  * Disable host events, enable guest events
 590  */
 591 static bool __hyp_text __pmu_switch_to_guest(struct kvm_cpu_context *host_ctxt)
 592 {
 593         struct kvm_host_data *host;
 594         struct kvm_pmu_events *pmu;
 595
 596         host = container_of(host_ctxt, struct kvm_host_data, host_ctxt);
 597         pmu = &host->pmu_events;
 598
 599         if (pmu->events_host)
 600                 write_sysreg(pmu->events_host, pmcntenclr_el0);
 601
 602         if (pmu->events_guest)
 603                 write_sysreg(pmu->events_guest, pmcntenset_el0);
 604
 605         return (pmu->events_host || pmu->events_guest);
 606 }
 607
 608 /**
 609  * Disable guest events, enable host events
 610  */
 611 static void __hyp_text __pmu_switch_to_host(struct kvm_cpu_context *host_ctxt)
 612 {
 613         struct kvm_host_data *host;
 614         struct kvm_pmu_events *pmu;
 615
 616         host = container_of(host_ctxt, struct kvm_host_data, host_ctxt);
 617         pmu = &host->pmu_events;
 618
 619         if (pmu->events_guest)
 620                 write_sysreg(pmu->events_guest, pmcntenclr_el0);
 621
 622         if (pmu->events_host)
 623                 write_sysreg(pmu->events_host, pmcntenset_el0);
 624 }
 625
 626 /* Switch to the guest for VHE systems running in EL2 */
 627 int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)
 628 {
 629         struct kvm_cpu_context *host_ctxt;
 630         struct kvm_cpu_context *guest_ctxt;
 631         u64 exit_code;
 632
 633         host_ctxt = vcpu->arch.host_cpu_context;
 634         host_ctxt->__hyp_running_vcpu = vcpu;
 635         guest_ctxt = &vcpu->arch.ctxt;
 636
 637         sysreg_save_host_state_vhe(host_ctxt);
 638
 639         /*
 640          * ARM erratum 1165522 requires us to configure both stage 1 and
 641          * stage 2 translation for the guest context before we clear
 642          * HCR_EL2.TGE.
 643          *
 644          * We have already configured the guest's stage 1 translation in
 645          * kvm_vcpu_load_sysregs above.  We must now call __activate_vm
 646          * before __activate_traps, because __activate_vm configures
 647          * stage 2 translation, and __activate_traps clear HCR_EL2.TGE
 648          * (among other things).
 649          */
 650         __activate_vm(vcpu->kvm);
 651         __activate_traps(vcpu);
 652
 653         sysreg_restore_guest_state_vhe(guest_ctxt);
 654         __debug_switch_to_guest(vcpu);
 655
 656         __set_guest_arch_workaround_state(vcpu);
 657
 658         do {
 659                 /* Jump in the fire! */
 660                 exit_code = __guest_enter(vcpu, host_ctxt);
 661
 662                 /* And we're baaack! */
 663         } while (fixup_guest_exit(vcpu, &exit_code));
 664
 665         __set_host_arch_workaround_state(vcpu);
 666
 667         sysreg_save_guest_state_vhe(guest_ctxt);
 668
 669         __deactivate_traps(vcpu);
 670
 671         sysreg_restore_host_state_vhe(host_ctxt);
 672
 673         if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED)
 674                 __fpsimd_save_fpexc32(vcpu);
 675
 676         __debug_switch_to_host(vcpu);
 677
 678         return exit_code;
 679 }
 680 NOKPROBE_SYMBOL(kvm_vcpu_run_vhe);
 681
 682 /* Switch to the guest for legacy non-VHE systems */
 683 int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu)
 684 {
 685         struct kvm_cpu_context *host_ctxt;
 686         struct kvm_cpu_context *guest_ctxt;
 687         bool pmu_switch_needed;
 688         u64 exit_code;
 689
 690         /*
 691          * Having IRQs masked via PMR when entering the guest means the GIC
 692          * will not signal the CPU of interrupts of lower priority, and the
 693          * only way to get out will be via guest exceptions.
 694          * Naturally, we want to avoid this.
 695          */
 696         if (system_uses_irq_prio_masking()) {
 697                 gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET);
 698                 pmr_sync();
 699         }
 700
 701         vcpu = kern_hyp_va(vcpu);
 702
 703         host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context);
 704         host_ctxt->__hyp_running_vcpu = vcpu;
 705         guest_ctxt = &vcpu->arch.ctxt;
 706
 707         pmu_switch_needed = __pmu_switch_to_guest(host_ctxt);
 708
 709         __sysreg_save_state_nvhe(host_ctxt);
 710
 711         /*
 712          * We must restore the 32-bit state before the sysregs, thanks
 713          * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72).
 714          *
 715          * Also, and in order to be able to deal with erratum #1319537 (A57)
 716          * and #1319367 (A72), we must ensure that all VM-related sysreg are
 717          * restored before we enable S2 translation.
 718          */
 719         __sysreg32_restore_state(vcpu);
 720         __sysreg_restore_state_nvhe(guest_ctxt);
 721
 722         __activate_vm(kern_hyp_va(vcpu->kvm));
 723         __activate_traps(vcpu);
 724
 725         __hyp_vgic_restore_state(vcpu);
 726         __timer_enable_traps(vcpu);
 727
 728         __debug_switch_to_guest(vcpu);
 729
 730         __set_guest_arch_workaround_state(vcpu);
 731
 732         do {
 733                 /* Jump in the fire! */
 734                 exit_code = __guest_enter(vcpu, host_ctxt);
 735
 736                 /* And we're baaack! */
 737         } while (fixup_guest_exit(vcpu, &exit_code));
 738
 739         __set_host_arch_workaround_state(vcpu);
 740
 741         __sysreg_save_state_nvhe(guest_ctxt);
 742         __sysreg32_save_state(vcpu);
 743         __timer_disable_traps(vcpu);
 744         __hyp_vgic_save_state(vcpu);
 745
 746         __deactivate_traps(vcpu);
 747         __deactivate_vm(vcpu);
 748
 749         __sysreg_restore_state_nvhe(host_ctxt);
 750
 751         if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED)
 752                 __fpsimd_save_fpexc32(vcpu);
 753
 754         /*
 755          * This must come after restoring the host sysregs, since a non-VHE
 756          * system may enable SPE here and make use of the TTBRs.
 757          */
 758         __debug_switch_to_host(vcpu);
 759
 760         if (pmu_switch_needed)
 761                 __pmu_switch_to_host(host_ctxt);
 762
 763         /* Returning to host will clear PSR.I, remask PMR if needed */
 764         if (system_uses_irq_prio_masking())
 765                 gic_write_pmr(GIC_PRIO_IRQOFF);
 766
 767         return exit_code;
 768 }
 769
 770 static const char __hyp_panic_string[] = "HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n";
 771
 772 static void __hyp_text __hyp_call_panic_nvhe(u64 spsr, u64 elr, u64 par,
 773                                              struct kvm_cpu_context *__host_ctxt)
 774 {
 775         struct kvm_vcpu *vcpu;
 776         unsigned long str_va;
 777
 778         vcpu = __host_ctxt->__hyp_running_vcpu;
 779
 780         if (read_sysreg(vttbr_el2)) {
 781                 __timer_disable_traps(vcpu);
 782                 __deactivate_traps(vcpu);
 783                 __deactivate_vm(vcpu);
 784                 __sysreg_restore_state_nvhe(__host_ctxt);
 785         }
 786
 787         /*
 788          * Force the panic string to be loaded from the literal pool,
 789          * making sure it is a kernel address and not a PC-relative
 790          * reference.
 791          */
 792         asm volatile("ldr %0, =__hyp_panic_string" : "=r" (str_va));
 793
 794         __hyp_do_panic(str_va,
 795                        spsr, elr,
 796                        read_sysreg(esr_el2), read_sysreg_el2(SYS_FAR),
 797                        read_sysreg(hpfar_el2), par, vcpu);
 798 }
 799
 800 static void __hyp_call_panic_vhe(u64 spsr, u64 elr, u64 par,
 801                                  struct kvm_cpu_context *host_ctxt)
 802 {
 803         struct kvm_vcpu *vcpu;
 804         vcpu = host_ctxt->__hyp_running_vcpu;
 805
 806         __deactivate_traps(vcpu);
 807         sysreg_restore_host_state_vhe(host_ctxt);
 808
 809         panic(__hyp_panic_string,
 810               spsr,  elr,
 811               read_sysreg_el2(SYS_ESR),   read_sysreg_el2(SYS_FAR),
 812               read_sysreg(hpfar_el2), par, vcpu);
 813 }
 814 NOKPROBE_SYMBOL(__hyp_call_panic_vhe);
 815
 816 void __hyp_text __noreturn hyp_panic(struct kvm_cpu_context *host_ctxt)
 817 {
 818         u64 spsr = read_sysreg_el2(SYS_SPSR);
 819         u64 elr = read_sysreg_el2(SYS_ELR);
 820         u64 par = read_sysreg(par_el1);
 821
 822         if (!has_vhe())
 823                 __hyp_call_panic_nvhe(spsr, elr, par, host_ctxt);
 824         else
 825                 __hyp_call_panic_vhe(spsr, elr, par, host_ctxt);
 826
 827         unreachable();
 828 }