1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
7 #include <hyp/switch.h>
8 #include <hyp/sysreg-sr.h>
10 #include <linux/arm-smccc.h>
11 #include <linux/kvm_host.h>
12 #include <linux/types.h>
13 #include <linux/jump_label.h>
14 #include <uapi/linux/psci.h>
16 #include <kvm/arm_psci.h>
18 #include <asm/barrier.h>
19 #include <asm/cpufeature.h>
20 #include <asm/kprobes.h>
21 #include <asm/kvm_asm.h>
22 #include <asm/kvm_emulate.h>
23 #include <asm/kvm_hyp.h>
24 #include <asm/kvm_mmu.h>
25 #include <asm/fpsimd.h>
26 #include <asm/debug-monitors.h>
27 #include <asm/processor.h>
29 #include <nvhe/fixed_config.h>
30 #include <nvhe/mem_protect.h>
32 /* Non-VHE specific context */
33 DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data);
34 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt);
35 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector);
37 extern void kvm_nvhe_prepare_backtrace(unsigned long fp, unsigned long pc);
39 static void __activate_traps(struct kvm_vcpu *vcpu)
43 ___activate_traps(vcpu);
44 __activate_traps_common(vcpu);
46 val = vcpu->arch.cptr_el2;
47 val |= CPTR_EL2_TTA | CPTR_EL2_TAM;
48 if (!guest_owns_fp_regs(vcpu)) {
49 val |= CPTR_EL2_TFP | CPTR_EL2_TZ;
50 __activate_traps_fpsimd32(vcpu);
52 if (cpus_have_final_cap(ARM64_SME))
55 write_sysreg(val, cptr_el2);
56 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el2);
58 if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {
59 struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt;
63 * At this stage, and thanks to the above isb(), S2 is
64 * configured and enabled. We can now restore the guest's S1
65 * configuration: SCTLR, and only then TCR.
67 write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR);
69 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR);
73 static void __deactivate_traps(struct kvm_vcpu *vcpu)
75 extern char __kvm_hyp_host_vector[];
78 ___deactivate_traps(vcpu);
80 if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {
84 * Set the TCR and SCTLR registers in the exact opposite
85 * sequence as __activate_traps (first prevent walks,
86 * then force the MMU on). A generous sprinkling of isb()
87 * ensure that things happen in this exact order.
89 val = read_sysreg_el1(SYS_TCR);
90 write_sysreg_el1(val | TCR_EPD1_MASK | TCR_EPD0_MASK, SYS_TCR);
92 val = read_sysreg_el1(SYS_SCTLR);
93 write_sysreg_el1(val | SCTLR_ELx_M, SYS_SCTLR);
97 __deactivate_traps_common(vcpu);
99 write_sysreg(this_cpu_ptr(&kvm_init_params)->hcr_el2, hcr_el2);
101 cptr = CPTR_EL2_DEFAULT;
102 if (vcpu_has_sve(vcpu) && (vcpu->arch.fp_state == FP_STATE_GUEST_OWNED))
104 if (cpus_have_final_cap(ARM64_SME))
105 cptr &= ~CPTR_EL2_TSM;
107 write_sysreg(cptr, cptr_el2);
108 write_sysreg(__kvm_hyp_host_vector, vbar_el2);
111 /* Save VGICv3 state on non-VHE systems */
112 static void __hyp_vgic_save_state(struct kvm_vcpu *vcpu)
114 if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
115 __vgic_v3_save_state(&vcpu->arch.vgic_cpu.vgic_v3);
116 __vgic_v3_deactivate_traps(&vcpu->arch.vgic_cpu.vgic_v3);
120 /* Restore VGICv3 state on non-VHE systems */
121 static void __hyp_vgic_restore_state(struct kvm_vcpu *vcpu)
123 if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
124 __vgic_v3_activate_traps(&vcpu->arch.vgic_cpu.vgic_v3);
125 __vgic_v3_restore_state(&vcpu->arch.vgic_cpu.vgic_v3);
130 * Disable host events, enable guest events
132 #ifdef CONFIG_HW_PERF_EVENTS
133 static bool __pmu_switch_to_guest(struct kvm_vcpu *vcpu)
135 struct kvm_pmu_events *pmu = &vcpu->arch.pmu.events;
137 if (pmu->events_host)
138 write_sysreg(pmu->events_host, pmcntenclr_el0);
140 if (pmu->events_guest)
141 write_sysreg(pmu->events_guest, pmcntenset_el0);
143 return (pmu->events_host || pmu->events_guest);
147 * Disable guest events, enable host events
149 static void __pmu_switch_to_host(struct kvm_vcpu *vcpu)
151 struct kvm_pmu_events *pmu = &vcpu->arch.pmu.events;
153 if (pmu->events_guest)
154 write_sysreg(pmu->events_guest, pmcntenclr_el0);
156 if (pmu->events_host)
157 write_sysreg(pmu->events_host, pmcntenset_el0);
160 #define __pmu_switch_to_guest(v) ({ false; })
161 #define __pmu_switch_to_host(v) do {} while (0)
165 * Handler for protected VM MSR, MRS or System instruction execution in AArch64.
167 * Returns true if the hypervisor has handled the exit, and control should go
168 * back to the guest, or false if it hasn't.
170 static bool kvm_handle_pvm_sys64(struct kvm_vcpu *vcpu, u64 *exit_code)
173 * Make sure we handle the exit for workarounds and ptrauth
174 * before the pKVM handling, as the latter could decide to
177 return (kvm_hyp_handle_sysreg(vcpu, exit_code) ||
178 kvm_handle_pvm_sysreg(vcpu, exit_code));
181 static const exit_handler_fn hyp_exit_handlers[] = {
182 [0 ... ESR_ELx_EC_MAX] = NULL,
183 [ESR_ELx_EC_CP15_32] = kvm_hyp_handle_cp15_32,
184 [ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg,
185 [ESR_ELx_EC_SVE] = kvm_hyp_handle_fpsimd,
186 [ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd,
187 [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low,
188 [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low,
189 [ESR_ELx_EC_PAC] = kvm_hyp_handle_ptrauth,
192 static const exit_handler_fn pvm_exit_handlers[] = {
193 [0 ... ESR_ELx_EC_MAX] = NULL,
194 [ESR_ELx_EC_SYS64] = kvm_handle_pvm_sys64,
195 [ESR_ELx_EC_SVE] = kvm_handle_pvm_restricted,
196 [ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd,
197 [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low,
198 [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low,
199 [ESR_ELx_EC_PAC] = kvm_hyp_handle_ptrauth,
202 static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu)
204 if (unlikely(kvm_vm_is_protected(kern_hyp_va(vcpu->kvm))))
205 return pvm_exit_handlers;
207 return hyp_exit_handlers;
211 * Some guests (e.g., protected VMs) are not be allowed to run in AArch32.
212 * The ARMv8 architecture does not give the hypervisor a mechanism to prevent a
213 * guest from dropping to AArch32 EL0 if implemented by the CPU. If the
214 * hypervisor spots a guest in such a state ensure it is handled, and don't
215 * trust the host to spot or fix it. The check below is based on the one in
216 * kvm_arch_vcpu_ioctl_run().
218 * Returns false if the guest ran in AArch32 when it shouldn't have, and
219 * thus should exit to the host, or true if a the guest run loop can continue.
221 static void early_exit_filter(struct kvm_vcpu *vcpu, u64 *exit_code)
223 struct kvm *kvm = kern_hyp_va(vcpu->kvm);
225 if (kvm_vm_is_protected(kvm) && vcpu_mode_is_32bit(vcpu)) {
227 * As we have caught the guest red-handed, decide that it isn't
228 * fit for purpose anymore by making the vcpu invalid. The VMM
229 * can try and fix it by re-initializing the vcpu with
230 * KVM_ARM_VCPU_INIT, however, this is likely not possible for
233 vcpu->arch.target = -1;
234 *exit_code &= BIT(ARM_EXIT_WITH_SERROR_BIT);
235 *exit_code |= ARM_EXCEPTION_IL;
239 /* Switch to the guest for legacy non-VHE systems */
240 int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
242 struct kvm_cpu_context *host_ctxt;
243 struct kvm_cpu_context *guest_ctxt;
244 struct kvm_s2_mmu *mmu;
245 bool pmu_switch_needed;
249 * Having IRQs masked via PMR when entering the guest means the GIC
250 * will not signal the CPU of interrupts of lower priority, and the
251 * only way to get out will be via guest exceptions.
252 * Naturally, we want to avoid this.
254 if (system_uses_irq_prio_masking()) {
255 gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET);
259 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
260 host_ctxt->__hyp_running_vcpu = vcpu;
261 guest_ctxt = &vcpu->arch.ctxt;
263 pmu_switch_needed = __pmu_switch_to_guest(vcpu);
265 __sysreg_save_state_nvhe(host_ctxt);
267 * We must flush and disable the SPE buffer for nVHE, as
268 * the translation regime(EL1&0) is going to be loaded with
269 * that of the guest. And we must do this before we change the
270 * translation regime to EL2 (via MDCR_EL2_E2PB == 0) and
271 * before we load guest Stage1.
273 __debug_save_host_buffers_nvhe(vcpu);
275 __kvm_adjust_pc(vcpu);
278 * We must restore the 32-bit state before the sysregs, thanks
279 * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72).
281 * Also, and in order to be able to deal with erratum #1319537 (A57)
282 * and #1319367 (A72), we must ensure that all VM-related sysreg are
283 * restored before we enable S2 translation.
285 __sysreg32_restore_state(vcpu);
286 __sysreg_restore_state_nvhe(guest_ctxt);
288 mmu = kern_hyp_va(vcpu->arch.hw_mmu);
289 __load_stage2(mmu, kern_hyp_va(mmu->arch));
290 __activate_traps(vcpu);
292 __hyp_vgic_restore_state(vcpu);
293 __timer_enable_traps(vcpu);
295 __debug_switch_to_guest(vcpu);
298 /* Jump in the fire! */
299 exit_code = __guest_enter(vcpu);
301 /* And we're baaack! */
302 } while (fixup_guest_exit(vcpu, &exit_code));
304 __sysreg_save_state_nvhe(guest_ctxt);
305 __sysreg32_save_state(vcpu);
306 __timer_disable_traps(vcpu);
307 __hyp_vgic_save_state(vcpu);
309 __deactivate_traps(vcpu);
310 __load_host_stage2();
312 __sysreg_restore_state_nvhe(host_ctxt);
314 if (vcpu->arch.fp_state == FP_STATE_GUEST_OWNED)
315 __fpsimd_save_fpexc32(vcpu);
317 __debug_switch_to_host(vcpu);
319 * This must come after restoring the host sysregs, since a non-VHE
320 * system may enable SPE here and make use of the TTBRs.
322 __debug_restore_host_buffers_nvhe(vcpu);
324 if (pmu_switch_needed)
325 __pmu_switch_to_host(vcpu);
327 /* Returning to host will clear PSR.I, remask PMR if needed */
328 if (system_uses_irq_prio_masking())
329 gic_write_pmr(GIC_PRIO_IRQOFF);
331 host_ctxt->__hyp_running_vcpu = NULL;
336 asmlinkage void __noreturn hyp_panic(void)
338 u64 spsr = read_sysreg_el2(SYS_SPSR);
339 u64 elr = read_sysreg_el2(SYS_ELR);
340 u64 par = read_sysreg_par();
341 struct kvm_cpu_context *host_ctxt;
342 struct kvm_vcpu *vcpu;
344 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
345 vcpu = host_ctxt->__hyp_running_vcpu;
348 __timer_disable_traps(vcpu);
349 __deactivate_traps(vcpu);
350 __load_host_stage2();
351 __sysreg_restore_state_nvhe(host_ctxt);
354 /* Prepare to dump kvm nvhe hyp stacktrace */
355 kvm_nvhe_prepare_backtrace((unsigned long)__builtin_frame_address(0),
358 __hyp_do_panic(host_ctxt, spsr, elr, par);
362 asmlinkage void __noreturn hyp_panic_bad_stack(void)
367 asmlinkage void kvm_unexpected_el2_exception(void)
369 __kvm_unexpected_el2_exception();