arch/arm64/kvm/hyp/include/hyp/switch.h

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 - ARM Ltd
   4  * Author: Marc Zyngier <marc.zyngier@arm.com>
   5  */
   6
   7 #ifndef __ARM64_KVM_HYP_SWITCH_H__
   8 #define __ARM64_KVM_HYP_SWITCH_H__
   9
  10 #include <hyp/adjust_pc.h>
  11 #include <hyp/fault.h>
  12
  13 #include <linux/arm-smccc.h>
  14 #include <linux/kvm_host.h>
  15 #include <linux/types.h>
  16 #include <linux/jump_label.h>
  17 #include <uapi/linux/psci.h>
  18
  19 #include <kvm/arm_psci.h>
  20
  21 #include <asm/barrier.h>
  22 #include <asm/cpufeature.h>
  23 #include <asm/extable.h>
  24 #include <asm/kprobes.h>
  25 #include <asm/kvm_asm.h>
  26 #include <asm/kvm_emulate.h>
  27 #include <asm/kvm_hyp.h>
  28 #include <asm/kvm_mmu.h>
  29 #include <asm/kvm_nested.h>
  30 #include <asm/fpsimd.h>
  31 #include <asm/debug-monitors.h>
  32 #include <asm/processor.h>
  33
  34 struct kvm_exception_table_entry {
  35         int insn, fixup;
  36 };
  37
  38 extern struct kvm_exception_table_entry __start___kvm_ex_table;
  39 extern struct kvm_exception_table_entry __stop___kvm_ex_table;
  40
  41 /* Check whether the FP regs are owned by the guest */
  42 static inline bool guest_owns_fp_regs(struct kvm_vcpu *vcpu)
  43 {
  44         return vcpu->arch.fp_state == FP_STATE_GUEST_OWNED;
  45 }
  46
  47 /* Save the 32-bit only FPSIMD system register state */
  48 static inline void __fpsimd_save_fpexc32(struct kvm_vcpu *vcpu)
  49 {
  50         if (!vcpu_el1_is_32bit(vcpu))
  51                 return;
  52
  53         __vcpu_sys_reg(vcpu, FPEXC32_EL2) = read_sysreg(fpexc32_el2);
  54 }
  55
  56 static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
  57 {
  58         /*
  59          * We are about to set CPTR_EL2.TFP to trap all floating point
  60          * register accesses to EL2, however, the ARM ARM clearly states that
  61          * traps are only taken to EL2 if the operation would not otherwise
  62          * trap to EL1.  Therefore, always make sure that for 32-bit guests,
  63          * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
  64          * If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to
  65          * it will cause an exception.
  66          */
  67         if (vcpu_el1_is_32bit(vcpu) && system_supports_fpsimd()) {
  68                 write_sysreg(1 << 30, fpexc32_el2);
  69                 isb();
  70         }
  71 }
  72
  73 static inline bool __hfgxtr_traps_required(void)
  74 {
  75         if (cpus_have_final_cap(ARM64_SME))
  76                 return true;
  77
  78         if (cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38))
  79                 return true;
  80
  81         return false;
  82 }
  83
  84 static inline void __activate_traps_hfgxtr(void)
  85 {
  86         u64 r_clr = 0, w_clr = 0, r_set = 0, w_set = 0, tmp;
  87
  88         if (cpus_have_final_cap(ARM64_SME)) {
  89                 tmp = HFGxTR_EL2_nSMPRI_EL1_MASK | HFGxTR_EL2_nTPIDR2_EL0_MASK;
  90
  91                 r_clr |= tmp;
  92                 w_clr |= tmp;
  93         }
  94
  95         /*
  96          * Trap guest writes to TCR_EL1 to prevent it from enabling HA or HD.
  97          */
  98         if (cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38))
  99                 w_set |= HFGxTR_EL2_TCR_EL1_MASK;
 100
 101         sysreg_clear_set_s(SYS_HFGRTR_EL2, r_clr, r_set);
 102         sysreg_clear_set_s(SYS_HFGWTR_EL2, w_clr, w_set);
 103 }
 104
 105 static inline void __deactivate_traps_hfgxtr(void)
 106 {
 107         u64 r_clr = 0, w_clr = 0, r_set = 0, w_set = 0, tmp;
 108
 109         if (cpus_have_final_cap(ARM64_SME)) {
 110                 tmp = HFGxTR_EL2_nSMPRI_EL1_MASK | HFGxTR_EL2_nTPIDR2_EL0_MASK;
 111
 112                 r_set |= tmp;
 113                 w_set |= tmp;
 114         }
 115
 116         if (cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38))
 117                 w_clr |= HFGxTR_EL2_TCR_EL1_MASK;
 118
 119         sysreg_clear_set_s(SYS_HFGRTR_EL2, r_clr, r_set);
 120         sysreg_clear_set_s(SYS_HFGWTR_EL2, w_clr, w_set);
 121 }
 122
 123 static inline void __activate_traps_common(struct kvm_vcpu *vcpu)
 124 {
 125         /* Trap on AArch32 cp15 c15 (impdef sysregs) accesses (EL1 or EL0) */
 126         write_sysreg(1 << 15, hstr_el2);
 127
 128         /*
 129          * Make sure we trap PMU access from EL0 to EL2. Also sanitize
 130          * PMSELR_EL0 to make sure it never contains the cycle
 131          * counter, which could make a PMXEVCNTR_EL0 access UNDEF at
 132          * EL1 instead of being trapped to EL2.
 133          */
 134         if (kvm_arm_support_pmu_v3()) {
 135                 struct kvm_cpu_context *hctxt;
 136
 137                 write_sysreg(0, pmselr_el0);
 138
 139                 hctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
 140                 ctxt_sys_reg(hctxt, PMUSERENR_EL0) = read_sysreg(pmuserenr_el0);
 141                 write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
 142                 vcpu_set_flag(vcpu, PMUSERENR_ON_CPU);
 143         }
 144
 145         vcpu->arch.mdcr_el2_host = read_sysreg(mdcr_el2);
 146         write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
 147
 148         if (__hfgxtr_traps_required())
 149                 __activate_traps_hfgxtr();
 150 }
 151
 152 static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu)
 153 {
 154         write_sysreg(vcpu->arch.mdcr_el2_host, mdcr_el2);
 155
 156         write_sysreg(0, hstr_el2);
 157         if (kvm_arm_support_pmu_v3()) {
 158                 struct kvm_cpu_context *hctxt;
 159
 160                 hctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
 161                 write_sysreg(ctxt_sys_reg(hctxt, PMUSERENR_EL0), pmuserenr_el0);
 162                 vcpu_clear_flag(vcpu, PMUSERENR_ON_CPU);
 163         }
 164
 165         if (__hfgxtr_traps_required())
 166                 __deactivate_traps_hfgxtr();
 167 }
 168
 169 static inline void ___activate_traps(struct kvm_vcpu *vcpu)
 170 {
 171         u64 hcr = vcpu->arch.hcr_el2;
 172
 173         if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM))
 174                 hcr |= HCR_TVM;
 175
 176         write_sysreg(hcr, hcr_el2);
 177
 178         if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE))
 179                 write_sysreg_s(vcpu->arch.vsesr_el2, SYS_VSESR_EL2);
 180 }
 181
 182 static inline void ___deactivate_traps(struct kvm_vcpu *vcpu)
 183 {
 184         /*
 185          * If we pended a virtual abort, preserve it until it gets
 186          * cleared. See D1.14.3 (Virtual Interrupts) for details, but
 187          * the crucial bit is "On taking a vSError interrupt,
 188          * HCR_EL2.VSE is cleared to 0."
 189          */
 190         if (vcpu->arch.hcr_el2 & HCR_VSE) {
 191                 vcpu->arch.hcr_el2 &= ~HCR_VSE;
 192                 vcpu->arch.hcr_el2 |= read_sysreg(hcr_el2) & HCR_VSE;
 193         }
 194 }
 195
 196 static inline bool __populate_fault_info(struct kvm_vcpu *vcpu)
 197 {
 198         return __get_fault_info(vcpu->arch.fault.esr_el2, &vcpu->arch.fault);
 199 }
 200
 201 static inline void __hyp_sve_restore_guest(struct kvm_vcpu *vcpu)
 202 {
 203         sve_cond_update_zcr_vq(vcpu_sve_max_vq(vcpu) - 1, SYS_ZCR_EL2);
 204         __sve_restore_state(vcpu_sve_pffr(vcpu),
 205                             &vcpu->arch.ctxt.fp_regs.fpsr);
 206         write_sysreg_el1(__vcpu_sys_reg(vcpu, ZCR_EL1), SYS_ZCR);
 207 }
 208
 209 /*
 210  * We trap the first access to the FP/SIMD to save the host context and
 211  * restore the guest context lazily.
 212  * If FP/SIMD is not implemented, handle the trap and inject an undefined
 213  * instruction exception to the guest. Similarly for trapped SVE accesses.
 214  */
 215 static bool kvm_hyp_handle_fpsimd(struct kvm_vcpu *vcpu, u64 *exit_code)
 216 {
 217         bool sve_guest;
 218         u8 esr_ec;
 219         u64 reg;
 220
 221         if (!system_supports_fpsimd())
 222                 return false;
 223
 224         sve_guest = vcpu_has_sve(vcpu);
 225         esr_ec = kvm_vcpu_trap_get_class(vcpu);
 226
 227         /* Only handle traps the vCPU can support here: */
 228         switch (esr_ec) {
 229         case ESR_ELx_EC_FP_ASIMD:
 230                 break;
 231         case ESR_ELx_EC_SVE:
 232                 if (!sve_guest)
 233                         return false;
 234                 break;
 235         default:
 236                 return false;
 237         }
 238
 239         /* Valid trap.  Switch the context: */
 240
 241         /* First disable enough traps to allow us to update the registers */
 242         if (has_vhe() || has_hvhe()) {
 243                 reg = CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN;
 244                 if (sve_guest)
 245                         reg |= CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN;
 246
 247                 sysreg_clear_set(cpacr_el1, 0, reg);
 248         } else {
 249                 reg = CPTR_EL2_TFP;
 250                 if (sve_guest)
 251                         reg |= CPTR_EL2_TZ;
 252
 253                 sysreg_clear_set(cptr_el2, reg, 0);
 254         }
 255         isb();
 256
 257         /* Write out the host state if it's in the registers */
 258         if (vcpu->arch.fp_state == FP_STATE_HOST_OWNED)
 259                 __fpsimd_save_state(vcpu->arch.host_fpsimd_state);
 260
 261         /* Restore the guest state */
 262         if (sve_guest)
 263                 __hyp_sve_restore_guest(vcpu);
 264         else
 265                 __fpsimd_restore_state(&vcpu->arch.ctxt.fp_regs);
 266
 267         /* Skip restoring fpexc32 for AArch64 guests */
 268         if (!(read_sysreg(hcr_el2) & HCR_RW))
 269                 write_sysreg(__vcpu_sys_reg(vcpu, FPEXC32_EL2), fpexc32_el2);
 270
 271         vcpu->arch.fp_state = FP_STATE_GUEST_OWNED;
 272
 273         return true;
 274 }
 275
 276 static inline bool handle_tx2_tvm(struct kvm_vcpu *vcpu)
 277 {
 278         u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
 279         int rt = kvm_vcpu_sys_get_rt(vcpu);
 280         u64 val = vcpu_get_reg(vcpu, rt);
 281
 282         /*
 283          * The normal sysreg handling code expects to see the traps,
 284          * let's not do anything here.
 285          */
 286         if (vcpu->arch.hcr_el2 & HCR_TVM)
 287                 return false;
 288
 289         switch (sysreg) {
 290         case SYS_SCTLR_EL1:
 291                 write_sysreg_el1(val, SYS_SCTLR);
 292                 break;
 293         case SYS_TTBR0_EL1:
 294                 write_sysreg_el1(val, SYS_TTBR0);
 295                 break;
 296         case SYS_TTBR1_EL1:
 297                 write_sysreg_el1(val, SYS_TTBR1);
 298                 break;
 299         case SYS_TCR_EL1:
 300                 write_sysreg_el1(val, SYS_TCR);
 301                 break;
 302         case SYS_ESR_EL1:
 303                 write_sysreg_el1(val, SYS_ESR);
 304                 break;
 305         case SYS_FAR_EL1:
 306                 write_sysreg_el1(val, SYS_FAR);
 307                 break;
 308         case SYS_AFSR0_EL1:
 309                 write_sysreg_el1(val, SYS_AFSR0);
 310                 break;
 311         case SYS_AFSR1_EL1:
 312                 write_sysreg_el1(val, SYS_AFSR1);
 313                 break;
 314         case SYS_MAIR_EL1:
 315                 write_sysreg_el1(val, SYS_MAIR);
 316                 break;
 317         case SYS_AMAIR_EL1:
 318                 write_sysreg_el1(val, SYS_AMAIR);
 319                 break;
 320         case SYS_CONTEXTIDR_EL1:
 321                 write_sysreg_el1(val, SYS_CONTEXTIDR);
 322                 break;
 323         default:
 324                 return false;
 325         }
 326
 327         __kvm_skip_instr(vcpu);
 328         return true;
 329 }
 330
 331 static inline bool esr_is_ptrauth_trap(u64 esr)
 332 {
 333         switch (esr_sys64_to_sysreg(esr)) {
 334         case SYS_APIAKEYLO_EL1:
 335         case SYS_APIAKEYHI_EL1:
 336         case SYS_APIBKEYLO_EL1:
 337         case SYS_APIBKEYHI_EL1:
 338         case SYS_APDAKEYLO_EL1:
 339         case SYS_APDAKEYHI_EL1:
 340         case SYS_APDBKEYLO_EL1:
 341         case SYS_APDBKEYHI_EL1:
 342         case SYS_APGAKEYLO_EL1:
 343         case SYS_APGAKEYHI_EL1:
 344                 return true;
 345         }
 346
 347         return false;
 348 }
 349
 350 #define __ptrauth_save_key(ctxt, key)                                   \
 351         do {                                                            \
 352         u64 __val;                                                      \
 353         __val = read_sysreg_s(SYS_ ## key ## KEYLO_EL1);                \
 354         ctxt_sys_reg(ctxt, key ## KEYLO_EL1) = __val;                   \
 355         __val = read_sysreg_s(SYS_ ## key ## KEYHI_EL1);                \
 356         ctxt_sys_reg(ctxt, key ## KEYHI_EL1) = __val;                   \
 357 } while(0)
 358
 359 DECLARE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt);
 360
 361 static bool kvm_hyp_handle_ptrauth(struct kvm_vcpu *vcpu, u64 *exit_code)
 362 {
 363         struct kvm_cpu_context *ctxt;
 364         u64 val;
 365
 366         if (!vcpu_has_ptrauth(vcpu))
 367                 return false;
 368
 369         ctxt = this_cpu_ptr(&kvm_hyp_ctxt);
 370         __ptrauth_save_key(ctxt, APIA);
 371         __ptrauth_save_key(ctxt, APIB);
 372         __ptrauth_save_key(ctxt, APDA);
 373         __ptrauth_save_key(ctxt, APDB);
 374         __ptrauth_save_key(ctxt, APGA);
 375
 376         vcpu_ptrauth_enable(vcpu);
 377
 378         val = read_sysreg(hcr_el2);
 379         val |= (HCR_API | HCR_APK);
 380         write_sysreg(val, hcr_el2);
 381
 382         return true;
 383 }
 384
 385 static bool kvm_hyp_handle_cntpct(struct kvm_vcpu *vcpu)
 386 {
 387         struct arch_timer_context *ctxt;
 388         u32 sysreg;
 389         u64 val;
 390
 391         /*
 392          * We only get here for 64bit guests, 32bit guests will hit
 393          * the long and winding road all the way to the standard
 394          * handling. Yes, it sucks to be irrelevant.
 395          */
 396         sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
 397
 398         switch (sysreg) {
 399         case SYS_CNTPCT_EL0:
 400         case SYS_CNTPCTSS_EL0:
 401                 if (vcpu_has_nv(vcpu)) {
 402                         if (is_hyp_ctxt(vcpu)) {
 403                                 ctxt = vcpu_hptimer(vcpu);
 404                                 break;
 405                         }
 406
 407                         /* Check for guest hypervisor trapping */
 408                         val = __vcpu_sys_reg(vcpu, CNTHCTL_EL2);
 409                         if (!vcpu_el2_e2h_is_set(vcpu))
 410                                 val = (val & CNTHCTL_EL1PCTEN) << 10;
 411
 412                         if (!(val & (CNTHCTL_EL1PCTEN << 10)))
 413                                 return false;
 414                 }
 415
 416                 ctxt = vcpu_ptimer(vcpu);
 417                 break;
 418         default:
 419                 return false;
 420         }
 421
 422         val = arch_timer_read_cntpct_el0();
 423
 424         if (ctxt->offset.vm_offset)
 425                 val -= *kern_hyp_va(ctxt->offset.vm_offset);
 426         if (ctxt->offset.vcpu_offset)
 427                 val -= *kern_hyp_va(ctxt->offset.vcpu_offset);
 428
 429         vcpu_set_reg(vcpu, kvm_vcpu_sys_get_rt(vcpu), val);
 430         __kvm_skip_instr(vcpu);
 431         return true;
 432 }
 433
 434 static bool handle_ampere1_tcr(struct kvm_vcpu *vcpu)
 435 {
 436         u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
 437         int rt = kvm_vcpu_sys_get_rt(vcpu);
 438         u64 val = vcpu_get_reg(vcpu, rt);
 439
 440         if (sysreg != SYS_TCR_EL1)
 441                 return false;
 442
 443         /*
 444          * Affected parts do not advertise support for hardware Access Flag /
 445          * Dirty state management in ID_AA64MMFR1_EL1.HAFDBS, but the underlying
 446          * control bits are still functional. The architecture requires these be
 447          * RES0 on systems that do not implement FEAT_HAFDBS.
 448          *
 449          * Uphold the requirements of the architecture by masking guest writes
 450          * to TCR_EL1.{HA,HD} here.
 451          */
 452         val &= ~(TCR_HD | TCR_HA);
 453         write_sysreg_el1(val, SYS_TCR);
 454         return true;
 455 }
 456
 457 static bool kvm_hyp_handle_sysreg(struct kvm_vcpu *vcpu, u64 *exit_code)
 458 {
 459         if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM) &&
 460             handle_tx2_tvm(vcpu))
 461                 return true;
 462
 463         if (cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38) &&
 464             handle_ampere1_tcr(vcpu))
 465                 return true;
 466
 467         if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
 468             __vgic_v3_perform_cpuif_access(vcpu) == 1)
 469                 return true;
 470
 471         if (esr_is_ptrauth_trap(kvm_vcpu_get_esr(vcpu)))
 472                 return kvm_hyp_handle_ptrauth(vcpu, exit_code);
 473
 474         if (kvm_hyp_handle_cntpct(vcpu))
 475                 return true;
 476
 477         return false;
 478 }
 479
 480 static bool kvm_hyp_handle_cp15_32(struct kvm_vcpu *vcpu, u64 *exit_code)
 481 {
 482         if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
 483             __vgic_v3_perform_cpuif_access(vcpu) == 1)
 484                 return true;
 485
 486         return false;
 487 }
 488
 489 static bool kvm_hyp_handle_memory_fault(struct kvm_vcpu *vcpu, u64 *exit_code)
 490 {
 491         if (!__populate_fault_info(vcpu))
 492                 return true;
 493
 494         return false;
 495 }
 496 static bool kvm_hyp_handle_iabt_low(struct kvm_vcpu *vcpu, u64 *exit_code)
 497         __alias(kvm_hyp_handle_memory_fault);
 498 static bool kvm_hyp_handle_watchpt_low(struct kvm_vcpu *vcpu, u64 *exit_code)
 499         __alias(kvm_hyp_handle_memory_fault);
 500
 501 static bool kvm_hyp_handle_dabt_low(struct kvm_vcpu *vcpu, u64 *exit_code)
 502 {
 503         if (kvm_hyp_handle_memory_fault(vcpu, exit_code))
 504                 return true;
 505
 506         if (static_branch_unlikely(&vgic_v2_cpuif_trap)) {
 507                 bool valid;
 508
 509                 valid = kvm_vcpu_trap_get_fault_type(vcpu) == ESR_ELx_FSC_FAULT &&
 510                         kvm_vcpu_dabt_isvalid(vcpu) &&
 511                         !kvm_vcpu_abt_issea(vcpu) &&
 512                         !kvm_vcpu_abt_iss1tw(vcpu);
 513
 514                 if (valid) {
 515                         int ret = __vgic_v2_perform_cpuif_access(vcpu);
 516
 517                         if (ret == 1)
 518                                 return true;
 519
 520                         /* Promote an illegal access to an SError.*/
 521                         if (ret == -1)
 522                                 *exit_code = ARM_EXCEPTION_EL1_SERROR;
 523                 }
 524         }
 525
 526         return false;
 527 }
 528
 529 typedef bool (*exit_handler_fn)(struct kvm_vcpu *, u64 *);
 530
 531 static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu);
 532
 533 static void early_exit_filter(struct kvm_vcpu *vcpu, u64 *exit_code);
 534
 535 /*
 536  * Allow the hypervisor to handle the exit with an exit handler if it has one.
 537  *
 538  * Returns true if the hypervisor handled the exit, and control should go back
 539  * to the guest, or false if it hasn't.
 540  */
 541 static inline bool kvm_hyp_handle_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
 542 {
 543         const exit_handler_fn *handlers = kvm_get_exit_handler_array(vcpu);
 544         exit_handler_fn fn;
 545
 546         fn = handlers[kvm_vcpu_trap_get_class(vcpu)];
 547
 548         if (fn)
 549                 return fn(vcpu, exit_code);
 550
 551         return false;
 552 }
 553
 554 static inline void synchronize_vcpu_pstate(struct kvm_vcpu *vcpu, u64 *exit_code)
 555 {
 556         /*
 557          * Check for the conditions of Cortex-A510's #2077057. When these occur
 558          * SPSR_EL2 can't be trusted, but isn't needed either as it is
 559          * unchanged from the value in vcpu_gp_regs(vcpu)->pstate.
 560          * Are we single-stepping the guest, and took a PAC exception from the
 561          * active-not-pending state?
 562          */
 563         if (cpus_have_final_cap(ARM64_WORKAROUND_2077057)               &&
 564             vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP                 &&
 565             *vcpu_cpsr(vcpu) & DBG_SPSR_SS                              &&
 566             ESR_ELx_EC(read_sysreg_el2(SYS_ESR)) == ESR_ELx_EC_PAC)
 567                 write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR);
 568
 569         vcpu->arch.ctxt.regs.pstate = read_sysreg_el2(SYS_SPSR);
 570 }
 571
 572 /*
 573  * Return true when we were able to fixup the guest exit and should return to
 574  * the guest, false when we should restore the host state and return to the
 575  * main run loop.
 576  */
 577 static inline bool fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
 578 {
 579         /*
 580          * Save PSTATE early so that we can evaluate the vcpu mode
 581          * early on.
 582          */
 583         synchronize_vcpu_pstate(vcpu, exit_code);
 584
 585         /*
 586          * Check whether we want to repaint the state one way or
 587          * another.
 588          */
 589         early_exit_filter(vcpu, exit_code);
 590
 591         if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ)
 592                 vcpu->arch.fault.esr_el2 = read_sysreg_el2(SYS_ESR);
 593
 594         if (ARM_SERROR_PENDING(*exit_code) &&
 595             ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ) {
 596                 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
 597
 598                 /*
 599                  * HVC already have an adjusted PC, which we need to
 600                  * correct in order to return to after having injected
 601                  * the SError.
 602                  *
 603                  * SMC, on the other hand, is *trapped*, meaning its
 604                  * preferred return address is the SMC itself.
 605                  */
 606                 if (esr_ec == ESR_ELx_EC_HVC32 || esr_ec == ESR_ELx_EC_HVC64)
 607                         write_sysreg_el2(read_sysreg_el2(SYS_ELR) - 4, SYS_ELR);
 608         }
 609
 610         /*
 611          * We're using the raw exception code in order to only process
 612          * the trap if no SError is pending. We will come back to the
 613          * same PC once the SError has been injected, and replay the
 614          * trapping instruction.
 615          */
 616         if (*exit_code != ARM_EXCEPTION_TRAP)
 617                 goto exit;
 618
 619         /* Check if there's an exit handler and allow it to handle the exit. */
 620         if (kvm_hyp_handle_exit(vcpu, exit_code))
 621                 goto guest;
 622 exit:
 623         /* Return to the host kernel and handle the exit */
 624         return false;
 625
 626 guest:
 627         /* Re-enter the guest */
 628         asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));
 629         return true;
 630 }
 631
 632 static inline void __kvm_unexpected_el2_exception(void)
 633 {
 634         extern char __guest_exit_panic[];
 635         unsigned long addr, fixup;
 636         struct kvm_exception_table_entry *entry, *end;
 637         unsigned long elr_el2 = read_sysreg(elr_el2);
 638
 639         entry = &__start___kvm_ex_table;
 640         end = &__stop___kvm_ex_table;
 641
 642         while (entry < end) {
 643                 addr = (unsigned long)&entry->insn + entry->insn;
 644                 fixup = (unsigned long)&entry->fixup + entry->fixup;
 645
 646                 if (addr != elr_el2) {
 647                         entry++;
 648                         continue;
 649                 }
 650
 651                 write_sysreg(fixup, elr_el2);
 652                 return;
 653         }
 654
 655         /* Trigger a panic after restoring the hyp context. */
 656         write_sysreg(__guest_exit_panic, elr_el2);
 657 }
 658
 659 #endif /* __ARM64_KVM_HYP_SWITCH_H__ */