arch/arm64/kvm/hyp/include/hyp/switch.h

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 - ARM Ltd
   4  * Author: Marc Zyngier <marc.zyngier@arm.com>
   5  */
   6
   7 #ifndef __ARM64_KVM_HYP_SWITCH_H__
   8 #define __ARM64_KVM_HYP_SWITCH_H__
   9
  10 #include <hyp/adjust_pc.h>
  11 #include <hyp/fault.h>
  12
  13 #include <linux/arm-smccc.h>
  14 #include <linux/kvm_host.h>
  15 #include <linux/types.h>
  16 #include <linux/jump_label.h>
  17 #include <uapi/linux/psci.h>
  18
  19 #include <kvm/arm_psci.h>
  20
  21 #include <asm/barrier.h>
  22 #include <asm/cpufeature.h>
  23 #include <asm/extable.h>
  24 #include <asm/kprobes.h>
  25 #include <asm/kvm_asm.h>
  26 #include <asm/kvm_emulate.h>
  27 #include <asm/kvm_hyp.h>
  28 #include <asm/kvm_mmu.h>
  29 #include <asm/kvm_nested.h>
  30 #include <asm/fpsimd.h>
  31 #include <asm/debug-monitors.h>
  32 #include <asm/processor.h>
  33
  34 struct kvm_exception_table_entry {
  35         int insn, fixup;
  36 };
  37
  38 extern struct kvm_exception_table_entry __start___kvm_ex_table;
  39 extern struct kvm_exception_table_entry __stop___kvm_ex_table;
  40
  41 /* Check whether the FP regs are owned by the guest */
  42 static inline bool guest_owns_fp_regs(struct kvm_vcpu *vcpu)
  43 {
  44         return vcpu->arch.fp_state == FP_STATE_GUEST_OWNED;
  45 }
  46
  47 /* Save the 32-bit only FPSIMD system register state */
  48 static inline void __fpsimd_save_fpexc32(struct kvm_vcpu *vcpu)
  49 {
  50         if (!vcpu_el1_is_32bit(vcpu))
  51                 return;
  52
  53         __vcpu_sys_reg(vcpu, FPEXC32_EL2) = read_sysreg(fpexc32_el2);
  54 }
  55
  56 static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
  57 {
  58         /*
  59          * We are about to set CPTR_EL2.TFP to trap all floating point
  60          * register accesses to EL2, however, the ARM ARM clearly states that
  61          * traps are only taken to EL2 if the operation would not otherwise
  62          * trap to EL1.  Therefore, always make sure that for 32-bit guests,
  63          * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
  64          * If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to
  65          * it will cause an exception.
  66          */
  67         if (vcpu_el1_is_32bit(vcpu) && system_supports_fpsimd()) {
  68                 write_sysreg(1 << 30, fpexc32_el2);
  69                 isb();
  70         }
  71 }
  72
  73 static inline void __activate_traps_common(struct kvm_vcpu *vcpu)
  74 {
  75         /* Trap on AArch32 cp15 c15 (impdef sysregs) accesses (EL1 or EL0) */
  76         write_sysreg(1 << 15, hstr_el2);
  77
  78         /*
  79          * Make sure we trap PMU access from EL0 to EL2. Also sanitize
  80          * PMSELR_EL0 to make sure it never contains the cycle
  81          * counter, which could make a PMXEVCNTR_EL0 access UNDEF at
  82          * EL1 instead of being trapped to EL2.
  83          */
  84         if (kvm_arm_support_pmu_v3()) {
  85                 write_sysreg(0, pmselr_el0);
  86                 write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
  87         }
  88
  89         vcpu->arch.mdcr_el2_host = read_sysreg(mdcr_el2);
  90         write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
  91
  92         if (cpus_have_final_cap(ARM64_SME)) {
  93                 sysreg_clear_set_s(SYS_HFGRTR_EL2,
  94                                    HFGxTR_EL2_nSMPRI_EL1_MASK |
  95                                    HFGxTR_EL2_nTPIDR2_EL0_MASK,
  96                                    0);
  97                 sysreg_clear_set_s(SYS_HFGWTR_EL2,
  98                                    HFGxTR_EL2_nSMPRI_EL1_MASK |
  99                                    HFGxTR_EL2_nTPIDR2_EL0_MASK,
 100                                    0);
 101         }
 102 }
 103
 104 static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu)
 105 {
 106         write_sysreg(vcpu->arch.mdcr_el2_host, mdcr_el2);
 107
 108         write_sysreg(0, hstr_el2);
 109         if (kvm_arm_support_pmu_v3())
 110                 write_sysreg(0, pmuserenr_el0);
 111
 112         if (cpus_have_final_cap(ARM64_SME)) {
 113                 sysreg_clear_set_s(SYS_HFGRTR_EL2, 0,
 114                                    HFGxTR_EL2_nSMPRI_EL1_MASK |
 115                                    HFGxTR_EL2_nTPIDR2_EL0_MASK);
 116                 sysreg_clear_set_s(SYS_HFGWTR_EL2, 0,
 117                                    HFGxTR_EL2_nSMPRI_EL1_MASK |
 118                                    HFGxTR_EL2_nTPIDR2_EL0_MASK);
 119         }
 120 }
 121
 122 static inline void ___activate_traps(struct kvm_vcpu *vcpu)
 123 {
 124         u64 hcr = vcpu->arch.hcr_el2;
 125
 126         if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM))
 127                 hcr |= HCR_TVM;
 128
 129         write_sysreg(hcr, hcr_el2);
 130
 131         if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE))
 132                 write_sysreg_s(vcpu->arch.vsesr_el2, SYS_VSESR_EL2);
 133 }
 134
 135 static inline void ___deactivate_traps(struct kvm_vcpu *vcpu)
 136 {
 137         /*
 138          * If we pended a virtual abort, preserve it until it gets
 139          * cleared. See D1.14.3 (Virtual Interrupts) for details, but
 140          * the crucial bit is "On taking a vSError interrupt,
 141          * HCR_EL2.VSE is cleared to 0."
 142          */
 143         if (vcpu->arch.hcr_el2 & HCR_VSE) {
 144                 vcpu->arch.hcr_el2 &= ~HCR_VSE;
 145                 vcpu->arch.hcr_el2 |= read_sysreg(hcr_el2) & HCR_VSE;
 146         }
 147 }
 148
 149 static inline bool __populate_fault_info(struct kvm_vcpu *vcpu)
 150 {
 151         return __get_fault_info(vcpu->arch.fault.esr_el2, &vcpu->arch.fault);
 152 }
 153
 154 static inline void __hyp_sve_restore_guest(struct kvm_vcpu *vcpu)
 155 {
 156         sve_cond_update_zcr_vq(vcpu_sve_max_vq(vcpu) - 1, SYS_ZCR_EL2);
 157         __sve_restore_state(vcpu_sve_pffr(vcpu),
 158                             &vcpu->arch.ctxt.fp_regs.fpsr);
 159         write_sysreg_el1(__vcpu_sys_reg(vcpu, ZCR_EL1), SYS_ZCR);
 160 }
 161
 162 /*
 163  * We trap the first access to the FP/SIMD to save the host context and
 164  * restore the guest context lazily.
 165  * If FP/SIMD is not implemented, handle the trap and inject an undefined
 166  * instruction exception to the guest. Similarly for trapped SVE accesses.
 167  */
 168 static bool kvm_hyp_handle_fpsimd(struct kvm_vcpu *vcpu, u64 *exit_code)
 169 {
 170         bool sve_guest;
 171         u8 esr_ec;
 172         u64 reg;
 173
 174         if (!system_supports_fpsimd())
 175                 return false;
 176
 177         sve_guest = vcpu_has_sve(vcpu);
 178         esr_ec = kvm_vcpu_trap_get_class(vcpu);
 179
 180         /* Only handle traps the vCPU can support here: */
 181         switch (esr_ec) {
 182         case ESR_ELx_EC_FP_ASIMD:
 183                 break;
 184         case ESR_ELx_EC_SVE:
 185                 if (!sve_guest)
 186                         return false;
 187                 break;
 188         default:
 189                 return false;
 190         }
 191
 192         /* Valid trap.  Switch the context: */
 193
 194         /* First disable enough traps to allow us to update the registers */
 195         if (has_vhe() || has_hvhe()) {
 196                 reg = CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN;
 197                 if (sve_guest)
 198                         reg |= CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN;
 199
 200                 sysreg_clear_set(cpacr_el1, 0, reg);
 201         } else {
 202                 reg = CPTR_EL2_TFP;
 203                 if (sve_guest)
 204                         reg |= CPTR_EL2_TZ;
 205
 206                 sysreg_clear_set(cptr_el2, reg, 0);
 207         }
 208         isb();
 209
 210         /* Write out the host state if it's in the registers */
 211         if (vcpu->arch.fp_state == FP_STATE_HOST_OWNED)
 212                 __fpsimd_save_state(vcpu->arch.host_fpsimd_state);
 213
 214         /* Restore the guest state */
 215         if (sve_guest)
 216                 __hyp_sve_restore_guest(vcpu);
 217         else
 218                 __fpsimd_restore_state(&vcpu->arch.ctxt.fp_regs);
 219
 220         /* Skip restoring fpexc32 for AArch64 guests */
 221         if (!(read_sysreg(hcr_el2) & HCR_RW))
 222                 write_sysreg(__vcpu_sys_reg(vcpu, FPEXC32_EL2), fpexc32_el2);
 223
 224         vcpu->arch.fp_state = FP_STATE_GUEST_OWNED;
 225
 226         return true;
 227 }
 228
 229 static inline bool handle_tx2_tvm(struct kvm_vcpu *vcpu)
 230 {
 231         u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
 232         int rt = kvm_vcpu_sys_get_rt(vcpu);
 233         u64 val = vcpu_get_reg(vcpu, rt);
 234
 235         /*
 236          * The normal sysreg handling code expects to see the traps,
 237          * let's not do anything here.
 238          */
 239         if (vcpu->arch.hcr_el2 & HCR_TVM)
 240                 return false;
 241
 242         switch (sysreg) {
 243         case SYS_SCTLR_EL1:
 244                 write_sysreg_el1(val, SYS_SCTLR);
 245                 break;
 246         case SYS_TTBR0_EL1:
 247                 write_sysreg_el1(val, SYS_TTBR0);
 248                 break;
 249         case SYS_TTBR1_EL1:
 250                 write_sysreg_el1(val, SYS_TTBR1);
 251                 break;
 252         case SYS_TCR_EL1:
 253                 write_sysreg_el1(val, SYS_TCR);
 254                 break;
 255         case SYS_ESR_EL1:
 256                 write_sysreg_el1(val, SYS_ESR);
 257                 break;
 258         case SYS_FAR_EL1:
 259                 write_sysreg_el1(val, SYS_FAR);
 260                 break;
 261         case SYS_AFSR0_EL1:
 262                 write_sysreg_el1(val, SYS_AFSR0);
 263                 break;
 264         case SYS_AFSR1_EL1:
 265                 write_sysreg_el1(val, SYS_AFSR1);
 266                 break;
 267         case SYS_MAIR_EL1:
 268                 write_sysreg_el1(val, SYS_MAIR);
 269                 break;
 270         case SYS_AMAIR_EL1:
 271                 write_sysreg_el1(val, SYS_AMAIR);
 272                 break;
 273         case SYS_CONTEXTIDR_EL1:
 274                 write_sysreg_el1(val, SYS_CONTEXTIDR);
 275                 break;
 276         default:
 277                 return false;
 278         }
 279
 280         __kvm_skip_instr(vcpu);
 281         return true;
 282 }
 283
 284 static inline bool esr_is_ptrauth_trap(u64 esr)
 285 {
 286         switch (esr_sys64_to_sysreg(esr)) {
 287         case SYS_APIAKEYLO_EL1:
 288         case SYS_APIAKEYHI_EL1:
 289         case SYS_APIBKEYLO_EL1:
 290         case SYS_APIBKEYHI_EL1:
 291         case SYS_APDAKEYLO_EL1:
 292         case SYS_APDAKEYHI_EL1:
 293         case SYS_APDBKEYLO_EL1:
 294         case SYS_APDBKEYHI_EL1:
 295         case SYS_APGAKEYLO_EL1:
 296         case SYS_APGAKEYHI_EL1:
 297                 return true;
 298         }
 299
 300         return false;
 301 }
 302
 303 #define __ptrauth_save_key(ctxt, key)                                   \
 304         do {                                                            \
 305         u64 __val;                                                      \
 306         __val = read_sysreg_s(SYS_ ## key ## KEYLO_EL1);                \
 307         ctxt_sys_reg(ctxt, key ## KEYLO_EL1) = __val;                   \
 308         __val = read_sysreg_s(SYS_ ## key ## KEYHI_EL1);                \
 309         ctxt_sys_reg(ctxt, key ## KEYHI_EL1) = __val;                   \
 310 } while(0)
 311
 312 DECLARE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt);
 313
 314 static bool kvm_hyp_handle_ptrauth(struct kvm_vcpu *vcpu, u64 *exit_code)
 315 {
 316         struct kvm_cpu_context *ctxt;
 317         u64 val;
 318
 319         if (!vcpu_has_ptrauth(vcpu))
 320                 return false;
 321
 322         ctxt = this_cpu_ptr(&kvm_hyp_ctxt);
 323         __ptrauth_save_key(ctxt, APIA);
 324         __ptrauth_save_key(ctxt, APIB);
 325         __ptrauth_save_key(ctxt, APDA);
 326         __ptrauth_save_key(ctxt, APDB);
 327         __ptrauth_save_key(ctxt, APGA);
 328
 329         vcpu_ptrauth_enable(vcpu);
 330
 331         val = read_sysreg(hcr_el2);
 332         val |= (HCR_API | HCR_APK);
 333         write_sysreg(val, hcr_el2);
 334
 335         return true;
 336 }
 337
 338 static bool kvm_hyp_handle_cntpct(struct kvm_vcpu *vcpu)
 339 {
 340         struct arch_timer_context *ctxt;
 341         u32 sysreg;
 342         u64 val;
 343
 344         /*
 345          * We only get here for 64bit guests, 32bit guests will hit
 346          * the long and winding road all the way to the standard
 347          * handling. Yes, it sucks to be irrelevant.
 348          */
 349         sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
 350
 351         switch (sysreg) {
 352         case SYS_CNTPCT_EL0:
 353         case SYS_CNTPCTSS_EL0:
 354                 if (vcpu_has_nv(vcpu)) {
 355                         if (is_hyp_ctxt(vcpu)) {
 356                                 ctxt = vcpu_hptimer(vcpu);
 357                                 break;
 358                         }
 359
 360                         /* Check for guest hypervisor trapping */
 361                         val = __vcpu_sys_reg(vcpu, CNTHCTL_EL2);
 362                         if (!vcpu_el2_e2h_is_set(vcpu))
 363                                 val = (val & CNTHCTL_EL1PCTEN) << 10;
 364
 365                         if (!(val & (CNTHCTL_EL1PCTEN << 10)))
 366                                 return false;
 367                 }
 368
 369                 ctxt = vcpu_ptimer(vcpu);
 370                 break;
 371         default:
 372                 return false;
 373         }
 374
 375         val = arch_timer_read_cntpct_el0();
 376
 377         if (ctxt->offset.vm_offset)
 378                 val -= *kern_hyp_va(ctxt->offset.vm_offset);
 379         if (ctxt->offset.vcpu_offset)
 380                 val -= *kern_hyp_va(ctxt->offset.vcpu_offset);
 381
 382         vcpu_set_reg(vcpu, kvm_vcpu_sys_get_rt(vcpu), val);
 383         __kvm_skip_instr(vcpu);
 384         return true;
 385 }
 386
 387 static bool kvm_hyp_handle_sysreg(struct kvm_vcpu *vcpu, u64 *exit_code)
 388 {
 389         if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM) &&
 390             handle_tx2_tvm(vcpu))
 391                 return true;
 392
 393         if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
 394             __vgic_v3_perform_cpuif_access(vcpu) == 1)
 395                 return true;
 396
 397         if (esr_is_ptrauth_trap(kvm_vcpu_get_esr(vcpu)))
 398                 return kvm_hyp_handle_ptrauth(vcpu, exit_code);
 399
 400         if (kvm_hyp_handle_cntpct(vcpu))
 401                 return true;
 402
 403         return false;
 404 }
 405
 406 static bool kvm_hyp_handle_cp15_32(struct kvm_vcpu *vcpu, u64 *exit_code)
 407 {
 408         if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
 409             __vgic_v3_perform_cpuif_access(vcpu) == 1)
 410                 return true;
 411
 412         return false;
 413 }
 414
 415 static bool kvm_hyp_handle_iabt_low(struct kvm_vcpu *vcpu, u64 *exit_code)
 416 {
 417         if (!__populate_fault_info(vcpu))
 418                 return true;
 419
 420         return false;
 421 }
 422
 423 static bool kvm_hyp_handle_dabt_low(struct kvm_vcpu *vcpu, u64 *exit_code)
 424 {
 425         if (!__populate_fault_info(vcpu))
 426                 return true;
 427
 428         if (static_branch_unlikely(&vgic_v2_cpuif_trap)) {
 429                 bool valid;
 430
 431                 valid = kvm_vcpu_trap_get_fault_type(vcpu) == ESR_ELx_FSC_FAULT &&
 432                         kvm_vcpu_dabt_isvalid(vcpu) &&
 433                         !kvm_vcpu_abt_issea(vcpu) &&
 434                         !kvm_vcpu_abt_iss1tw(vcpu);
 435
 436                 if (valid) {
 437                         int ret = __vgic_v2_perform_cpuif_access(vcpu);
 438
 439                         if (ret == 1)
 440                                 return true;
 441
 442                         /* Promote an illegal access to an SError.*/
 443                         if (ret == -1)
 444                                 *exit_code = ARM_EXCEPTION_EL1_SERROR;
 445                 }
 446         }
 447
 448         return false;
 449 }
 450
 451 typedef bool (*exit_handler_fn)(struct kvm_vcpu *, u64 *);
 452
 453 static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu);
 454
 455 static void early_exit_filter(struct kvm_vcpu *vcpu, u64 *exit_code);
 456
 457 /*
 458  * Allow the hypervisor to handle the exit with an exit handler if it has one.
 459  *
 460  * Returns true if the hypervisor handled the exit, and control should go back
 461  * to the guest, or false if it hasn't.
 462  */
 463 static inline bool kvm_hyp_handle_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
 464 {
 465         const exit_handler_fn *handlers = kvm_get_exit_handler_array(vcpu);
 466         exit_handler_fn fn;
 467
 468         fn = handlers[kvm_vcpu_trap_get_class(vcpu)];
 469
 470         if (fn)
 471                 return fn(vcpu, exit_code);
 472
 473         return false;
 474 }
 475
 476 static inline void synchronize_vcpu_pstate(struct kvm_vcpu *vcpu, u64 *exit_code)
 477 {
 478         /*
 479          * Check for the conditions of Cortex-A510's #2077057. When these occur
 480          * SPSR_EL2 can't be trusted, but isn't needed either as it is
 481          * unchanged from the value in vcpu_gp_regs(vcpu)->pstate.
 482          * Are we single-stepping the guest, and took a PAC exception from the
 483          * active-not-pending state?
 484          */
 485         if (cpus_have_final_cap(ARM64_WORKAROUND_2077057)               &&
 486             vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP                 &&
 487             *vcpu_cpsr(vcpu) & DBG_SPSR_SS                              &&
 488             ESR_ELx_EC(read_sysreg_el2(SYS_ESR)) == ESR_ELx_EC_PAC)
 489                 write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR);
 490
 491         vcpu->arch.ctxt.regs.pstate = read_sysreg_el2(SYS_SPSR);
 492 }
 493
 494 /*
 495  * Return true when we were able to fixup the guest exit and should return to
 496  * the guest, false when we should restore the host state and return to the
 497  * main run loop.
 498  */
 499 static inline bool fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
 500 {
 501         /*
 502          * Save PSTATE early so that we can evaluate the vcpu mode
 503          * early on.
 504          */
 505         synchronize_vcpu_pstate(vcpu, exit_code);
 506
 507         /*
 508          * Check whether we want to repaint the state one way or
 509          * another.
 510          */
 511         early_exit_filter(vcpu, exit_code);
 512
 513         if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ)
 514                 vcpu->arch.fault.esr_el2 = read_sysreg_el2(SYS_ESR);
 515
 516         if (ARM_SERROR_PENDING(*exit_code) &&
 517             ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ) {
 518                 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
 519
 520                 /*
 521                  * HVC already have an adjusted PC, which we need to
 522                  * correct in order to return to after having injected
 523                  * the SError.
 524                  *
 525                  * SMC, on the other hand, is *trapped*, meaning its
 526                  * preferred return address is the SMC itself.
 527                  */
 528                 if (esr_ec == ESR_ELx_EC_HVC32 || esr_ec == ESR_ELx_EC_HVC64)
 529                         write_sysreg_el2(read_sysreg_el2(SYS_ELR) - 4, SYS_ELR);
 530         }
 531
 532         /*
 533          * We're using the raw exception code in order to only process
 534          * the trap if no SError is pending. We will come back to the
 535          * same PC once the SError has been injected, and replay the
 536          * trapping instruction.
 537          */
 538         if (*exit_code != ARM_EXCEPTION_TRAP)
 539                 goto exit;
 540
 541         /* Check if there's an exit handler and allow it to handle the exit. */
 542         if (kvm_hyp_handle_exit(vcpu, exit_code))
 543                 goto guest;
 544 exit:
 545         /* Return to the host kernel and handle the exit */
 546         return false;
 547
 548 guest:
 549         /* Re-enter the guest */
 550         asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));
 551         return true;
 552 }
 553
 554 static inline void __kvm_unexpected_el2_exception(void)
 555 {
 556         extern char __guest_exit_panic[];
 557         unsigned long addr, fixup;
 558         struct kvm_exception_table_entry *entry, *end;
 559         unsigned long elr_el2 = read_sysreg(elr_el2);
 560
 561         entry = &__start___kvm_ex_table;
 562         end = &__stop___kvm_ex_table;
 563
 564         while (entry < end) {
 565                 addr = (unsigned long)&entry->insn + entry->insn;
 566                 fixup = (unsigned long)&entry->fixup + entry->fixup;
 567
 568                 if (addr != elr_el2) {
 569                         entry++;
 570                         continue;
 571                 }
 572
 573                 write_sysreg(fixup, elr_el2);
 574                 return;
 575         }
 576
 577         /* Trigger a panic after restoring the hyp context. */
 578         write_sysreg(__guest_exit_panic, elr_el2);
 579 }
 580
 581 #endif /* __ARM64_KVM_HYP_SWITCH_H__ */